forked from OSchip/llvm-project
[X86] add an exedepfix entry for movq == movlps == movlpd
This is a 1-line patch (with a TODO for AVX because that will affect even more regression tests) that lets us substitute the appropriate 64-bit store for the float/double/int domains. It's not clear to me exactly what the difference is between the 0xD6 (MOVPQI2QImr) and 0x7E (MOVSDto64mr) opcodes, but this is apparently the right choice. Differential Revision: http://reviews.llvm.org/D8691 llvm-svn: 235014
This commit is contained in:
Sanjay Patel
parent
fa990f0338
commit
c03d93baa0
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@ -5999,6 +5999,7 @@ static const uint16_t ReplaceableInstrs[][3] = {
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{ X86::MOVAPSrr, X86::MOVAPDrr, X86::MOVDQArr },
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{ X86::MOVUPSmr, X86::MOVUPDmr, X86::MOVDQUmr },
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{ X86::MOVUPSrm, X86::MOVUPDrm, X86::MOVDQUrm },
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{ X86::MOVLPSmr, X86::MOVLPDmr, X86::MOVPQI2QImr },
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{ X86::MOVNTPSmr, X86::MOVNTPDmr, X86::MOVNTDQmr },
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{ X86::ANDNPSrm, X86::ANDNPDrm, X86::PANDNrm },
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{ X86::ANDNPSrr, X86::ANDNPDrr, X86::PANDNrr },
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@ -6014,6 +6015,7 @@ static const uint16_t ReplaceableInstrs[][3] = {
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{ X86::VMOVAPSrr, X86::VMOVAPDrr, X86::VMOVDQArr },
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{ X86::VMOVUPSmr, X86::VMOVUPDmr, X86::VMOVDQUmr },
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{ X86::VMOVUPSrm, X86::VMOVUPDrm, X86::VMOVDQUrm },
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// TODO: Add the AVX versions of MOVLPSmr
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{ X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
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{ X86::VANDNPSrm, X86::VANDNPDrm, X86::VPANDNrm },
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{ X86::VANDNPSrr, X86::VANDNPDrr, X86::VPANDNrr },
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@ -26,7 +26,7 @@ entry:
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}
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; CHECK-LABEL: zero_test
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; CHECK: pxor %xmm0, %xmm0
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; CHECK: xorps %xmm0, %xmm0
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; CHECK: ret
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define void @zero_test() {
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@ -6,7 +6,7 @@ entry:
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; CHECK: pmovzxwd
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%A27 = load <4 x i16>, <4 x i16>* %in, align 4
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%A28 = add <4 x i16> %A27, %A27
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; CHECK: movlpd
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; CHECK: movq
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store <4 x i16> %A28, <4 x i16>* %in, align 4
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ret void
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; CHECK: ret
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@ -18,7 +18,7 @@ define void @store_64(<2 x i32>* %ptr) {
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BB:
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store <2 x i32> zeroinitializer, <2 x i32>* %ptr
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ret void
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;CHECK: movlpd
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;CHECK: movlps
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;CHECK: ret
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}
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@ -0,0 +1,73 @@
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=sse2 | FileCheck %s --check-prefix=SSE
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx | FileCheck %s --check-prefix=AVX
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; Verify that we select the correct version of the instruction that stores the low 64-bits
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; of a 128-bit vector. We want to avoid int/fp domain crossing penalties, so ignore the
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; bitcast ops and choose:
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;
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; movlps for floats
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; movlpd for doubles
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; movq for integers
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define void @store_floats(<4 x float> %x, i64* %p) {
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; SSE-LABEL: store_floats:
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; SSE: # BB#0:
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; SSE-NEXT: addps %xmm0, %xmm0
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; SSE-NEXT: movlps %xmm0, (%rdi)
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; SSE-NEXT: retq
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;
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; AVX-LABEL: store_floats:
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; AVX: # BB#0:
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; AVX-NEXT: vaddps %xmm0, %xmm0, %xmm0
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; !!! FIXME - the AVX version is not handled correctly.
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; AVX-NEXT: vmovq %xmm0, (%rdi)
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; AVX-NEXT: retq
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%a = fadd <4 x float> %x, %x
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%b = shufflevector <4 x float> %a, <4 x float> undef, <2 x i32> <i32 0, i32 1>
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%c = bitcast <2 x float> %b to i64
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store i64 %c, i64* %p
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ret void
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}
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define void @store_double(<2 x double> %x, i64* %p) {
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; SSE-LABEL: store_double:
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; SSE: # BB#0:
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; SSE-NEXT: addpd %xmm0, %xmm0
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; SSE-NEXT: movlpd %xmm0, (%rdi)
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; SSE-NEXT: retq
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;
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; AVX-LABEL: store_double:
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; AVX: # BB#0:
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; AVX-NEXT: vaddpd %xmm0, %xmm0, %xmm0
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; AVX-NEXT: vmovlpd %xmm0, (%rdi)
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; AVX-NEXT: retq
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%a = fadd <2 x double> %x, %x
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%b = extractelement <2 x double> %a, i32 0
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%c = bitcast double %b to i64
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store i64 %c, i64* %p
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ret void
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}
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define void @store_int(<4 x i32> %x, <2 x float>* %p) {
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; SSE-LABEL: store_int:
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; SSE: # BB#0:
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; SSE-NEXT: paddd %xmm0, %xmm0
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; SSE-NEXT: movq %xmm0, (%rdi)
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; SSE-NEXT: retq
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;
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; AVX-LABEL: store_int:
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; AVX: # BB#0:
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; AVX-NEXT: vpaddd %xmm0, %xmm0, %xmm0
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; AVX-NEXT: vmovq %xmm0, (%rdi)
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; AVX-NEXT: retq
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%a = add <4 x i32> %x, %x
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%b = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 0, i32 1>
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%c = bitcast <2 x i32> %b to <2 x float>
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store <2 x float> %c, <2 x float>* %p
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ret void
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}
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@ -581,7 +581,7 @@ declare <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double>) nounwind readnone
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define void @test_x86_sse2_storel_dq(i8* %a0, <4 x i32> %a1) {
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; CHECK: test_x86_sse2_storel_dq
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; CHECK: movl
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; CHECK: movq
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; CHECK: movlps
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call void @llvm.x86.sse2.storel.dq(i8* %a0, <4 x i32> %a1)
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ret void
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}
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@ -9,7 +9,7 @@ define void @t1(i32 %a, x86_mmx* %P) nounwind {
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; CHECK-NEXT: shll $12, %ecx
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; CHECK-NEXT: movd %ecx, %xmm0
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; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,0,1,1]
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; CHECK-NEXT: movlpd %xmm0, (%eax)
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; CHECK-NEXT: movq %xmm0, (%eax)
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; CHECK-NEXT: retl
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%tmp12 = shl i32 %a, 12
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%tmp21 = insertelement <2 x i32> undef, i32 %tmp12, i32 1
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@ -7,7 +7,7 @@ define x86_mmx @t0(i32 %A) nounwind {
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; X86-32: ## BB#0:
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; X86-32: movd {{[0-9]+}}(%esp), %xmm0
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; X86-32-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,0,1,1]
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; X86-32-NEXT: movlpd %xmm0, (%esp)
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; X86-32-NEXT: movq %xmm0, (%esp)
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; X86-32-NEXT: movq (%esp), %mm0
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; X86-32-NEXT: addl $12, %esp
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; X86-32-NEXT: retl
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@ -9,7 +9,7 @@
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define void @test1() {
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;CHECK-LABEL: @test1
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;CHECK: xorpd
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;CHECK: xorps
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store <1 x i64> zeroinitializer, <1 x i64>* @M1
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store <2 x i32> zeroinitializer, <2 x i32>* @M2
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ret void
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@ -9,7 +9,7 @@ define void @test0(<1 x i64>* %x) {
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
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; X32-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,2,3]
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; X32-NEXT: movlpd %xmm0, (%eax)
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; X32-NEXT: movq %xmm0, (%eax)
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; X32-NEXT: retl
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;
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; X64-LABEL: test0:
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@ -38,13 +38,13 @@ define void @test1() {
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; X32-NEXT: .cfi_def_cfa_offset 24
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; X32-NEXT: Ltmp2:
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; X32-NEXT: .cfi_offset %edi, -8
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; X32-NEXT: xorpd %xmm0, %xmm0
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; X32-NEXT: movlpd %xmm0, (%esp)
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; X32-NEXT: xorps %xmm0, %xmm0
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; X32-NEXT: movlps %xmm0, (%esp)
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; X32-NEXT: movq (%esp), %mm0
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; X32-NEXT: pshuflw {{.*#+}} xmm0 = mem[0,2,2,3,4,5,6,7]
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; X32-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,6,6,7]
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; X32-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
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; X32-NEXT: movlpd %xmm0, {{[0-9]+}}(%esp)
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; X32-NEXT: movq %xmm0, {{[0-9]+}}(%esp)
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; X32-NEXT: movq {{[0-9]+}}(%esp), %mm1
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; X32-NEXT: xorl %edi, %edi
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; X32-NEXT: maskmovq %mm1, %mm0
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@ -54,8 +54,8 @@ define void @test1() {
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;
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; X64-LABEL: test1:
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; X64: ## BB#0: ## %entry
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; X64-NEXT: pxor %xmm0, %xmm0
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; X64-NEXT: movq %xmm0, -{{[0-9]+}}(%rsp)
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; X64-NEXT: xorps %xmm0, %xmm0
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; X64-NEXT: movlps %xmm0, -{{[0-9]+}}(%rsp)
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; X64-NEXT: movq -{{[0-9]+}}(%rsp), %mm0
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; X64-NEXT: pshuflw {{.*#+}} xmm0 = mem[0,2,2,3,4,5,6,7]
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; X64-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,6,6,7]
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@ -3,12 +3,14 @@
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; CHECK: movl
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; CHECK: paddw
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; CHECK: movlpd
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; CHECK: movq
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; FIXME - if this test cares about scheduling, why isn't it being checked?
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; Scheduler causes produce a different instruction order
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; ATOM: movl
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; ATOM: paddw
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; ATOM: movlpd
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; ATOM: movq
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; bitcast a v4i16 to v2i32
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@ -52,7 +52,7 @@ forbody: ; preds = %forcond
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; CHECK-NEXT: psraw $8
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; CHECK-NEXT: psraw $2
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; CHECK-NEXT: pshufb
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; CHECK-NEXT: movlpd
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; CHECK-NEXT: movq
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;
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; FIXME: We shouldn't require both a movd and an insert.
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; CHECK-WIDE: %forbody
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@ -1,6 +1,6 @@
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; RUN: llc < %s -march=x86 -mattr=+sse4.2 | FileCheck %s
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; CHECK: movl
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; CHECK: movlpd
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; CHECK: movq
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; bitcast a i64 to v2i32
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define void @convert(<2 x i32>* %dst.addr, i64 %src) nounwind {
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@ -84,7 +84,7 @@ define void @shuf5(<8 x i8>* %p) nounwind {
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: movdqa {{.*#+}} xmm0 = [33,33,33,33,33,33,33,33]
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; CHECK-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u]
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; CHECK-NEXT: movlpd %xmm0, (%eax)
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; CHECK-NEXT: movq %xmm0, (%eax)
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; CHECK-NEXT: retl
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%v = shufflevector <2 x i8> <i8 4, i8 33>, <2 x i8> undef, <8 x i32> <i32 1, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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store <8 x i8> %v, <8 x i8>* %p, align 8
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