forked from OSchip/llvm-project
[ARM] Improve codegen of volatile load/store of i64
Summary: Instead of generating two i32 instructions for each load or store of a volatile i64 value (two LDRs or STRs), now emit LDRD/STRD. These improvements cover architectures implementing ARMv5TE or Thumb-2. The code generation explicitly deviates from using the register-offset variant of LDRD/STRD. In this variant, the register allocated to the register-offset cannot be reused in any of the remaining operands. Such restriction seems to be non-trivial to implement in LLVM, thus it is left as a to-do. Differential Revision: https://reviews.llvm.org/D70072
This commit is contained in:
Victor Campos
parent
23ac16cf9b
commit
c010d4d195
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@ -2735,6 +2735,24 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
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MI.eraseFromParent();
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return true;
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}
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case ARM::LOADDUAL:
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case ARM::STOREDUAL: {
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Register PairReg = MI.getOperand(0).getReg();
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MachineInstrBuilder MIB =
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BuildMI(MBB, MBBI, MI.getDebugLoc(),
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TII->get(Opcode == ARM::LOADDUAL ? ARM::LDRD : ARM::STRD))
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.addReg(TRI->getSubReg(PairReg, ARM::gsub_0),
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Opcode == ARM::LOADDUAL ? RegState::Define : 0)
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.addReg(TRI->getSubReg(PairReg, ARM::gsub_1),
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Opcode == ARM::LOADDUAL ? RegState::Define : 0);
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for (unsigned i = 1; i < MI.getNumOperands(); i++)
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MIB.add(MI.getOperand(i));
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MIB.add(predOps(ARMCC::AL));
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MIB.cloneMemRefs(MI);
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MI.eraseFromParent();
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return true;
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}
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}
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}
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@ -145,6 +145,8 @@ public:
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// Thumb 2 Addressing Modes:
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bool SelectT2AddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
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template <unsigned Shift>
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bool SelectT2AddrModeImm8(SDValue N, SDValue &Base, SDValue &OffImm);
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bool SelectT2AddrModeImm8(SDValue N, SDValue &Base,
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SDValue &OffImm);
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bool SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
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@ -1312,6 +1314,33 @@ bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDValue N,
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return true;
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}
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template <unsigned Shift>
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bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDValue N, SDValue &Base,
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SDValue &OffImm) {
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if (N.getOpcode() == ISD::SUB || CurDAG->isBaseWithConstantOffset(N)) {
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int RHSC;
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if (isScaledConstantInRange(N.getOperand(1), 1 << Shift, -255, 256, RHSC)) {
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Base = N.getOperand(0);
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if (Base.getOpcode() == ISD::FrameIndex) {
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int FI = cast<FrameIndexSDNode>(Base)->getIndex();
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Base = CurDAG->getTargetFrameIndex(
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FI, TLI->getPointerTy(CurDAG->getDataLayout()));
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}
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if (N.getOpcode() == ISD::SUB)
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RHSC = -RHSC;
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OffImm =
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CurDAG->getTargetConstant(RHSC * (1 << Shift), SDLoc(N), MVT::i32);
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return true;
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}
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}
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// Base only.
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Base = N;
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OffImm = CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32);
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return true;
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}
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bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDValue N,
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SDValue &Base, SDValue &OffImm) {
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// Match simple R - imm8 operands.
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@ -3655,6 +3684,59 @@ void ARMDAGToDAGISel::Select(SDNode *N) {
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CurDAG->RemoveDeadNode(N);
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return;
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}
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case ARMISD::LDRD: {
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if (Subtarget->isThumb2())
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break; // TableGen handles isel in this case.
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SDValue Base, RegOffset, ImmOffset;
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const SDValue &Chain = N->getOperand(0);
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const SDValue &Addr = N->getOperand(1);
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SelectAddrMode3(Addr, Base, RegOffset, ImmOffset);
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if (RegOffset != CurDAG->getRegister(0, MVT::i32)) {
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// The register-offset variant of LDRD mandates that the register
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// allocated to RegOffset is not reused in any of the remaining operands.
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// This restriction is currently not enforced. Therefore emitting this
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// variant is explicitly avoided.
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Base = Addr;
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RegOffset = CurDAG->getRegister(0, MVT::i32);
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}
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SDValue Ops[] = {Base, RegOffset, ImmOffset, Chain};
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SDNode *New = CurDAG->getMachineNode(ARM::LOADDUAL, dl,
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{MVT::Untyped, MVT::Other}, Ops);
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SDValue Lo = CurDAG->getTargetExtractSubreg(ARM::gsub_0, dl, MVT::i32,
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SDValue(New, 0));
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SDValue Hi = CurDAG->getTargetExtractSubreg(ARM::gsub_1, dl, MVT::i32,
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SDValue(New, 0));
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transferMemOperands(N, New);
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ReplaceUses(SDValue(N, 0), Lo);
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ReplaceUses(SDValue(N, 1), Hi);
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ReplaceUses(SDValue(N, 2), SDValue(New, 1));
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CurDAG->RemoveDeadNode(N);
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return;
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}
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case ARMISD::STRD: {
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if (Subtarget->isThumb2())
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break; // TableGen handles isel in this case.
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SDValue Base, RegOffset, ImmOffset;
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const SDValue &Chain = N->getOperand(0);
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const SDValue &Addr = N->getOperand(3);
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SelectAddrMode3(Addr, Base, RegOffset, ImmOffset);
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if (RegOffset != CurDAG->getRegister(0, MVT::i32)) {
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// The register-offset variant of STRD mandates that the register
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// allocated to RegOffset is not reused in any of the remaining operands.
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// This restriction is currently not enforced. Therefore emitting this
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// variant is explicitly avoided.
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Base = Addr;
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RegOffset = CurDAG->getRegister(0, MVT::i32);
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}
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SDNode *RegPair =
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createGPRPairNode(MVT::Untyped, N->getOperand(1), N->getOperand(2));
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SDValue Ops[] = {SDValue(RegPair, 0), Base, RegOffset, ImmOffset, Chain};
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SDNode *New = CurDAG->getMachineNode(ARM::STOREDUAL, dl, MVT::Other, Ops);
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transferMemOperands(N, New);
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ReplaceUses(SDValue(N, 0), SDValue(New, 0));
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CurDAG->RemoveDeadNode(N);
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return;
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}
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case ARMISD::LOOP_DEC: {
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SDValue Ops[] = { N->getOperand(1),
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N->getOperand(2),
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@ -1082,6 +1082,8 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::SRA, MVT::i64, Custom);
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setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
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setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
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setOperationAction(ISD::LOAD, MVT::i64, Custom);
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setOperationAction(ISD::STORE, MVT::i64, Custom);
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// MVE lowers 64 bit shifts to lsll and lsrl
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// assuming that ISD::SRL and SRA of i64 are already marked custom
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@ -1624,6 +1626,9 @@ const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
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case ARMISD::PRELOAD: return "ARMISD::PRELOAD";
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case ARMISD::LDRD: return "ARMISD::LDRD";
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case ARMISD::STRD: return "ARMISD::STRD";
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case ARMISD::WIN__CHKSTK: return "ARMISD::WIN__CHKSTK";
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case ARMISD::WIN__DBZCHK: return "ARMISD::WIN__DBZCHK";
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@ -9151,6 +9156,25 @@ static SDValue LowerPredicateLoad(SDValue Op, SelectionDAG &DAG) {
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return DAG.getMergeValues({Pred, Load.getValue(1)}, dl);
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}
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void ARMTargetLowering::LowerLOAD(SDNode *N, SmallVectorImpl<SDValue> &Results,
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SelectionDAG &DAG) const {
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LoadSDNode *LD = cast<LoadSDNode>(N);
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EVT MemVT = LD->getMemoryVT();
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assert(LD->isUnindexed() && "Loads should be unindexed at this point.");
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if (MemVT == MVT::i64 && Subtarget->hasV5TEOps() &&
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!Subtarget->isThumb1Only() && LD->isVolatile()) {
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SDLoc dl(N);
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SDValue Result = DAG.getMemIntrinsicNode(
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ARMISD::LDRD, dl, DAG.getVTList({MVT::i32, MVT::i32, MVT::Other}),
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{LD->getChain(), LD->getBasePtr()}, MemVT, LD->getMemOperand());
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SDValue Lo = Result.getValue(DAG.getDataLayout().isLittleEndian() ? 0 : 1);
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SDValue Hi = Result.getValue(DAG.getDataLayout().isLittleEndian() ? 1 : 0);
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SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
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Results.append({Pair, Result.getValue(2)});
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}
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}
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static SDValue LowerPredicateStore(SDValue Op, SelectionDAG &DAG) {
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StoreSDNode *ST = cast<StoreSDNode>(Op.getNode());
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EVT MemVT = ST->getMemoryVT();
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@ -9180,6 +9204,38 @@ static SDValue LowerPredicateStore(SDValue Op, SelectionDAG &DAG) {
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ST->getMemOperand());
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}
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static SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG,
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const ARMSubtarget *Subtarget) {
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StoreSDNode *ST = cast<StoreSDNode>(Op.getNode());
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EVT MemVT = ST->getMemoryVT();
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assert(ST->isUnindexed() && "Stores should be unindexed at this point.");
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if (MemVT == MVT::i64 && Subtarget->hasV5TEOps() &&
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!Subtarget->isThumb1Only() && ST->isVolatile()) {
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SDNode *N = Op.getNode();
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SDLoc dl(N);
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SDValue Lo = DAG.getNode(
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ISD::EXTRACT_ELEMENT, dl, MVT::i32, ST->getValue(),
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DAG.getTargetConstant(DAG.getDataLayout().isLittleEndian() ? 0 : 1, dl,
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MVT::i32));
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SDValue Hi = DAG.getNode(
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ISD::EXTRACT_ELEMENT, dl, MVT::i32, ST->getValue(),
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DAG.getTargetConstant(DAG.getDataLayout().isLittleEndian() ? 1 : 0, dl,
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MVT::i32));
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return DAG.getMemIntrinsicNode(ARMISD::STRD, dl, DAG.getVTList(MVT::Other),
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{ST->getChain(), Lo, Hi, ST->getBasePtr()},
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MemVT, ST->getMemOperand());
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} else if (Subtarget->hasMVEIntegerOps() &&
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((MemVT == MVT::v4i1 || MemVT == MVT::v8i1 ||
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MemVT == MVT::v16i1))) {
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return LowerPredicateStore(Op, DAG);
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}
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return SDValue();
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}
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static bool isZeroVector(SDValue N) {
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return (ISD::isBuildVectorAllZeros(N.getNode()) ||
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(N->getOpcode() == ARMISD::VMOVIMM &&
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@ -9414,7 +9470,7 @@ SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
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case ISD::LOAD:
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return LowerPredicateLoad(Op, DAG);
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case ISD::STORE:
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return LowerPredicateStore(Op, DAG);
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return LowerSTORE(Op, DAG, Subtarget);
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case ISD::MLOAD:
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return LowerMLOAD(Op, DAG);
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case ISD::ATOMIC_LOAD:
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@ -9518,7 +9574,9 @@ void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
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case ISD::ABS:
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lowerABS(N, Results, DAG);
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return ;
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case ISD::LOAD:
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LowerLOAD(N, Results, DAG);
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break;
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}
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if (Res.getNode())
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Results.push_back(Res);
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@ -305,7 +305,11 @@ class VectorType;
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VST4_UPD,
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VST2LN_UPD,
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VST3LN_UPD,
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VST4LN_UPD
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VST4LN_UPD,
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// Load/Store of dual registers
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LDRD,
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STRD
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};
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} // end namespace ARMISD
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@ -771,6 +775,8 @@ class VectorType;
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SDValue LowerFSETCC(SDValue Op, SelectionDAG &DAG) const;
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void lowerABS(SDNode *N, SmallVectorImpl<SDValue> &Results,
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SelectionDAG &DAG) const;
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void LowerLOAD(SDNode *N, SmallVectorImpl<SDValue> &Results,
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SelectionDAG &DAG) const;
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Register getRegisterByName(const char* RegName, LLT VT,
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const MachineFunction &MF) const override;
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@ -245,6 +245,12 @@ def ARMqsub8b : SDNode<"ARMISD::QSUB8b", SDT_ARMAnd, []>;
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def ARMqadd16b : SDNode<"ARMISD::QADD16b", SDT_ARMAnd, []>;
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def ARMqsub16b : SDNode<"ARMISD::QSUB16b", SDT_ARMAnd, []>;
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def SDT_ARMldrd : SDTypeProfile<2, 1, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>, SDTCisPtrTy<2>]>;
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def ARMldrd : SDNode<"ARMISD::LDRD", SDT_ARMldrd, [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
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def SDT_ARMstrd : SDTypeProfile<0, 3, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>, SDTCisPtrTy<2>]>;
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def ARMstrd : SDNode<"ARMISD::STRD", SDT_ARMstrd, [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
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// Vector operations shared between NEON and MVE
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def ARMvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>;
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@ -2736,6 +2742,14 @@ let mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1 in {
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Requires<[IsARM, HasV5TE]>;
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}
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let mayLoad = 1, hasSideEffects = 0, hasNoSchedulingInfo = 1 in {
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def LOADDUAL : ARMPseudoInst<(outs GPRPairOp:$Rt), (ins addrmode3:$addr),
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64, IIC_iLoad_d_r, []>,
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Requires<[IsARM, HasV5TE]> {
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let AM = AddrMode3;
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}
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}
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def LDA : AIldracq<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
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NoItinerary, "lda", "\t$Rt, $addr", []>;
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def LDAB : AIldracq<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
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@ -3014,6 +3028,14 @@ let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in {
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}
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}
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let mayStore = 1, hasSideEffects = 0, hasNoSchedulingInfo = 1 in {
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def STOREDUAL : ARMPseudoInst<(outs), (ins GPRPairOp:$Rt, addrmode3:$addr),
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64, IIC_iStore_d_r, []>,
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Requires<[IsARM, HasV5TE]> {
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let AM = AddrMode3;
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}
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}
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// Indexed stores
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multiclass AI2_stridx<bit isByte, string opc,
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InstrItinClass iii, InstrItinClass iir> {
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@ -270,7 +270,8 @@ def t2am_imm8_offset : MemOperand,
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// t2addrmode_imm8s4 := reg +/- (imm8 << 2)
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def MemImm8s4OffsetAsmOperand : AsmOperandClass {let Name = "MemImm8s4Offset";}
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class T2AddrMode_Imm8s4 : MemOperand {
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class T2AddrMode_Imm8s4 : MemOperand,
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ComplexPattern<i32, 2, "SelectT2AddrModeImm8<2>", []> {
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let EncoderMethod = "getT2AddrModeImm8s4OpValue";
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let DecoderMethod = "DecodeT2AddrModeImm8s4";
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let ParserMatchClass = MemImm8s4OffsetAsmOperand;
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@ -1448,7 +1449,8 @@ let mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1 in {
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// Load doubleword
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def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs rGPR:$Rt, rGPR:$Rt2),
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(ins t2addrmode_imm8s4:$addr),
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IIC_iLoad_d_i, "ldrd", "\t$Rt, $Rt2, $addr", "", []>,
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IIC_iLoad_d_i, "ldrd", "\t$Rt, $Rt2, $addr", "",
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[(set rGPR:$Rt, rGPR:$Rt2, (ARMldrd t2addrmode_imm8s4:$addr))]>,
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Sched<[WriteLd]>;
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} // mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1
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@ -1629,7 +1631,8 @@ defm t2STRH:T2I_st<0b01,"strh", IIC_iStore_bh_i, IIC_iStore_bh_si,
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let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in
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def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
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(ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4:$addr),
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IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", "", []>,
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IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", "",
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[(ARMstrd rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4:$addr)]>,
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Sched<[WriteST]>;
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// Indexed stores
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@ -0,0 +1,191 @@
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; RUN: llc -mtriple=armv5e-arm-none-eabi %s -o - | FileCheck %s --check-prefixes=CHECK-ARMV5TE,CHECK
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; RUN: llc -mtriple=thumbv6t2-arm-none-eabi %s -o - | FileCheck %s --check-prefixes=CHECK-T2,CHECK
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; RUN: llc -mtriple=armv4t-arm-none-eabi %s -o - | FileCheck %s --check-prefixes=CHECK-ARMV4T,CHECK
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@x = common dso_local global i64 0, align 8
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@y = common dso_local global i64 0, align 8
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define void @test() {
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entry:
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; CHECK-LABEL: test:
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; CHECK-ARMV5TE: ldr [[ADDR0:r[0-9]+]]
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; CHECK-ARMV5TE-NEXT: ldr [[ADDR1:r[0-9]+]]
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; CHECK-ARMV5TE-NEXT: ldrd [[R0:r[0-9]+]], [[R1:r[0-9]+]], {{\[}}[[ADDR0]]]
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; CHECK-ARMV5TE-NEXT: strd [[R0]], [[R1]], {{\[}}[[ADDR1]]]
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; CHECK-T2: movw [[ADDR0:r[0-9]+]], :lower16:x
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; CHECK-T2-NEXT: movw [[ADDR1:r[0-9]+]], :lower16:y
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; CHECK-T2-NEXT: movt [[ADDR0]], :upper16:x
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; CHECK-T2-NEXT: movt [[ADDR1]], :upper16:y
|
||||
; CHECK-T2-NEXT: ldrd [[R0:r[0-9]+]], [[R1:r[0-9]+]], {{\[}}[[ADDR0]]]
|
||||
; CHECK-T2-NEXT: strd [[R0]], [[R1]], {{\[}}[[ADDR1]]]
|
||||
; CHECK-ARMV4T: ldr [[ADDR0:r[0-9]+]]
|
||||
; CHECK-ARMV4T-NEXT: ldr [[ADDR1:r[0-9]+]]
|
||||
; CHECK-ARMV4T-NEXT: ldr [[R1:r[0-9]+]], {{\[}}[[ADDR0]]]
|
||||
; CHECK-ARMV4T-NEXT: ldr [[R0:r[0-9]+]], {{\[}}[[ADDR0]], #4]
|
||||
; CHECK-ARMV4T-NEXT: str [[R0]], {{\[}}[[ADDR1]], #4]
|
||||
; CHECK-ARMV4T-NEXT: str [[R1]], {{\[}}[[ADDR1]]]
|
||||
%0 = load volatile i64, i64* @x, align 8
|
||||
store volatile i64 %0, i64* @y, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @test_offset() {
|
||||
entry:
|
||||
; CHECK-LABEL: test_offset:
|
||||
; CHECK-ARMV5TE: ldr [[ADDR0:r[0-9]+]]
|
||||
; CHECK-ARMV5TE-NEXT: ldr [[ADDR1:r[0-9]+]]
|
||||
; CHECK-ARMV5TE-NEXT: ldrd [[R0:r[0-9]+]], [[R1:r[0-9]+]], {{\[}}[[ADDR0]], #-4]
|
||||
; CHECK-ARMV5TE-NEXT: strd [[R0]], [[R1]], {{\[}}[[ADDR1]], #-4]
|
||||
; CHECK-T2: movw [[ADDR0:r[0-9]+]], :lower16:x
|
||||
; CHECK-T2-NEXT: movw [[ADDR1:r[0-9]+]], :lower16:y
|
||||
; CHECK-T2-NEXT: movt [[ADDR0]], :upper16:x
|
||||
; CHECK-T2-NEXT: movt [[ADDR1]], :upper16:y
|
||||
; CHECK-T2-NEXT: ldrd [[R0:r[0-9]+]], [[R1:r[0-9]+]], {{\[}}[[ADDR0]], #-4]
|
||||
; CHECK-T2-NEXT: strd [[R0]], [[R1]], {{\[}}[[ADDR1]], #-4]
|
||||
; CHECK-ARMV4T: ldr [[ADDR0:r[0-9]+]]
|
||||
; CHECK-ARMV4T-NEXT: ldr [[ADDR1:r[0-9]+]]
|
||||
; CHECK-ARMV4T-NEXT: ldr [[R0:r[0-9]+]], {{\[}}[[ADDR0]], #-4]
|
||||
; CHECK-ARMV4T-NEXT: ldr [[R1:r[0-9]+]], {{\[}}[[ADDR0]]]
|
||||
; CHECK-ARMV4T-NEXT: str [[R1]], {{\[}}[[ADDR1]]]
|
||||
; CHECK-ARMV4T-NEXT: str [[R0]], {{\[}}[[ADDR1]], #-4]
|
||||
%0 = load volatile i64, i64* bitcast (i8* getelementptr (i8, i8* bitcast (i64* @x to i8*), i32 -4) to i64*), align 8
|
||||
store volatile i64 %0, i64* bitcast (i8* getelementptr (i8, i8* bitcast (i64* @y to i8*), i32 -4) to i64*), align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @test_offset_1() {
|
||||
; CHECK-LABEL: test_offset_1:
|
||||
; CHECK-ARMV5TE: ldr [[ADDR0:r[0-9]+]]
|
||||
; CHECK-ARMV5TE-NEXT: ldr [[ADDR1:r[0-9]+]]
|
||||
; CHECK-ARMV5TE-NEXT: ldrd [[R0:r[0-9]+]], [[R1:r[0-9]+]], {{\[}}[[ADDR0]], #255]
|
||||
; CHECK-ARMV5TE-NEXT: strd [[R0]], [[R1]], {{\[}}[[ADDR1]], #255]
|
||||
; CHECK-T2: adds [[ADDR0:r[0-9]+]], #255
|
||||
; CHECK-T2-NEXT: adds [[ADDR1:r[0-9]+]], #255
|
||||
; CHECK-T2-NEXT: ldrd [[R0:r[0-9]+]], [[R1:r[0-9]+]], {{\[}}[[ADDR0]]]
|
||||
; CHECK-T2-NEXT: strd [[R0]], [[R1]], {{\[}}[[ADDR1]]]
|
||||
; CHECK-ARMV4T: ldr [[ADDR0:r[0-9]+]]
|
||||
; CHECK-ARMV4T-NEXT: ldr [[ADDR1:r[0-9]+]]
|
||||
; CHECK-ARMV4T-NEXT: ldr [[R0:r[0-9]+]], {{\[}}[[ADDR0]], #255]
|
||||
; CHECK-ARMV4T-NEXT: ldr [[R1:r[0-9]+]], {{\[}}[[ADDR0]], #259]
|
||||
; CHECK-ARMV4T-NEXT: str [[R1]], {{\[}}[[ADDR1]], #259]
|
||||
; CHECK-ARMV4T-NEXT: str [[R0]], {{\[}}[[ADDR1]], #255]
|
||||
entry:
|
||||
%0 = load volatile i64, i64* bitcast (i8* getelementptr (i8, i8* bitcast (i64* @x to i8*), i32 255) to i64*), align 8
|
||||
store volatile i64 %0, i64* bitcast (i8* getelementptr (i8, i8* bitcast (i64* @y to i8*), i32 255) to i64*), align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @test_offset_2() {
|
||||
; CHECK-LABEL: test_offset_2:
|
||||
; CHECK-ARMV5TE: ldr [[ADDR0:r[0-9]+]]
|
||||
; CHECK-ARMV5TE-NEXT: ldr [[ADDR1:r[0-9]+]]
|
||||
; CHECK-ARMV5TE-NEXT: add [[ADDR0]], [[ADDR0]], #256
|
||||
; CHECK-ARMV5TE-NEXT: add [[ADDR1]], [[ADDR1]], #256
|
||||
; CHECK-ARMV5TE-NEXT: ldrd [[R0:r[0-9]+]], [[R1:r[0-9]+]], {{\[}}[[ADDR0]]]
|
||||
; CHECK-ARMV5TE-NEXT: strd [[R0]], [[R1]], {{\[}}[[ADDR1]]]
|
||||
; CHECK-T2: movw [[ADDR0:r[0-9]+]], :lower16:x
|
||||
; CHECK-T2-NEXT: movw [[ADDR1:r[0-9]+]], :lower16:y
|
||||
; CHECK-T2-NEXT: movt [[ADDR0]], :upper16:x
|
||||
; CHECK-T2-NEXT: movt [[ADDR1]], :upper16:y
|
||||
; CHECK-T2-NEXT: ldrd [[R0:r[0-9]+]], [[R1:r[0-9]+]], {{\[}}[[ADDR0]], #256]
|
||||
; CHECK-T2-NEXT: strd [[R0]], [[R1]], {{\[}}[[ADDR1]], #256]
|
||||
; CHECK-ARMV4T: ldr [[ADDR0:r[0-9]+]]
|
||||
; CHECK-ARMV4T-NEXT: ldr [[ADDR1:r[0-9]+]]
|
||||
; CHECK-ARMV4T-NEXT: ldr [[R0:r[0-9]+]], {{\[}}[[ADDR0]], #256]
|
||||
; CHECK-ARMV4T-NEXT: ldr [[R1:r[0-9]+]], {{\[}}[[ADDR0]], #260]
|
||||
; CHECK-ARMV4T-NEXT: str [[R1]], {{\[}}[[ADDR1]], #260]
|
||||
; CHECK-ARMV4T-NEXT: str [[R0]], {{\[}}[[ADDR1]], #256]
|
||||
entry:
|
||||
%0 = load volatile i64, i64* bitcast (i8* getelementptr (i8, i8* bitcast (i64* @x to i8*), i32 256) to i64*), align 8
|
||||
store volatile i64 %0, i64* bitcast (i8* getelementptr (i8, i8* bitcast (i64* @y to i8*), i32 256) to i64*), align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @test_offset_3() {
|
||||
; CHECK-LABEL: test_offset_3:
|
||||
; CHECK-ARMV5TE: ldr [[ADDR0:r[0-9]+]]
|
||||
; CHECK-ARMV5TE-NEXT: ldr [[ADDR1:r[0-9]+]]
|
||||
; CHECK-ARMV5TE-NEXT: add [[ADDR0]], [[ADDR0]], #1020
|
||||
; CHECK-ARMV5TE-NEXT: add [[ADDR1]], [[ADDR1]], #1020
|
||||
; CHECK-ARMV5TE-NEXT: ldrd [[R0:r[0-9]+]], [[R1:r[0-9]+]], {{\[}}[[ADDR0]]]
|
||||
; CHECK-ARMV5TE-NEXT: strd [[R0]], [[R1]], {{\[}}[[ADDR1]]]
|
||||
; CHECK-T2: movw [[ADDR0:r[0-9]+]], :lower16:x
|
||||
; CHECK-T2-NEXT: movw [[ADDR1:r[0-9]+]], :lower16:y
|
||||
; CHECK-T2-NEXT: movt [[ADDR0]], :upper16:x
|
||||
; CHECK-T2-NEXT: movt [[ADDR1]], :upper16:y
|
||||
; CHECK-T2-NEXT: ldrd [[R0:r[0-9]+]], [[R1:r[0-9]+]], {{\[}}[[ADDR0]], #1020]
|
||||
; CHECK-T2-NEXT: strd [[R0]], [[R1]], {{\[}}[[ADDR1]], #1020]
|
||||
; CHECK-ARMV4T: ldr [[ADDR0:r[0-9]+]]
|
||||
; CHECK-ARMV4T-NEXT: ldr [[ADDR1:r[0-9]+]]
|
||||
; CHECK-ARMV4T-NEXT: ldr [[R0:r[0-9]+]], {{\[}}[[ADDR0]], #1020]
|
||||
; CHECK-ARMV4T-NEXT: ldr [[R1:r[0-9]+]], {{\[}}[[ADDR0]], #1024]
|
||||
; CHECK-ARMV4T-NEXT: str [[R1]], {{\[}}[[ADDR1]], #1024]
|
||||
; CHECK-ARMV4T-NEXT: str [[R0]], {{\[}}[[ADDR1]], #1020]
|
||||
entry:
|
||||
%0 = load volatile i64, i64* bitcast (i8* getelementptr (i8, i8* bitcast (i64* @x to i8*), i32 1020) to i64*), align 8
|
||||
store volatile i64 %0, i64* bitcast (i8* getelementptr (i8, i8* bitcast (i64* @y to i8*), i32 1020) to i64*), align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @test_offset_4() {
|
||||
; CHECK-LABEL: test_offset_4:
|
||||
; CHECK-ARMV5TE: ldr [[ADDR0:r[0-9]+]]
|
||||
; CHECK-ARMV5TE: ldr [[ADDR1:r[0-9]+]]
|
||||
; CHECK-ARMV5TE-NEXT: add [[ADDR0]], [[ADDR0]], #1024
|
||||
; CHECK-ARMV5TE-NEXT: add [[ADDR1]], [[ADDR1]], #1024
|
||||
; CHECK-ARMV5TE-NEXT: ldrd [[R0:r[0-9]+]], [[R1:r[0-9]+]], {{\[}}[[ADDR0]]]
|
||||
; CHECK-ARMV5TE-NEXT: strd [[R0]], [[R1]], {{\[}}[[ADDR1]]]
|
||||
; CHECK-T2: movw [[ADDR1:r[0-9]+]], :lower16:y
|
||||
; CHECK-T2-NEXT: movw [[ADDR0:r[0-9]+]], :lower16:x
|
||||
; CHECK-T2-NEXT: movt [[ADDR1]], :upper16:y
|
||||
; CHECK-T2-NEXT: movt [[ADDR0]], :upper16:x
|
||||
; CHECK-T2-NEXT: add.w [[ADDR0]], [[ADDR0]], #1024
|
||||
; CHECK-T2-NEXT: add.w [[ADDR1]], [[ADDR1]], #1024
|
||||
; CHECK-T2-NEXT: ldrd [[R0:r[0-9]+]], [[R1:r[0-9]+]], {{\[}}[[ADDR0]]]
|
||||
; CHECK-T2-NEXT: strd [[R0]], [[R1]], {{\[}}[[ADDR1]]]
|
||||
; CHECK-ARMV4T: ldr [[ADDR0:r[0-9]+]]
|
||||
; CHECK-ARMV4T-NEXT: ldr [[ADDR1:r[0-9]+]]
|
||||
; CHECK-ARMV4T-NEXT: ldr [[R0:r[0-9]+]], {{\[}}[[ADDR0]], #1024]
|
||||
; CHECK-ARMV4T-NEXT: ldr [[R1:r[0-9]+]], {{\[}}[[ADDR0]], #1028]
|
||||
; CHECK-ARMV4T-NEXT: str [[R1]], {{\[}}[[ADDR1]], #1028]
|
||||
; CHECK-ARMV4T-NEXT: str [[R0]], {{\[}}[[ADDR1]], #1024]
|
||||
entry:
|
||||
%0 = load volatile i64, i64* bitcast (i8* getelementptr (i8, i8* bitcast (i64* @x to i8*), i32 1024) to i64*), align 8
|
||||
store volatile i64 %0, i64* bitcast (i8* getelementptr (i8, i8* bitcast (i64* @y to i8*), i32 1024) to i64*), align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
define i64 @test_stack() {
|
||||
; CHECK-LABEL: test_stack:
|
||||
; CHECK-ARMV5TE: sub sp, sp, #80
|
||||
; CHECK-ARMV5TE-NEXT: mov [[R0:r[0-9]+]], #0
|
||||
; CHECK-ARMV5TE-NEXT: mov [[R1:r[0-9]+]], #1
|
||||
; CHECK-ARMV5TE-NEXT: strd [[R1]], [[R0]], [sp, #8]
|
||||
; CHECK-ARMV5TE-NEXT: ldrd r0, r1, [sp, #8]
|
||||
; CHECK-ARMV5TE-NEXT: add sp, sp, #80
|
||||
; CHECK-ARMV5TE-NEXT: bx lr
|
||||
; CHECK-T2: sub sp, #80
|
||||
; CHECK-T2-NEXT: movs [[R0:r[0-9]+]], #0
|
||||
; CHECK-T2-NEXT: movs [[R1:r[0-9]+]], #1
|
||||
; CHECK-T2-NEXT: strd [[R1]], [[R0]], [sp, #8]
|
||||
; CHECK-T2-NEXT: ldrd r0, r1, [sp, #8]
|
||||
; CHECK-T2-NEXT: add sp, #80
|
||||
; CHECK-T2-NEXT: bx lr
|
||||
; CHECK-ARMV4T: sub sp, sp, #80
|
||||
; CHECK-ARMV4T-NEXT: mov [[R0:r[0-9]+]], #0
|
||||
; CHECK-ARMV4T-NEXT: str [[R0]], [sp, #12]
|
||||
; CHECK-ARMV4T-NEXT: mov [[R1:r[0-9]+]], #1
|
||||
; CHECK-ARMV4T-NEXT: str [[R1]], [sp, #8]
|
||||
; CHECK-ARMV4T-NEXT: ldr r0, [sp, #8]
|
||||
; CHECK-ARMV4T-NEXT: ldr r1, [sp, #12]
|
||||
; CHECK-ARMV4T-NEXT: add sp, sp, #80
|
||||
; CHECK-ARMV4T-NEXT: bx lr
|
||||
entry:
|
||||
%a = alloca [10 x i64], align 8
|
||||
%arrayidx = getelementptr inbounds [10 x i64], [10 x i64]* %a, i32 0, i32 1
|
||||
store volatile i64 1, i64* %arrayidx, align 8
|
||||
%arrayidx1 = getelementptr inbounds [10 x i64], [10 x i64]* %a, i32 0, i32 1
|
||||
%0 = load volatile i64, i64* %arrayidx1, align 8
|
||||
ret i64 %0
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue