forked from OSchip/llvm-project
Cleanup and factoring of mips16 tablegen classes. Make register classes
CPU16RegsRegClass and CPURARegRegClass available. Add definition of mips16 jalr instruction. Patch by Reed Kotler. llvm-svn: 157730
This commit is contained in:
Akira Hatanaka
parent
5bcaf5836b
commit
bff8e31d3c
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@ -61,19 +61,16 @@ def FrmEXT_I816 : Format16<20>;
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def FrmEXT_I8_SVRS16 : Format16<21>;
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def FrmOther16 : Format16<22>; // Instruction w/ a custom format
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// Generic Mips 16 Format
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class MipsInst16<dag outs, dag ins, string asmstr, list<dag> pattern,
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// Base class for Mips 16 Format
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// This class does not depend on the instruction size
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//
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class MipsInst16_Base<dag outs, dag ins, string asmstr, list<dag> pattern,
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InstrItinClass itin, Format16 f>: Instruction
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{
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field bits<16> Inst;
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Format16 Form = f;
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let Namespace = "Mips";
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bits<5> Opcode = 0;
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// Top 6 bits are the 'opcode' field
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let Inst{15-11} = Opcode;
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let OutOperandList = outs;
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let InOperandList = ins;
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@ -89,42 +86,42 @@ class MipsInst16<dag outs, dag ins, string asmstr, list<dag> pattern,
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// TSFlags layout should be kept in sync with MipsInstrInfo.h.
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let TSFlags{4-0} = FormBits;
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let Predicates = [InMips16Mode];
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}
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//
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// TBD. Maybe MipsInst16 and Mips16_EXTEND should be derived from a single
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// base class
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// Generic Mips 16 Format
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//
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class MipsInst16_EXTEND<dag outs, dag ins, string asmstr, list<dag> pattern,
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InstrItinClass itin, Format16 f>: Instruction
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class MipsInst16<dag outs, dag ins, string asmstr, list<dag> pattern,
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InstrItinClass itin, Format16 f>:
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MipsInst16_Base<outs, ins, asmstr, pattern, itin, f>
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{
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field bits<32> Inst;
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Format16 Form = f;
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let Namespace = "Mips";
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field bits<16> Inst;
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bits<5> Opcode = 0;
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bits<5> extend;
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// Top 6 bits are the 'opcode' field
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let Inst{31-27} = extend;
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let Inst{15-11} = Opcode;
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}
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let OutOperandList = outs;
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let InOperandList = ins;
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//
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// For 32 bit extended instruction forms.
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//
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class MipsInst16_32<dag outs, dag ins, string asmstr, list<dag> pattern,
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InstrItinClass itin, Format16 f>:
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MipsInst16_Base<outs, ins, asmstr, pattern, itin, f>
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{
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field bits<32> Inst;
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let AsmString = asmstr;
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let Pattern = pattern;
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let Itinerary = itin;
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}
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//
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// Attributes specific to Mips instructions...
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//
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bits<5> FormBits = Form.Value;
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class MipsInst16_EXTEND<dag outs, dag ins, string asmstr, list<dag> pattern,
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InstrItinClass itin, Format16 f>:
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MipsInst16_32<outs, ins, asmstr, pattern, itin, f>
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{
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let Inst{31-27} = 0b11110;
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// TSFlags layout should be kept in sync with MipsInstrInfo.h.
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let TSFlags{4-0} = FormBits;
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}
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@ -189,6 +186,28 @@ class FRR16<bits<5> _funct, dag outs, dag ins, string asmstr,
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let Inst{4-0} = funct;
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}
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//
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// J(AL)R(C) subformat
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//
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class FRR16_JALRC<dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin>:
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MipsInst16<outs, ins, asmstr, pattern, itin, FrmRR16>
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{
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bits<3> rx;
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bits<1> nd;
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bits<1> l;
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bits<1> ra;
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let Opcode = 0b11101;
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let Inst{10-8} = rx;
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let Inst{7} = nd;
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let Inst{6} = l;
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let Inst{5} = ra;
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let Inst{4-0} = 0;
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}
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//===----------------------------------------------------------------------===//
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// Format RRI instruction class in Mips : <|opcode|rx|ry|immed|>
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//===----------------------------------------------------------------------===//
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@ -376,15 +395,15 @@ class FI8_SVRS16<bits<5> op, bits<3> _SVRS, dag outs, dag ins, string asmstr,
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class FJAL16<bits<5> op, bits<1> _X, dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin>:
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MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin, FrmJAL16>
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MipsInst16_32<outs, ins, asmstr, pattern, itin, FrmJAL16>
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{
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bits<1> X;
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bits<26> immed26;
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let Opcode = op;
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let X = _X;
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let Inst{31-27} = 0b00011;
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let Inst{26} = X;
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let Inst{25-21} = immed26{20-16};
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let Inst{20-16} = immed26{25-21};
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@ -398,14 +417,13 @@ class FJAL16<bits<5> op, bits<1> _X, dag outs, dag ins, string asmstr,
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// <|opcode|immed10:5|immed15:1|op|0|0|0|0|0|0|immed4:0>
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//===----------------------------------------------------------------------===//
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class FEXT_I16<bits<5> op, bits<5> _eop, dag outs, dag ins, string asmstr,
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class FEXT_I16<bits<5> _eop, dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin>:
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MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin, FrmEXT_I16>
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{
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bits<16> immed16;
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bits<5> eop;
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let Opcode = op;
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let eop = _eop;
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let Inst{26-21} = immed16{10-5};
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@ -439,7 +457,6 @@ class FASMACRO16<bits<5> op, dag outs, dag ins, string asmstr,
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bits<3> p1;
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bits<5> p0;
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let Opcode = op;
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let Inst{26-24} = select;
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let Inst{23-21} = p4;
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@ -457,21 +474,20 @@ class FASMACRO16<bits<5> op, dag outs, dag ins, string asmstr,
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// <|opcode|immed10:5|immed15:11|op|rx|0|0|0|immed4:0>
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//===----------------------------------------------------------------------===//
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class FEXT_RI16<bits<5> op, bits<5> _eop, dag outs, dag ins, string asmstr,
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class FEXT_RI16<bits<5> _op, dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin>:
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MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin,
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FrmEXT_RI16>
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{
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bits<16> immed16;
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bits<5> eop;
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bits<5> op;
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bits<3> rx;
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let Opcode = op;
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let eop = _eop;
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let op = _op;
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let Inst{26-21} = immed16{10-5};
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let Inst{20-16} = immed16{15-11};
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let Inst{15-11} = eop;
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let Inst{15-11} = op;
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let Inst{10-8} = rx;
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let Inst{7-5} = 0;
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let Inst{4-0} = immed16{4-0};
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@ -483,22 +499,19 @@ class FEXT_RI16<bits<5> op, bits<5> _eop, dag outs, dag ins, string asmstr,
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// <|opcode|immed10:5|immed15:11|op|rx|ry|immed4:0>
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//===----------------------------------------------------------------------===//
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class FEXT_RRI16<bits<5> op, bits<5> _eop, dag outs, dag ins, string asmstr,
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class FEXT_RRI16<bits<5> _op, dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin>:
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MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin,
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FrmEXT_RRI16>
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{
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bits<16> immed16;
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bits<5> eop;
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bits<3> rx;
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bits<3> ry;
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let Opcode = op;
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let eop = _eop;
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let Inst{26-21} = immed16{10-5};
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let Inst{20-16} = immed16{15-11};
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let Inst{15-11} = eop;
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let Inst{15-11} = _op;
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let Inst{10-8} = rx;
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let Inst{7-5} = ry;
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let Inst{4-0} = immed16{4-0};
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@ -510,23 +523,21 @@ class FEXT_RRI16<bits<5> op, bits<5> _eop, dag outs, dag ins, string asmstr,
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// <|opcode|immed10:4|immed14:11|RRI-A|rx|ry|f|immed3:0>
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//===----------------------------------------------------------------------===//
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class FEXT_RRI_A16<bits<5> op, bits<1> _f, dag outs, dag ins, string asmstr,
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class FEXT_RRI_A16<bits<1> _f, dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin>:
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MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin,
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FrmEXT_RRI_A16>
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{
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bits<15> immed15;
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bits<5> RRI_A;
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bits<3> rx;
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bits<3> ry;
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bits<1> f;
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let Opcode = op;
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let f = _f;
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let Inst{26-20} = immed15{10-4};
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let Inst{19-16} = immed15{14-11};
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let Inst{15-11} = RRI_A;
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let Inst{15-11} = 0b01000;
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let Inst{10-8} = rx;
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let Inst{7-5} = ry;
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let Inst{4} = f;
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@ -545,18 +556,16 @@ class FEXT_SHIFT16<bits<5> op, bits<2> _f, dag outs, dag ins, string asmstr,
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FrmEXT_SHIFT16>
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{
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bits<6> sa6;
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bits<5> shift;
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bits<3> rx;
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bits<3> ry;
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bits<2> f;
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let Opcode = op;
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let f = _f;
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let Inst{26-22} = sa6{4-0};
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let Inst{21} = sa6{5};
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let Inst{20-16} = 0;
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let Inst{15-11} = shift;
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let Inst{15-11} = 0b00110;
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let Inst{10-8} = rx;
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let Inst{7-5} = ry;
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let Inst{4-2} = 0;
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@ -569,7 +578,7 @@ class FEXT_SHIFT16<bits<5> op, bits<2> _f, dag outs, dag ins, string asmstr,
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// <|opcode|immed10:5|immed15:11|I8|funct|0|immed4:0>
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//===----------------------------------------------------------------------===//
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class FEXT_I816<bits<5> op, bits<3> _funct, dag outs, dag ins, string asmstr,
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class FEXT_I816<bits<3> _funct, dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin>:
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MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin,
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FrmEXT_I816>
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@ -578,7 +587,6 @@ class FEXT_I816<bits<5> op, bits<3> _funct, dag outs, dag ins, string asmstr,
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bits<5> I8;
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bits<3> funct;
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let Opcode = op;
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let funct = _funct;
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let Inst{26-21} = immed16{10-5};
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@ -595,7 +603,7 @@ class FEXT_I816<bits<5> op, bits<3> _funct, dag outs, dag ins, string asmstr,
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// <|opcode|xsregs|framesize7:4|aregs|I8|SVRS|s|ra|s0|s1|framesize3:0>
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//===----------------------------------------------------------------------===//
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class FEXT_I8_SVRS16<bits<5> op, dag outs, dag ins, string asmstr,
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class FEXT_I8_SVRS16<dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin>:
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MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin,
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FrmI8_SVRS16>
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@ -610,7 +618,6 @@ class FEXT_I8_SVRS16<bits<5> op, dag outs, dag ins, string asmstr,
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bits<1> s0;
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bits<1> s1;
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let Opcode = op;
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let Inst{26-24} = xsregs;
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let Inst{23-20} = framesize{7-4};
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@ -12,7 +12,23 @@
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//===----------------------------------------------------------------------===//
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let isReturn=1, isTerminator=1, hasDelaySlot=1, isCodeGenOnly=1,
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isBarrier=1, hasCtrlDep=1, rx=0b000, ry=0b001 in
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def RET16 : FRR16 <0, (outs), (ins CPURAReg:$target),
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"jr\t$target", [(MipsRet CPURAReg:$target)], IIBranch>,
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Requires<[InMips16Mode]>;
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isBarrier=1, hasCtrlDep=1, rx=0, nd=0, l=0, ra=0 in
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def RET16 : FRR16_JALRC < (outs), (ins CPURAReg:$target),
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"jr\t$target", [(MipsRet CPURAReg:$target)], IIBranch>;
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// As stack alignment is always done with addiu, we need a 16-bit immediate
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let Defs = [SP], Uses = [SP] in {
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def ADJCALLSTACKDOWN16 : MipsPseudo16<(outs), (ins uimm16:$amt),
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"!ADJCALLSTACKDOWN $amt",
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[(callseq_start timm:$amt)]>;
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def ADJCALLSTACKUP16 : MipsPseudo16<(outs), (ins uimm16:$amt1, uimm16:$amt2),
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"!ADJCALLSTACKUP $amt1",
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[(callseq_end timm:$amt1, timm:$amt2)]>;
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}
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// Jump and Link (Call)
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let isCall=1, hasDelaySlot=1, nd=0, l=0, ra=0 in
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def JumpLinkReg16:
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FRR16_JALRC<(outs), (ins CPU16Regs:$rs, variable_ops),
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"jalr \t$rs", [(MipsJmpLink CPU16Regs:$rs)], IIBranch>;
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@ -103,6 +103,11 @@ MipsTargetLowering(MipsTargetMachine &TM)
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if (HasMips64)
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addRegisterClass(MVT::i64, &Mips::CPU64RegsRegClass);
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if (Subtarget->inMips16Mode()) {
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addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass);
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addRegisterClass(MVT::i32, &Mips::CPURARegRegClass);
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}
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if (!TM.Options.UseSoftFloat) {
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addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
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