forked from OSchip/llvm-project
Eliminate separate enum for operand register type.
Use union for alternative data for different operand types. Add iterator over Value* operands in a MachineInstr. llvm-svn: 307
This commit is contained in:
Vikram S. Adve
parent
3a7aa63841
commit
bff682dfac
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@ -15,11 +15,15 @@
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#ifndef LLVM_CODEGEN_MACHINEINSTR_H
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#define LLVM_CODEGEN_MACHINEINSTR_H
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#include <iterator>
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#include "llvm/CodeGen/InstrForest.h"
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#include "llvm/Support/DataTypes.h"
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#include "llvm/Support/NonCopyable.h"
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#include "llvm/CodeGen/TargetMachine.h"
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template<class _MI, class _V> class ValOpIterator;
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//---------------------------------------------------------------------------
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// class MachineOperand
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//
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@ -56,56 +60,78 @@
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//---------------------------------------------------------------------------
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class MachineOperand {
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public:
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friend ostream& operator<<(ostream& os, const MachineOperand& mop);
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public:
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enum MachineOperandType {
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MO_Register,
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MO_VirtualRegister, // virtual register for *value
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MO_MachineRegister, // pre-assigned machine register `regNum'
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MO_CCRegister,
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MO_SignExtendedImmed,
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MO_UnextendedImmed,
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MO_PCRelativeDisp,
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};
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enum VirtualRegisterType {
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MO_VirtualReg, // virtual register for *value
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MO_MachineReg // pre-assigned machine register `regNum'
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};
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MachineOperandType machineOperandType;
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VirtualRegisterType vregType;
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private:
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MachineOperandType opType;
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union {
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Value* value; // BasicBlockVal for a label operand.
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// ConstantVal for a non-address immediate.
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// Virtual register for a register operand.
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// Virtual register for an SSA operand,
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// including hidden operands required for
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// the generated machine code.
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unsigned int regNum; // register number for an explicit register
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int64_t immedVal; // constant value for an explicit constant
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};
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public:
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/*ctor*/ MachineOperand ();
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/*ctor*/ MachineOperand (MachineOperandType operandType,
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Value* _val);
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/*copy ctor*/ MachineOperand (const MachineOperand&);
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/*dtor*/ ~MachineOperand () {}
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// Accessor methods. Caller is responsible for checking the
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// operand type before invoking the corresponding accessor.
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//
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MachineOperandType getOperandType () const {
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return opType;
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}
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Value* getVRegValue () const {
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assert(opType == MO_VirtualRegister || opType == MO_CCRegister);
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return value;
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}
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unsigned int getMachineRegNum() const {
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assert(opType == MO_MachineRegister);
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return regNum;
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}
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int64_t getImmedValue () const {
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assert(opType >= MO_SignExtendedImmed || opType <= MO_PCRelativeDisp);
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return immedVal;
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}
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public:
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friend ostream& operator<<(ostream& os, const MachineOperand& mop);
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private:
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// These functions are provided so that a vector of operands can be
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// statically allocated and individual ones can be initialized later.
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// Give class MachineInstr gets access to these functions.
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//
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void Initialize (MachineOperandType operandType,
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Value* _val);
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void InitializeConst (MachineOperandType operandType,
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int64_t intValue);
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void InitializeReg (unsigned int regNum);
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friend class MachineInstr;
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};
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inline
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MachineOperand::MachineOperand()
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: machineOperandType(MO_Register),
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vregType(MO_VirtualReg),
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: opType(MO_VirtualRegister),
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value(NULL),
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regNum(0),
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immedVal(0)
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@ -114,8 +140,7 @@ MachineOperand::MachineOperand()
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inline
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MachineOperand::MachineOperand(MachineOperandType operandType,
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Value* _val)
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: machineOperandType(operandType),
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vregType(MO_VirtualReg),
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: opType(operandType),
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value(_val),
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regNum(0),
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immedVal(0)
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@ -123,19 +148,24 @@ MachineOperand::MachineOperand(MachineOperandType operandType,
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inline
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MachineOperand::MachineOperand(const MachineOperand& mo)
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: machineOperandType(mo.machineOperandType),
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vregType(mo.vregType),
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value(mo.value),
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regNum(mo.regNum),
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immedVal(mo.immedVal)
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: opType(mo.opType)
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{
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switch(opType) {
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case MO_VirtualRegister:
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case MO_CCRegister: value = mo.value; break;
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case MO_MachineRegister: regNum = mo.regNum; break;
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case MO_SignExtendedImmed:
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case MO_UnextendedImmed:
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case MO_PCRelativeDisp: immedVal = mo.immedVal; break;
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default: assert(0);
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}
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}
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inline void
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MachineOperand::Initialize(MachineOperandType operandType,
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Value* _val)
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{
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machineOperandType = operandType;
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opType = operandType;
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value = _val;
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}
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@ -143,7 +173,7 @@ inline void
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MachineOperand::InitializeConst(MachineOperandType operandType,
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int64_t intValue)
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{
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machineOperandType = operandType;
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opType = operandType;
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value = NULL;
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immedVal = intValue;
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}
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@ -151,8 +181,7 @@ MachineOperand::InitializeConst(MachineOperandType operandType,
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inline void
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MachineOperand::InitializeReg(unsigned int _regNum)
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{
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machineOperandType = MO_Register;
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vregType = MO_MachineReg;
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opType = MO_MachineRegister;
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value = NULL;
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regNum = _regNum;
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}
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@ -166,8 +195,6 @@ MachineOperand::InitializeReg(unsigned int _regNum)
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//
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// MachineOpCode must be an enum, defined separately for each target.
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// E.g., It is defined in SparcInstructionSelection.h for the SPARC.
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// The array MachineInstrInfo TargetMachineInstrInfo[] objects
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// (indexed by opCode) provides information about each target instruction.
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//
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// opCodeMask is used to record variants of an instruction.
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// E.g., each branch instruction on SPARC has 2 flags (i.e., 4 variants):
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@ -181,12 +208,15 @@ class MachineInstr : public NonCopyable {
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private:
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MachineOpCode opCode;
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OpCodeMask opCodeMask; // extra bits for variants of an opcode
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vector<MachineOperand> operands; // operand 0 is the result
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vector<MachineOperand> operands;
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public:
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typedef ValOpIterator<const MachineInstr, const Value> val_op_const_iterator;
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typedef ValOpIterator< MachineInstr, Value> val_op_iterator;
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public:
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/*ctor*/ MachineInstr (MachineOpCode _opCode,
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OpCodeMask _opCodeMask = 0x0);
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inline ~MachineInstr () {}
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const MachineOpCode getOpCode () const;
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@ -194,11 +224,14 @@ public:
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unsigned int getNumOperands () const;
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const MachineOperand& getOperand (unsigned int i) const;
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MachineOperand& getOperand (unsigned int i);
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void dump (unsigned int indent = 0);
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public:
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friend ostream& operator<<(ostream& os, const MachineInstr& minstr);
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friend val_op_const_iterator;
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friend val_op_iterator;
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public:
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// Access to set the operands when building the machine instruction
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@ -221,10 +254,15 @@ MachineInstr::getOpCode() const
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inline unsigned int
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MachineInstr::getNumOperands() const
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{
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assert(operands.size() == TargetMachineInstrInfo[opCode].numOperands);
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return operands.size();
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}
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inline MachineOperand&
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MachineInstr::getOperand(unsigned int i)
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{
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return operands[i];
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}
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inline const MachineOperand&
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MachineInstr::getOperand(unsigned int i) const
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{
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@ -232,6 +270,38 @@ MachineInstr::getOperand(unsigned int i) const
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}
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template<class _MI, class _V>
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class ValOpIterator : public std::forward_iterator<_V, ptrdiff_t> {
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private:
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unsigned int i;
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int resultPos;
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_MI*& minstr;
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inline void skipToNextVal() {
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while (i < minstr->getNumOperands()
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&& minstr->getOperand(i).getOperandType() != MachineOperand::MO_VirtualRegister
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&& minstr->getOperand(i).getOperandType() != MachineOperand::MO_CCRegister)
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++i;
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}
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public:
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typedef ValOpIterator<_MI, _V> _Self;
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inline ValOpIterator(_MI* _minstr) : i(0), minstr(_minstr) {
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resultPos = TargetInstrDescriptors[minstr->opCode].resultPos;
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skipToNextVal();
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};
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inline _V* operator*() const { return minstr->getOperand(i).getVRegValue();}
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inline _V* operator->() const { return operator*(); }
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inline bool isDef () const { return (((int) i) == resultPos); }
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inline bool done () const { return (i == minstr->getNumOperands()); }
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inline _Self& operator++() { i++; skipToNextVal(); return *this; }
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inline _Self operator++(int) { _Self tmp = *this; ++*this; return tmp; }
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};
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//---------------------------------------------------------------------------
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// class MachineInstructionsForVMInstr
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//
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@ -335,7 +405,6 @@ MachineOperand::MachineOperandType
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MachineOpCode opCode,
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const TargetMachine& targetMachine,
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bool canUseImmed,
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MachineOperand::VirtualRegisterType& getVRegType,
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unsigned int& getMachineRegNum,
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int64_t& getImmedValue);
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@ -20,28 +20,11 @@
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//************************ Class Implementations **************************/
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bool
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MachineInstrInfo::constantFitsInImmedField(int64_t intValue) const
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{
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// First, check if opCode has an immed field.
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bool isSignExtended;
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uint64_t maxImmedValue = this->maxImmedConstant(isSignExtended);
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if (maxImmedValue != 0)
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{
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// Now check if the constant fits
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if (intValue <= (int64_t) maxImmedValue &&
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intValue >= -((int64_t) maxImmedValue+1))
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return true;
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}
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return false;
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}
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MachineInstr::MachineInstr(MachineOpCode _opCode,
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OpCodeMask _opCodeMask)
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: opCode(_opCode),
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opCodeMask(_opCodeMask),
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operands(TargetMachineInstrInfo[_opCode].numOperands)
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operands(TargetInstrDescriptors[_opCode].numOperands)
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{
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}
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@ -50,7 +33,7 @@ MachineInstr::SetMachineOperand(unsigned int i,
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MachineOperand::MachineOperandType operandType,
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Value* _val)
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{
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assert(i < TargetMachineInstrInfo[opCode].numOperands);
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assert(i < operands.size());
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operands[i].Initialize(operandType, _val);
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}
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@ -59,7 +42,7 @@ MachineInstr::SetMachineOperand(unsigned int i,
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MachineOperand::MachineOperandType operandType,
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int64_t intValue)
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{
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assert(i < TargetMachineInstrInfo[opCode].numOperands);
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assert(i < operands.size());
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operands[i].InitializeConst(operandType, intValue);
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}
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@ -67,7 +50,7 @@ void
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MachineInstr::SetMachineOperand(unsigned int i,
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unsigned int regNum)
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{
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assert(i < TargetMachineInstrInfo[opCode].numOperands);
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assert(i < operands.size());
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operands[i].InitializeReg(regNum);
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}
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@ -83,11 +66,22 @@ MachineInstr::dump(unsigned int indent)
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ostream&
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operator<< (ostream& os, const MachineInstr& minstr)
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{
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os << TargetMachineInstrInfo[minstr.opCode].opCodeString;
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os << TargetInstrDescriptors[minstr.opCode].opCodeString;
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for (unsigned i=0, N=minstr.getNumOperands(); i < N; i++)
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os << "\t" << minstr.getOperand(i);
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#undef DEBUG_VAL_OP_ITERATOR
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#ifdef DEBUG_VAL_OP_ITERATOR
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os << endl << "\tValue operands are: ";
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for (MachineInstr::val_op_const_iterator vo(&minstr); ! vo.done(); ++vo)
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{
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const Value* val = *vo;
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os << val << (vo.isDef()? "(def), " : ", ");
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}
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os << endl;
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#endif
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return os;
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}
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@ -95,19 +89,17 @@ ostream&
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operator<< (ostream& os, const MachineOperand& mop)
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{
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strstream regInfo;
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if (mop.machineOperandType == MachineOperand::MO_Register)
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{
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if (mop.vregType == MachineOperand::MO_VirtualReg)
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if (mop.opType == MachineOperand::MO_VirtualRegister)
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regInfo << "(val " << mop.value << ")" << ends;
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else
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else if (mop.opType == MachineOperand::MO_MachineRegister)
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regInfo << "(" << mop.regNum << ")" << ends;
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}
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else if (mop.machineOperandType == MachineOperand::MO_CCRegister)
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else if (mop.opType == MachineOperand::MO_CCRegister)
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regInfo << "(val " << mop.value << ")" << ends;
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switch(mop.machineOperandType)
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switch(mop.opType)
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{
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case MachineOperand::MO_Register:
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case MachineOperand::MO_VirtualRegister:
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case MachineOperand::MO_MachineRegister:
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os << "%reg" << regInfo.str();
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free(regInfo.str());
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break;
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@ -169,21 +161,22 @@ operator<< (ostream& os, const MachineOperand& mop)
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void
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Set2OperandsFromInstr(MachineInstr* minstr,
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InstructionNode* vmInstrNode,
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const TargetMachine& targetMachine,
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const TargetMachine& target,
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bool canDiscardResult,
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int op1Position,
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int resultPosition)
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{
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Set3OperandsFromInstr(minstr, vmInstrNode, targetMachine,
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Set3OperandsFromInstr(minstr, vmInstrNode, target,
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canDiscardResult, op1Position,
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/*op2Position*/ -1, resultPosition);
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}
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#undef REVERT_TO_EXPLICIT_CONSTANT_CHECKS
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#ifdef REVERT_TO_EXPLICIT_CONSTANT_CHECKS
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unsigned
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Set3OperandsFromInstrJUNK(MachineInstr* minstr,
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InstructionNode* vmInstrNode,
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const TargetMachine& targetMachine,
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const TargetMachine& target,
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bool canDiscardResult,
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int op1Position,
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int op2Position,
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@ -198,15 +191,15 @@ Set3OperandsFromInstrJUNK(MachineInstr* minstr,
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Value* op1Value = vmInstrNode->leftChild()->getValue();
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bool isValidConstant;
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int64_t intValue = GetConstantValueAsSignedInt(op1Value, isValidConstant);
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if (isValidConstant && intValue == 0 && targetMachine.zeroRegNum >= 0)
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minstr->SetMachineOperand(op1Position, /*regNum*/ targetMachine.zeroRegNum);
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if (isValidConstant && intValue == 0 && target.zeroRegNum >= 0)
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minstr->SetMachineOperand(op1Position, /*regNum*/ target.zeroRegNum);
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else
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{
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if (op1Value->getValueType() == Value::ConstantVal)
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{// value is constant and must be loaded from constant pool
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returnFlags = returnFlags | (1 << op1Position);
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}
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minstr->SetMachineOperand(op1Position, MachineOperand::MO_Register,
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minstr->SetMachineOperand(op1Position,MachineOperand::MO_VirtualRegister,
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op1Value);
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}
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@ -216,19 +209,16 @@ Set3OperandsFromInstrJUNK(MachineInstr* minstr,
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{
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Value* op2Value = vmInstrNode->rightChild()->getValue();
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int64_t immedValue;
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MachineOperand::VirtualRegisterType vregType;
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unsigned int machineRegNum;
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MachineOperand::MachineOperandType
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op2type = ChooseRegOrImmed(op2Value, minstr->getOpCode(),targetMachine,
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op2type = ChooseRegOrImmed(op2Value, minstr->getOpCode(), target,
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/*canUseImmed*/ true,
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vregType, machineRegNum, immedValue);
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machineRegNum, immedValue);
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if (op2type == MachineOperand::MO_Register)
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{
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if (vregType == MachineOperand::MO_MachineReg)
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if (op2type == MachineOperand::MO_MachineRegister)
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minstr->SetMachineOperand(op2Position, machineRegNum);
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else
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else if (op2type == MachineOperand::MO_VirtualRegister)
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{
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if (op2Value->getValueType() == Value::ConstantVal)
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{// value is constant and must be loaded from constant pool
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@ -236,26 +226,28 @@ Set3OperandsFromInstrJUNK(MachineInstr* minstr,
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}
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minstr->SetMachineOperand(op2Position, op2type, op2Value);
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}
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}
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else
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{
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assert(op2type != MO_CCRegister);
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minstr->SetMachineOperand(op2Position, op2type, immedValue);
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}
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}
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// If operand 3 (result) can be discarded, use a dead register if one exists
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if (canDiscardResult && targetMachine.zeroRegNum >= 0)
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minstr->SetMachineOperand(resultPosition, targetMachine.zeroRegNum);
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if (canDiscardResult && target.zeroRegNum >= 0)
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||||
minstr->SetMachineOperand(resultPosition, target.zeroRegNum);
|
||||
else
|
||||
minstr->SetMachineOperand(resultPosition, MachineOperand::MO_Register,
|
||||
vmInstrNode->getValue());
|
||||
minstr->SetMachineOperand(resultPosition, MachineOperand::MO_VirtualRegister, vmInstrNode->getValue());
|
||||
|
||||
return returnFlags;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
void
|
||||
Set3OperandsFromInstr(MachineInstr* minstr,
|
||||
InstructionNode* vmInstrNode,
|
||||
const TargetMachine& targetMachine,
|
||||
const TargetMachine& target,
|
||||
bool canDiscardResult,
|
||||
int op1Position,
|
||||
int op2Position,
|
||||
|
|
@ -265,34 +257,32 @@ Set3OperandsFromInstr(MachineInstr* minstr,
|
|||
assert(resultPosition >= 0);
|
||||
|
||||
// operand 1
|
||||
minstr->SetMachineOperand(op1Position, MachineOperand::MO_Register,
|
||||
minstr->SetMachineOperand(op1Position, MachineOperand::MO_VirtualRegister,
|
||||
vmInstrNode->leftChild()->getValue());
|
||||
|
||||
// operand 2 (if any)
|
||||
if (op2Position >= 0)
|
||||
minstr->SetMachineOperand(op2Position, MachineOperand::MO_Register,
|
||||
minstr->SetMachineOperand(op2Position, MachineOperand::MO_VirtualRegister,
|
||||
vmInstrNode->rightChild()->getValue());
|
||||
|
||||
// result operand: if it can be discarded, use a dead register if one exists
|
||||
if (canDiscardResult && targetMachine.zeroRegNum >= 0)
|
||||
minstr->SetMachineOperand(resultPosition, targetMachine.zeroRegNum);
|
||||
if (canDiscardResult && target.zeroRegNum >= 0)
|
||||
minstr->SetMachineOperand(resultPosition, target.zeroRegNum);
|
||||
else
|
||||
minstr->SetMachineOperand(resultPosition, MachineOperand::MO_Register,
|
||||
vmInstrNode->getValue());
|
||||
minstr->SetMachineOperand(resultPosition, MachineOperand::MO_VirtualRegister, vmInstrNode->getValue());
|
||||
}
|
||||
|
||||
|
||||
MachineOperand::MachineOperandType
|
||||
ChooseRegOrImmed(Value* val,
|
||||
MachineOpCode opCode,
|
||||
const TargetMachine& targetMachine,
|
||||
const TargetMachine& target,
|
||||
bool canUseImmed,
|
||||
MachineOperand::VirtualRegisterType& getVRegType,
|
||||
unsigned int& getMachineRegNum,
|
||||
int64_t& getImmedValue)
|
||||
{
|
||||
MachineOperand::MachineOperandType opType = MachineOperand::MO_Register;
|
||||
getVRegType = MachineOperand::MO_VirtualReg;
|
||||
MachineOperand::MachineOperandType opType =
|
||||
MachineOperand::MO_VirtualRegister;
|
||||
getMachineRegNum = 0;
|
||||
getImmedValue = 0;
|
||||
|
||||
|
|
@ -311,13 +301,13 @@ ChooseRegOrImmed(Value* val,
|
|||
|
||||
if (isValidConstant)
|
||||
{
|
||||
if (intValue == 0 && targetMachine.zeroRegNum >= 0)
|
||||
if (intValue == 0 && target.zeroRegNum >= 0)
|
||||
{
|
||||
getVRegType = MachineOperand::MO_MachineReg;
|
||||
getMachineRegNum = targetMachine.zeroRegNum;
|
||||
opType = MachineOperand::MO_MachineRegister;
|
||||
getMachineRegNum = target.zeroRegNum;
|
||||
}
|
||||
else if (canUseImmed &&
|
||||
targetMachine.machineInstrInfo[opCode].constantFitsInImmedField(intValue))
|
||||
target.getInstrInfo().constantFitsInImmedField(opCode,intValue))
|
||||
{
|
||||
opType = MachineOperand::MO_SignExtendedImmed;
|
||||
getImmedValue = intValue;
|
||||
|
|
|
|||
Loading…
Reference in New Issue