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[PowerPC] Add floating point overloads for vec_sldw 

These are added for compatibility with XLC.
This commit is contained in:
Nemanja Ivanovic 2021-04-30 20:29:03 -05:00
parent bed58a4a58
commit bfd60b36f8
3 changed files with 34 additions and 0 deletions
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10
clang/lib/Headers/altivec.h
View File

@ -9091,6 +9091,11 @@ static __inline__ vector unsigned int __ATTRS_o_ai vec_sldw(
return vec_sld(__a, __b, ((__c << 2) & 0x0F));
}
static __inline__ vector float __ATTRS_o_ai vec_sldw(
vector float __a, vector float __b, unsigned const int __c) {
return vec_sld(__a, __b, ((__c << 2) & 0x0F));
}
#ifdef __VSX__
static __inline__ vector signed long long __ATTRS_o_ai
vec_sldw(vector signed long long __a, vector signed long long __b,
@ -9103,6 +9108,11 @@ vec_sldw(vector unsigned long long __a, vector unsigned long long __b,
unsigned const int __c) {
return vec_sld(__a, __b, ((__c << 2) & 0x0F));
}
static __inline__ vector double __ATTRS_o_ai vec_sldw(
vector double __a, vector double __b, unsigned const int __c) {
return vec_sld(__a, __b, ((__c << 2) & 0x0F));
}
#endif
#ifdef __POWER9_VECTOR__

12
clang/test/CodeGen/builtins-ppc-altivec.c
View File

@ -3759,6 +3759,18 @@ void test6() {
// CHECK-LE: sub nsw i32 31
// CHECK-LE: @llvm.ppc.altivec.vperm
res_vf = vec_sldw(vf, vf, 0);
// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 1
// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 2
// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 3
// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 15
// CHECK: @llvm.ppc.altivec.vperm
// CHECK-LE: sub nsw i32 16
// CHECK-LE: sub nsw i32 17
// CHECK-LE: sub nsw i32 18
// CHECK-LE: sub nsw i32 31
// CHECK-LE: @llvm.ppc.altivec.vperm
res_vsc = vec_vsldoi(vsc, vsc, 0);
// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 1
// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 2

12
clang/test/CodeGen/builtins-ppc-vsx.c
View File

@ -1888,6 +1888,18 @@ void test1() {
// CHECK-LE: sub nsw i32 17
// CHECK-LE: sub nsw i32 18
// CHECK-LE: sub nsw i32 31
// CHECK-LE: @llvm.ppc.altivec.vperm
res_vd = vec_sldw(vd, vd, 0);
// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 1
// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 2
// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 3
// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 15
// CHECK: @llvm.ppc.altivec.vperm
// CHECK-LE: sub nsw i32 16
// CHECK-LE: sub nsw i32 17
// CHECK-LE: sub nsw i32 18
// CHECK-LE: sub nsw i32 31
// CHECK-LE: @llvm.ppc.altivec.vperm
res_vsll = vec_sll(vsll, vuc);