From bf96e02a54cf3d4877cacdc7e4dad25b7fb04f5d Mon Sep 17 00:00:00 2001
From: Reid Spencer <rspencer@reidspencer.com>
Date: Mon, 8 Jan 2007 16:17:51 +0000
Subject: [PATCH] For PR1097: Enable complex addressing modes on 64-bit
 platforms involving two induction variables by keeping a size and scale in
 64-bits not 32. Patch by Dan Gohman.

llvm-svn: 33011
---
 llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp b/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
index 53fa9e200c03..798fb81190f4 100644
--- a/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
+++ b/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
@@ -893,7 +893,7 @@ unsigned LoopStrengthReduce::CheckForIVReuse(const SCEVHandle &Stride,
       if (unsigned(abs(SInt)) < Scale || (SInt % Scale) != 0)
         continue;
       std::map<SCEVHandle, IVsOfOneStride>::iterator SI =
-        IVsByStride.find(SCEVUnknown::getIntegerSCEV(SInt/Scale, Type::Int32Ty));
+        IVsByStride.find(SCEVUnknown::getIntegerSCEV(SInt/Scale, UIntPtrTy));
       if (SI == IVsByStride.end())
         continue;
       for (std::vector<IVExpr>::iterator II = SI->second.IVs.begin(),