maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

Schedule high latency instructions for latency reduction even if they are not vfp / NEON instructions. 

llvm-svn: 105060
This commit is contained in:
Evan Cheng 2010-05-28 23:25:23 +00:00
parent e8be73f3e7
commit bf91499f1a
1 changed files with 19 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
llvm/lib/Target/ARM/ARMISelLowering.cpp
View File

@ -605,11 +605,29 @@ unsigned ARMTargetLowering::getFunctionAlignment(const Function *F) const {
}
Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
unsigned NumVals = N->getNumValues();
if (!NumVals)
return Sched::RegPressure;
for (unsigned i = 0; i != NumVals; ++i) {
EVT VT = N->getValueType(i);
if (VT.isFloatingPoint() || VT.isVector())
return Sched::Latency;
}
if (!N->isMachineOpcode())
return Sched::RegPressure;
// Load are scheduled for latency even if there instruction itinerary
// is not available.
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
const TargetInstrDesc &TID = TII->get(N->getMachineOpcode());
if (TID.mayLoad())
return Sched::Latency;
const InstrItineraryData &Itins = getTargetMachine().getInstrItineraryData();
if (!Itins.isEmpty() && Itins.getStageLatency(TID.getSchedClass()) > 2)
return Sched::Latency;
return Sched::RegPressure;
}