forked from OSchip/llvm-project
Update these argument lists for the isNormalMemory
argument. This doesn't affect current functionality. llvm-svn: 61779
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79c3516912
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@ -729,7 +729,8 @@ void ScheduleDAGRRList::ListScheduleBottomUp() {
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DOUT << "Adding an edge from SU # " << TrySU->NodeNum
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<< " to SU #" << Copies.front()->NodeNum << "\n";
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AddPred(TrySU, SDep(Copies.front(), SDep::Order, /*Latency=*/1,
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/*Reg=*/0, /*isMustAlias=*/false,
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/*Reg=*/0, /*isNormalMemory=*/false,
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/*isMustAlias=*/false,
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/*isArtificial=*/true));
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NewDef = Copies.back();
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}
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@ -738,7 +739,8 @@ void ScheduleDAGRRList::ListScheduleBottomUp() {
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<< " to SU #" << TrySU->NodeNum << "\n";
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LiveRegDefs[Reg] = NewDef;
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AddPred(NewDef, SDep(TrySU, SDep::Order, /*Latency=*/1,
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/*Reg=*/0, /*isMustAlias=*/false,
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/*Reg=*/0, /*isNormalMemory=*/false,
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/*isMustAlias=*/false,
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/*isArtificial=*/true));
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TrySU->isAvailable = false;
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CurSU = NewDef;
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@ -1253,7 +1255,8 @@ void RegReductionPriorityQueue<SF>::AddPseudoTwoAddrDeps() {
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DOUT << "Adding a pseudo-two-addr edge from SU # " << SU->NodeNum
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<< " to SU #" << SuccSU->NodeNum << "\n";
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scheduleDAG->AddPred(SU, SDep(SuccSU, SDep::Order, /*Latency=*/0,
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/*Reg=*/0, /*isMustAlias=*/false,
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/*Reg=*/0, /*isNormalMemory=*/false,
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/*isMustAlias=*/false,
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/*isArtificial=*/true));
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}
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}
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