forked from OSchip/llvm-project
* Multiplications by 2^X are turned into shifts. This factors code out of the
getelementptr code path for use by other code paths (like malloc and alloca). * Optimize comparisons with zero * Generate neg, not, inc, and dec instructions, when possible. This gives some code size wins, which might translate into performance. We'll see tommorow in the nightly tester. llvm-svn: 9267
This commit is contained in:
Chris Lattner
parent
55a8ef0cc8
commit
bf87734fa0
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@ -140,6 +140,10 @@ namespace {
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void doMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator &MBBI,
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unsigned DestReg, const Type *DestTy,
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unsigned Op0Reg, unsigned Op1Reg);
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void doMultiplyConst(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator &MBBI,
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unsigned DestReg, const Type *DestTy,
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unsigned Op0Reg, unsigned Op1Val);
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void visitMul(BinaryOperator &B);
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void visitDiv(BinaryOperator &B) { visitDivRem(B); }
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@ -153,10 +157,10 @@ namespace {
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// Comparison operators...
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void visitSetCondInst(SetCondInst &I);
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bool EmitComparisonGetSignedness(unsigned OpNum, Value *Op0, Value *Op1,
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MachineBasicBlock *MBB,
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MachineBasicBlock::iterator &MBBI);
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unsigned EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
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MachineBasicBlock *MBB,
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MachineBasicBlock::iterator &MBBI);
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// Memory Instructions
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MachineInstr *doFPLoad(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator &MBBI,
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@ -360,7 +364,7 @@ void ISel::copyConstantToRegister(MachineBasicBlock *MBB,
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default:
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std::cerr << "Offending expr: " << C << "\n";
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assert(0 && "Constant expressions not yet handled!\n");
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assert(0 && "Constant expression not yet handled!\n");
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}
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}
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@ -599,17 +603,23 @@ static unsigned getSetCCNumber(unsigned Opcode) {
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// setge -> setge setae
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// setgt -> setg seta
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// setle -> setle setbe
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static const unsigned SetCCOpcodeTab[2][6] = {
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{X86::SETEr, X86::SETNEr, X86::SETBr, X86::SETAEr, X86::SETAr, X86::SETBEr},
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{X86::SETEr, X86::SETNEr, X86::SETLr, X86::SETGEr, X86::SETGr, X86::SETLEr},
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// ----
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// sets // Used by comparison with 0 optimization
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// setns
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static const unsigned SetCCOpcodeTab[2][8] = {
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{ X86::SETEr, X86::SETNEr, X86::SETBr, X86::SETAEr, X86::SETAr, X86::SETBEr,
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0, 0 },
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{ X86::SETEr, X86::SETNEr, X86::SETLr, X86::SETGEr, X86::SETGr, X86::SETLEr,
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X86::SETSr, X86::SETNSr },
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};
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bool ISel::EmitComparisonGetSignedness(unsigned OpNum, Value *Op0, Value *Op1,
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MachineBasicBlock *MBB,
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MachineBasicBlock::iterator &IP) {
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// EmitComparison - This function emits a comparison of the two operands,
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// returning the extended setcc code to use.
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unsigned ISel::EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
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MachineBasicBlock *MBB,
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MachineBasicBlock::iterator &IP) {
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// The arguments are already supposed to be of the same type.
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const Type *CompTy = Op0->getType();
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bool isSigned = CompTy->isSigned();
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unsigned Class = getClassB(CompTy);
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unsigned Op0r = getReg(Op0, MBB, IP);
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@ -621,14 +631,26 @@ bool ISel::EmitComparisonGetSignedness(unsigned OpNum, Value *Op0, Value *Op1,
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// Mask off any upper bits of the constant, if there are any...
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Op1v &= (1ULL << (8 << Class)) - 1;
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switch (Class) {
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case cByte: BMI(MBB,IP, X86::CMPri8, 2).addReg(Op0r).addZImm(Op1v);break;
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case cShort: BMI(MBB,IP, X86::CMPri16,2).addReg(Op0r).addZImm(Op1v);break;
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case cInt: BMI(MBB,IP, X86::CMPri32,2).addReg(Op0r).addZImm(Op1v);break;
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default:
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assert(0 && "Invalid class!");
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// If this is a comparison against zero, emit more efficient code. We
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// can't handle unsigned comparisons against zero unless they are == or
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// !=. These should have been strength reduced already anyway.
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if (Op1v == 0 && (CompTy->isSigned() || OpNum < 2)) {
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static const unsigned TESTTab[] = {
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X86::TESTrr8, X86::TESTrr16, X86::TESTrr32
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};
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BMI(MBB, IP, TESTTab[Class], 2).addReg(Op0r).addReg(Op0r);
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if (OpNum == 2) return 6; // Map jl -> js
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if (OpNum == 3) return 7; // Map jg -> jns
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return OpNum;
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}
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return isSigned;
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static const unsigned CMPTab[] = {
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X86::CMPri8, X86::CMPri16, X86::CMPri32
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};
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BMI(MBB, IP, CMPTab[Class], 2).addReg(Op0r).addZImm(Op1v);
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return OpNum;
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}
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unsigned Op1r = getReg(Op1, MBB, IP);
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@ -650,7 +672,6 @@ bool ISel::EmitComparisonGetSignedness(unsigned OpNum, Value *Op0, Value *Op1,
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BMI(MBB, IP, X86::FpUCOM, 2).addReg(Op0r).addReg(Op1r);
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BMI(MBB, IP, X86::FNSTSWr8, 0);
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BMI(MBB, IP, X86::SAHF, 1);
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isSigned = false; // Compare with unsigned operators
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break;
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case cLong:
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@ -679,16 +700,16 @@ bool ISel::EmitComparisonGetSignedness(unsigned OpNum, Value *Op0, Value *Op1,
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BMI(MBB, IP, X86::CMPrr32, 2).addReg(Op0r).addReg(Op1r);
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BMI(MBB, IP, SetCCOpcodeTab[0][OpNum], 0, X86::AL);
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BMI(MBB, IP, X86::CMPrr32, 2).addReg(Op0r+1).addReg(Op1r+1);
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BMI(MBB, IP, SetCCOpcodeTab[isSigned][OpNum], 0, X86::BL);
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BMI(MBB, IP, SetCCOpcodeTab[CompTy->isSigned()][OpNum], 0, X86::BL);
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BMI(MBB, IP, X86::IMPLICIT_DEF, 0, X86::BH);
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BMI(MBB, IP, X86::IMPLICIT_DEF, 0, X86::AH);
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BMI(MBB, IP, X86::CMOVErr16, 2, X86::BX).addReg(X86::BX).addReg(X86::AX);
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// NOTE: visitSetCondInst knows that the value is dumped into the BL
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// register at this point for long values...
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return isSigned;
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return OpNum;
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}
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}
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return isSigned;
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return OpNum;
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}
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@ -711,9 +732,13 @@ void ISel::emitSetCCOperation(MachineBasicBlock *MBB,
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Value *Op0, Value *Op1, unsigned Opcode,
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unsigned TargetReg) {
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unsigned OpNum = getSetCCNumber(Opcode);
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bool isSigned = EmitComparisonGetSignedness(OpNum, Op0, Op1, MBB, IP);
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OpNum = EmitComparison(OpNum, Op0, Op1, MBB, IP);
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if (getClassB(Op0->getType()) != cLong || OpNum < 2) {
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const Type *CompTy = Op0->getType();
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unsigned CompClass = getClassB(CompTy);
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bool isSigned = CompTy->isSigned() && CompClass != cFP;
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if (CompClass != cLong || OpNum < 2) {
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// Handle normal comparisons with a setcc instruction...
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BMI(MBB, IP, SetCCOpcodeTab[isSigned][OpNum], 0, TargetReg);
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} else {
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@ -845,9 +870,12 @@ void ISel::visitBranchInst(BranchInst &BI) {
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unsigned OpNum = getSetCCNumber(SCI->getOpcode());
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MachineBasicBlock::iterator MII = BB->end();
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bool isSigned = EmitComparisonGetSignedness(OpNum, SCI->getOperand(0),
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SCI->getOperand(1), BB, MII);
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OpNum = EmitComparison(OpNum, SCI->getOperand(0), SCI->getOperand(1), BB, MII);
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const Type *CompTy = SCI->getOperand(0)->getType();
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bool isSigned = CompTy->isSigned() && getClassB(CompTy) != cFP;
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// LLVM -> X86 signed X86 unsigned
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// ----- ---------- ------------
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// seteq -> je je
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@ -856,9 +884,14 @@ void ISel::visitBranchInst(BranchInst &BI) {
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// setge -> jge jae
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// setgt -> jg ja
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// setle -> jle jbe
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static const unsigned OpcodeTab[2][6] = {
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{ X86::JE, X86::JNE, X86::JB, X86::JAE, X86::JA, X86::JBE },
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{ X86::JE, X86::JNE, X86::JL, X86::JGE, X86::JG, X86::JLE },
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// ----
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// js // Used by comparison with 0 optimization
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// jns
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static const unsigned OpcodeTab[2][8] = {
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{ X86::JE, X86::JNE, X86::JB, X86::JAE, X86::JA, X86::JBE, 0, 0 },
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{ X86::JE, X86::JNE, X86::JL, X86::JGE, X86::JG, X86::JLE,
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X86::JS, X86::JNS },
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};
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if (BI.getSuccessor(0) != NextBB) {
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@ -1049,17 +1082,38 @@ void ISel::visitSimpleBinary(BinaryOperator &B, unsigned OperatorClass) {
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OperatorClass, DestReg);
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}
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/// visitSimpleBinary - Implement simple binary operators for integral types...
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/// OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for Or,
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/// 4 for Xor.
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/// emitSimpleBinaryOperation - Implement simple binary operators for integral
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/// types... OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for
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/// Or, 4 for Xor.
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///
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/// emitSimpleBinaryOperation - Common code shared between visitSimpleBinary
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/// and constant expression support.
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void ISel::emitSimpleBinaryOperation(MachineBasicBlock *BB,
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///
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void ISel::emitSimpleBinaryOperation(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator &IP,
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Value *Op0, Value *Op1,
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unsigned OperatorClass,unsigned TargetReg){
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unsigned OperatorClass, unsigned DestReg) {
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unsigned Class = getClassB(Op0->getType());
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// sub 0, X -> neg X
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if (OperatorClass == 1 && Class != cLong)
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if (ConstantInt *CI = dyn_cast<ConstantInt>(Op0))
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if (CI->isNullValue()) {
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unsigned op1Reg = getReg(Op1, MBB, IP);
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switch (Class) {
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default: assert(0 && "Unknown class for this function!");
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case cByte:
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BMI(MBB, IP, X86::NEGr8, 1, DestReg).addReg(op1Reg);
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return;
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case cShort:
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BMI(MBB, IP, X86::NEGr16, 1, DestReg).addReg(op1Reg);
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return;
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case cInt:
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BMI(MBB, IP, X86::NEGr32, 1, DestReg).addReg(op1Reg);
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return;
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}
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}
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if (!isa<ConstantInt>(Op1) || Class == cLong) {
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static const unsigned OpcodeTab[][4] = {
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// Arithmetic operators
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@ -1080,41 +1134,63 @@ void ISel::emitSimpleBinaryOperation(MachineBasicBlock *BB,
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unsigned Opcode = OpcodeTab[OperatorClass][Class];
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assert(Opcode && "Floating point arguments to logical inst?");
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unsigned Op0r = getReg(Op0, BB, IP);
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unsigned Op1r = getReg(Op1, BB, IP);
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BMI(BB, IP, Opcode, 2, TargetReg).addReg(Op0r).addReg(Op1r);
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unsigned Op0r = getReg(Op0, MBB, IP);
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unsigned Op1r = getReg(Op1, MBB, IP);
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BMI(MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1r);
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if (isLong) { // Handle the upper 32 bits of long values...
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static const unsigned TopTab[] = {
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X86::ADCrr32, X86::SBBrr32, X86::ANDrr32, X86::ORrr32, X86::XORrr32
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};
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BMI(BB, IP, TopTab[OperatorClass], 2,
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TargetReg+1).addReg(Op0r+1).addReg(Op1r+1);
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BMI(MBB, IP, TopTab[OperatorClass], 2,
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DestReg+1).addReg(Op0r+1).addReg(Op1r+1);
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}
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} else {
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// Special case: op Reg, <const>
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ConstantInt *Op1C = cast<ConstantInt>(Op1);
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static const unsigned OpcodeTab[][3] = {
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// Arithmetic operators
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{ X86::ADDri8, X86::ADDri16, X86::ADDri32 }, // ADD
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{ X86::SUBri8, X86::SUBri16, X86::SUBri32 }, // SUB
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// Bitwise operators
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{ X86::ANDri8, X86::ANDri16, X86::ANDri32 }, // AND
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{ X86:: ORri8, X86:: ORri16, X86:: ORri32 }, // OR
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{ X86::XORri8, X86::XORri16, X86::XORri32 }, // XOR
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};
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assert(Class < 3 && "General code handles 64-bit integer types!");
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unsigned Opcode = OpcodeTab[OperatorClass][Class];
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unsigned Op0r = getReg(Op0, BB, IP);
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uint64_t Op1v = cast<ConstantInt>(Op1C)->getRawValue();
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// Mask off any upper bits of the constant, if there are any...
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Op1v &= (1ULL << (8 << Class)) - 1;
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BMI(BB, IP, Opcode, 2, TargetReg).addReg(Op0r).addZImm(Op1v);
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return;
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}
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// Special case: op Reg, <const>
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ConstantInt *Op1C = cast<ConstantInt>(Op1);
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unsigned Op0r = getReg(Op0, MBB, IP);
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// xor X, -1 -> not X
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if (OperatorClass == 4 && Op1C->isAllOnesValue()) {
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static unsigned const NOTTab[] = { X86::NOTr8, X86::NOTr16, X86::NOTr32 };
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BMI(MBB, IP, NOTTab[Class], 1, DestReg).addReg(Op0r);
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return;
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}
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// add X, -1 -> dec X
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if (OperatorClass == 0 && Op1C->isAllOnesValue()) {
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static unsigned const DECTab[] = { X86::DECr8, X86::DECr16, X86::DECr32 };
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BMI(MBB, IP, DECTab[Class], 1, DestReg).addReg(Op0r);
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return;
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}
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// add X, 1 -> inc X
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if (OperatorClass == 0 && Op1C->equalsInt(1)) {
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static unsigned const DECTab[] = { X86::INCr8, X86::INCr16, X86::INCr32 };
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BMI(MBB, IP, DECTab[Class], 1, DestReg).addReg(Op0r);
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return;
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}
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static const unsigned OpcodeTab[][3] = {
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// Arithmetic operators
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{ X86::ADDri8, X86::ADDri16, X86::ADDri32 }, // ADD
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{ X86::SUBri8, X86::SUBri16, X86::SUBri32 }, // SUB
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// Bitwise operators
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{ X86::ANDri8, X86::ANDri16, X86::ANDri32 }, // AND
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{ X86:: ORri8, X86:: ORri16, X86:: ORri32 }, // OR
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{ X86::XORri8, X86::XORri16, X86::XORri32 }, // XOR
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};
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assert(Class < 3 && "General code handles 64-bit integer types!");
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unsigned Opcode = OpcodeTab[OperatorClass][Class];
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uint64_t Op1v = cast<ConstantInt>(Op1C)->getRawValue();
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// Mask off any upper bits of the constant, if there are any...
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Op1v &= (1ULL << (8 << Class)) - 1;
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BMI(MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addZImm(Op1v);
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}
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/// doMultiply - Emit appropriate instructions to multiply together the
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@ -1145,19 +1221,75 @@ void ISel::doMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator &MBBI,
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}
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}
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// ExactLog2 - This function solves for (Val == 1 << (N-1)) and returns N. It
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// returns zero when the input is not exactly a power of two.
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static unsigned ExactLog2(unsigned Val) {
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if (Val == 0) return 0;
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unsigned Count = 0;
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while (Val != 1) {
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if (Val & 1) return 0;
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Val >>= 1;
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++Count;
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}
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return Count+1;
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}
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void ISel::doMultiplyConst(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator &IP,
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unsigned DestReg, const Type *DestTy,
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unsigned op0Reg, unsigned ConstRHS) {
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unsigned Class = getClass(DestTy);
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// If the element size is exactly a power of 2, use a shift to get it.
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if (unsigned Shift = ExactLog2(ConstRHS)) {
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switch (Class) {
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default: assert(0 && "Unknown class for this function!");
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case cByte:
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BMI(MBB, IP, X86::SHLir32, 2, DestReg).addReg(op0Reg).addZImm(Shift-1);
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return;
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case cShort:
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BMI(MBB, IP, X86::SHLir32, 2, DestReg).addReg(op0Reg).addZImm(Shift-1);
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return;
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case cInt:
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BMI(MBB, IP, X86::SHLir32, 2, DestReg).addReg(op0Reg).addZImm(Shift-1);
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return;
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}
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}
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// Most general case, emit a normal multiply...
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static const unsigned MOVirTab[] = {
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X86::MOVir8, X86::MOVir16, X86::MOVir32
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};
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unsigned TmpReg = makeAnotherReg(DestTy);
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BMI(MBB, IP, MOVirTab[Class], 1, TmpReg).addZImm(ConstRHS);
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// Emit a MUL to multiply the register holding the index by
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// elementSize, putting the result in OffsetReg.
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doMultiply(MBB, IP, DestReg, DestTy, op0Reg, TmpReg);
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}
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/// visitMul - Multiplies are not simple binary operators because they must deal
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/// with the EAX register explicitly.
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///
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void ISel::visitMul(BinaryOperator &I) {
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unsigned Op0Reg = getReg(I.getOperand(0));
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unsigned Op1Reg = getReg(I.getOperand(1));
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unsigned DestReg = getReg(I);
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// Simple scalar multiply?
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if (I.getType() != Type::LongTy && I.getType() != Type::ULongTy) {
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MachineBasicBlock::iterator MBBI = BB->end();
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doMultiply(BB, MBBI, DestReg, I.getType(), Op0Reg, Op1Reg);
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if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(1))) {
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unsigned Val = (unsigned)CI->getRawValue(); // Cannot be 64-bit constant
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MachineBasicBlock::iterator MBBI = BB->end();
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doMultiplyConst(BB, MBBI, DestReg, I.getType(), Op0Reg, Val);
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} else {
|
||||
unsigned Op1Reg = getReg(I.getOperand(1));
|
||||
MachineBasicBlock::iterator MBBI = BB->end();
|
||||
doMultiply(BB, MBBI, DestReg, I.getType(), Op0Reg, Op1Reg);
|
||||
}
|
||||
} else {
|
||||
unsigned Op1Reg = getReg(I.getOperand(1));
|
||||
|
||||
// Long value. We have to do things the hard way...
|
||||
// Multiply the two low parts... capturing carry into EDX
|
||||
BuildMI(BB, X86::MOVrr32, 1, X86::EAX).addReg(Op0Reg);
|
||||
|
|
@ -1949,19 +2081,6 @@ void ISel::visitVAArgInst(VAArgInst &I) {
|
|||
}
|
||||
|
||||
|
||||
// ExactLog2 - This function solves for (Val == 1 << (N-1)) and returns N. It
|
||||
// returns zero when the input is not exactly a power of two.
|
||||
static unsigned ExactLog2(unsigned Val) {
|
||||
if (Val == 0) return 0;
|
||||
unsigned Count = 0;
|
||||
while (Val != 1) {
|
||||
if (Val & 1) return 0;
|
||||
Val >>= 1;
|
||||
++Count;
|
||||
}
|
||||
return Count+1;
|
||||
}
|
||||
|
||||
void ISel::visitGetElementPtrInst(GetElementPtrInst &I) {
|
||||
unsigned outputReg = getReg(I);
|
||||
MachineBasicBlock::iterator MI = BB->end();
|
||||
|
|
@ -2040,19 +2159,9 @@ void ISel::emitGEPOperation(MachineBasicBlock *MBB,
|
|||
} else {
|
||||
unsigned idxReg = getReg(idx, MBB, IP);
|
||||
unsigned OffsetReg = makeAnotherReg(Type::UIntTy);
|
||||
if (unsigned Shift = ExactLog2(elementSize)) {
|
||||
// If the element size is exactly a power of 2, use a shift to get it.
|
||||
BMI(MBB, IP, X86::SHLir32, 2,
|
||||
OffsetReg).addReg(idxReg).addZImm(Shift-1);
|
||||
} else {
|
||||
// Most general case, emit a multiply...
|
||||
unsigned elementSizeReg = makeAnotherReg(Type::LongTy);
|
||||
BMI(MBB, IP, X86::MOVir32, 1, elementSizeReg).addZImm(elementSize);
|
||||
|
||||
// Emit a MUL to multiply the register holding the index by
|
||||
// elementSize, putting the result in OffsetReg.
|
||||
doMultiply(MBB, IP, OffsetReg, Type::IntTy, idxReg, elementSizeReg);
|
||||
}
|
||||
|
||||
doMultiplyConst(MBB, IP, OffsetReg, Type::IntTy, idxReg, elementSize);
|
||||
|
||||
// Emit an ADD to add OffsetReg to the basePtr.
|
||||
NextReg = makeAnotherReg(Type::UIntTy);
|
||||
BMI(MBB, IP, X86::ADDrr32, 2,NextReg).addReg(BaseReg).addReg(OffsetReg);
|
||||
|
|
@ -2097,12 +2206,10 @@ void ISel::visitAllocaInst(AllocaInst &I) {
|
|||
// constant by the variable amount.
|
||||
unsigned TotalSizeReg = makeAnotherReg(Type::UIntTy);
|
||||
unsigned SrcReg1 = getReg(I.getArraySize());
|
||||
unsigned SizeReg = makeAnotherReg(Type::UIntTy);
|
||||
BuildMI(BB, X86::MOVir32, 1, SizeReg).addZImm(TySize);
|
||||
|
||||
// TotalSizeReg = mul <numelements>, <TypeSize>
|
||||
MachineBasicBlock::iterator MBBI = BB->end();
|
||||
doMultiply(BB, MBBI, TotalSizeReg, Type::UIntTy, SrcReg1, SizeReg);
|
||||
doMultiplyConst(BB, MBBI, TotalSizeReg, Type::UIntTy, SrcReg1, TySize);
|
||||
|
||||
// AddedSize = add <TotalSizeReg>, 15
|
||||
unsigned AddedSizeReg = makeAnotherReg(Type::UIntTy);
|
||||
|
|
@ -2135,10 +2242,9 @@ void ISel::visitMallocInst(MallocInst &I) {
|
|||
Arg = getReg(ConstantUInt::get(Type::UIntTy, C->getValue() * AllocSize));
|
||||
} else {
|
||||
Arg = makeAnotherReg(Type::UIntTy);
|
||||
unsigned Op0Reg = getReg(ConstantUInt::get(Type::UIntTy, AllocSize));
|
||||
unsigned Op1Reg = getReg(I.getOperand(0));
|
||||
unsigned Op0Reg = getReg(I.getOperand(0));
|
||||
MachineBasicBlock::iterator MBBI = BB->end();
|
||||
doMultiply(BB, MBBI, Arg, Type::UIntTy, Op0Reg, Op1Reg);
|
||||
doMultiplyConst(BB, MBBI, Arg, Type::UIntTy, Op0Reg, AllocSize);
|
||||
}
|
||||
|
||||
std::vector<ValueRecord> Args;
|
||||
|
|
|
|||
Loading…
Reference in New Issue