forked from OSchip/llvm-project
AMDGPU: Assembler support for exp
compr is not currently parsed (or printed) correctly, but that should probably be fixed along with intrinsic changes. llvm-svn: 288698
This commit is contained in:
Matt Arsenault
parent
8a63cb9044
commit
bf6bdac1ad
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@ -135,9 +135,11 @@ public:
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ImmTyDA,
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ImmTyR128,
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ImmTyLWE,
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ImmTyExpTgt,
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ImmTyExpCompr,
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ImmTyExpVM,
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ImmTyHwreg,
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ImmTyOff,
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ImmTySendMsg,
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};
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@ -215,6 +217,10 @@ public:
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return isRegOrImmWithInputMods(MVT::f64);
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}
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bool isVReg32OrOff() const {
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return isOff() || isRegClass(AMDGPU::VGPR_32RegClassID);
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}
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bool isImmTy(ImmTy ImmT) const {
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return isImm() && Imm.Type == ImmT;
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}
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@ -230,6 +236,8 @@ public:
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bool isDA() const { return isImmTy(ImmTyDA); }
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bool isR128() const { return isImmTy(ImmTyUNorm); }
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bool isLWE() const { return isImmTy(ImmTyLWE); }
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bool isOff() const { return isImmTy(ImmTyOff); }
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bool isExpTgt() const { return isImmTy(ImmTyExpTgt); }
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bool isExpVM() const { return isImmTy(ImmTyExpVM); }
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bool isExpCompr() const { return isImmTy(ImmTyExpCompr); }
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bool isOffen() const { return isImmTy(ImmTyOffen); }
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@ -460,7 +468,7 @@ public:
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}
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}
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void printImmTy(raw_ostream& OS, ImmTy Type) const {
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static void printImmTy(raw_ostream& OS, ImmTy Type) {
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switch (Type) {
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case ImmTyNone: OS << "None"; break;
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case ImmTyGDS: OS << "GDS"; break;
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@ -488,6 +496,8 @@ public:
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case ImmTyDA: OS << "DA"; break;
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case ImmTyR128: OS << "R128"; break;
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case ImmTyLWE: OS << "LWE"; break;
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case ImmTyOff: OS << "Off"; break;
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case ImmTyExpTgt: OS << "ExpTgt"; break;
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case ImmTyExpCompr: OS << "ExpCompr"; break;
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case ImmTyExpVM: OS << "ExpVM"; break;
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case ImmTyHwreg: OS << "Hwreg"; break;
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@ -713,9 +723,11 @@ public:
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OperandMatchResultTy parseRegOrImm(OperandVector &Operands);
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OperandMatchResultTy parseRegOrImmWithFPInputMods(OperandVector &Operands);
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OperandMatchResultTy parseRegOrImmWithIntInputMods(OperandVector &Operands);
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OperandMatchResultTy parseVReg32OrOff(OperandVector &Operands);
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void cvtDSOffset01(MCInst &Inst, const OperandVector &Operands);
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void cvtDS(MCInst &Inst, const OperandVector &Operands);
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void cvtExp(MCInst &Inst, const OperandVector &Operands);
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bool parseCnt(int64_t &IntVal);
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OperandMatchResultTy parseSWaitCntOps(OperandVector &Operands);
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@ -730,9 +742,14 @@ private:
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bool parseSendMsgConstruct(OperandInfoTy &Msg, OperandInfoTy &Operation, int64_t &StreamId);
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bool parseHwregConstruct(OperandInfoTy &HwReg, int64_t &Offset, int64_t &Width);
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void errorExpTgt();
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OperandMatchResultTy parseExpTgtImpl(StringRef Str, uint8_t &Val);
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public:
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OperandMatchResultTy parseOptionalOperand(OperandVector &Operands);
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OperandMatchResultTy parseExpTgt(OperandVector &Operands);
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OperandMatchResultTy parseSendMsgOp(OperandVector &Operands);
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OperandMatchResultTy parseSOppBrTarget(OperandVector &Operands);
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@ -751,6 +768,7 @@ public:
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AMDGPUOperand::Ptr defaultSMRDOffset8() const;
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AMDGPUOperand::Ptr defaultSMRDOffset20() const;
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AMDGPUOperand::Ptr defaultSMRDLiteralOffset() const;
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AMDGPUOperand::Ptr defaultExpTgt() const;
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AMDGPUOperand::Ptr defaultExpCompr() const;
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AMDGPUOperand::Ptr defaultExpVM() const;
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@ -1358,9 +1376,28 @@ AMDGPUAsmParser::parseRegOrImmWithIntInputMods(OperandVector &Operands) {
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AMDGPUOperand &Op = static_cast<AMDGPUOperand &>(*Operands.back());
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Op.setModifiers(Mods);
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}
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return MatchOperand_Success;
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}
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OperandMatchResultTy AMDGPUAsmParser::parseVReg32OrOff(OperandVector &Operands) {
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std::unique_ptr<AMDGPUOperand> Reg = parseRegister();
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if (Reg) {
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Operands.push_back(std::move(Reg));
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return MatchOperand_Success;
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}
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const AsmToken &Tok = Parser.getTok();
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if (Tok.getString() == "off") {
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Operands.push_back(AMDGPUOperand::CreateImm(this, 0, Tok.getLoc(),
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AMDGPUOperand::ImmTyOff, false));
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Parser.Lex();
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return MatchOperand_Success;
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}
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return MatchOperand_NoMatch;
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}
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unsigned AMDGPUAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
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uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags;
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@ -2000,6 +2037,46 @@ void AMDGPUAsmParser::cvtDS(MCInst &Inst, const OperandVector &Operands) {
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Inst.addOperand(MCOperand::createReg(AMDGPU::M0)); // m0
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}
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void AMDGPUAsmParser::cvtExp(MCInst &Inst, const OperandVector &Operands) {
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OptionalImmIndexMap OptionalIdx;
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unsigned EnMask = 0;
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int SrcIdx = 0;
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for (unsigned i = 1, e = Operands.size(); i != e; ++i) {
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AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
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// Add the register arguments
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if (Op.isReg()) {
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EnMask |= (1 << SrcIdx);
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Op.addRegOperands(Inst, 1);
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++SrcIdx;
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continue;
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}
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if (Op.isOff()) {
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++SrcIdx;
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Inst.addOperand(MCOperand::createReg(AMDGPU::NoRegister));
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continue;
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}
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if (Op.isImm() && Op.getImmTy() == AMDGPUOperand::ImmTyExpTgt) {
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Op.addImmOperands(Inst, 1);
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continue;
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}
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if (Op.isToken() && Op.getToken() == "done")
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continue;
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// Handle optional arguments
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OptionalIdx[Op.getImmTy()] = i;
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}
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addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyExpVM);
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addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyExpCompr);
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Inst.addOperand(MCOperand::createImm(EnMask));
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}
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//===----------------------------------------------------------------------===//
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// s_waitcnt
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@ -2274,6 +2351,85 @@ bool AMDGPUAsmParser::parseSendMsgConstruct(OperandInfoTy &Msg, OperandInfoTy &O
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return false;
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}
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void AMDGPUAsmParser::errorExpTgt() {
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Error(Parser.getTok().getLoc(), "invalid exp target");
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}
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OperandMatchResultTy AMDGPUAsmParser::parseExpTgtImpl(StringRef Str,
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uint8_t &Val) {
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if (Str == "null") {
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Val = 9;
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return MatchOperand_Success;
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}
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if (Str.startswith("mrt")) {
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Str = Str.drop_front(3);
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if (Str == "z") { // == mrtz
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Val = 8;
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return MatchOperand_Success;
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}
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if (Str.getAsInteger(10, Val))
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return MatchOperand_ParseFail;
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if (Val > 7)
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errorExpTgt();
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return MatchOperand_Success;
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}
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if (Str.startswith("pos")) {
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Str = Str.drop_front(3);
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if (Str.getAsInteger(10, Val))
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return MatchOperand_ParseFail;
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if (Val > 3)
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errorExpTgt();
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Val += 12;
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return MatchOperand_Success;
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}
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if (Str.startswith("param")) {
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Str = Str.drop_front(5);
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if (Str.getAsInteger(10, Val))
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return MatchOperand_ParseFail;
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if (Val >= 32)
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errorExpTgt();
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Val += 32;
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return MatchOperand_Success;
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}
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if (Str.startswith("invalid_target_")) {
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Str = Str.drop_front(15);
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if (Str.getAsInteger(10, Val))
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return MatchOperand_ParseFail;
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errorExpTgt();
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return MatchOperand_Success;
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}
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return MatchOperand_NoMatch;
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}
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OperandMatchResultTy AMDGPUAsmParser::parseExpTgt(OperandVector &Operands) {
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uint8_t Val;
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StringRef Str = Parser.getTok().getString();
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auto Res = parseExpTgtImpl(Str, Val);
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if (Res != MatchOperand_Success)
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return Res;
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SMLoc S = Parser.getTok().getLoc();
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Parser.Lex();
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Operands.push_back(AMDGPUOperand::CreateImm(this, Val, S,
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AMDGPUOperand::ImmTyExpTgt));
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return MatchOperand_Success;
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}
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OperandMatchResultTy
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AMDGPUAsmParser::parseSendMsgOp(OperandVector &Operands) {
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using namespace llvm::AMDGPU::SendMsg;
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@ -2539,6 +2695,10 @@ AMDGPUOperand::Ptr AMDGPUAsmParser::defaultLWE() const {
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return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyLWE);
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}
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AMDGPUOperand::Ptr AMDGPUAsmParser::defaultExpTgt() const {
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return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyExpTgt);
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}
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AMDGPUOperand::Ptr AMDGPUAsmParser::defaultExpCompr() const {
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return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyExpCompr);
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}
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@ -2643,6 +2803,7 @@ static const OptionalOperand AMDGPUOptionalOperandTable[] = {
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{"src0_sel", AMDGPUOperand::ImmTySdwaSrc0Sel, false, nullptr},
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{"src1_sel", AMDGPUOperand::ImmTySdwaSrc1Sel, false, nullptr},
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{"dst_unused", AMDGPUOperand::ImmTySdwaDstUnused, false, nullptr},
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{"vm", AMDGPUOperand::ImmTyExpVM, true, nullptr},
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};
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OperandMatchResultTy AMDGPUAsmParser::parseOptionalOperand(OperandVector &Operands) {
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@ -3125,6 +3286,9 @@ unsigned AMDGPUAsmParser::validateTargetOperandClass(MCParsedAsmOperand &Op,
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return Operand.isSSrcF32() ? Match_Success : Match_InvalidOperand;
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case MCK_SoppBrTarget:
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return Operand.isSoppBrTarget() ? Match_Success : Match_InvalidOperand;
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default: return Match_InvalidOperand;
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case MCK_VReg32OrOff:
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return Operand.isVReg32OrOff() ? Match_Success : Match_InvalidOperand;
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default:
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return Match_InvalidOperand;
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}
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}
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@ -315,6 +315,13 @@ def SendMsgMatchClass : AsmOperandClass {
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let RenderMethod = "addImmOperands";
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}
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def ExpTgtMatchClass : AsmOperandClass {
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let Name = "ExpTgt";
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let PredicateMethod = "isExpTgt";
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let ParserMethod = "parseExpTgt";
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let RenderMethod = "printExpTgt";
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}
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def SendMsgImm : Operand<i32> {
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let PrintMethod = "printSendMsg";
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let ParserMatchClass = SendMsgMatchClass;
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@ -326,6 +333,11 @@ def SWaitMatchClass : AsmOperandClass {
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let ParserMethod = "parseSWaitCntOps";
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}
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def VReg32OrOffClass : AsmOperandClass {
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let Name = "VReg32OrOff";
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let ParserMethod = "parseVReg32OrOff";
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}
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def WAIT_FLAG : Operand <i32> {
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let ParserMatchClass = SWaitMatchClass;
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let PrintMethod = "printWaitFlag";
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@ -334,6 +346,31 @@ def WAIT_FLAG : Operand <i32> {
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include "SIInstrFormats.td"
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include "VIInstrFormats.td"
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// ===----------------------------------------------------------------------===//
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// ExpSrc* Special cases for exp src operands which are printed as
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// "off" depending on en operand.
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// ===----------------------------------------------------------------------===//
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def ExpSrc0 : RegisterOperand<VGPR_32> {
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let PrintMethod = "printExpSrc0";
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let ParserMatchClass = VReg32OrOffClass;
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}
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def ExpSrc1 : RegisterOperand<VGPR_32> {
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let PrintMethod = "printExpSrc1";
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let ParserMatchClass = VReg32OrOffClass;
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}
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def ExpSrc2 : RegisterOperand<VGPR_32> {
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let PrintMethod = "printExpSrc2";
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let ParserMatchClass = VReg32OrOffClass;
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}
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def ExpSrc3 : RegisterOperand<VGPR_32> {
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let PrintMethod = "printExpSrc3";
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let ParserMatchClass = VReg32OrOffClass;
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}
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class NamedMatchClass<string CName, bit Optional = 1> : AsmOperandClass {
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let Name = "Imm"#CName;
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let PredicateMethod = "is"#CName;
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@ -402,8 +439,8 @@ def dst_unused : NamedOperandU32<"SDWADstUnused", NamedMatchClass<"SDWADstUnused
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def hwreg : NamedOperandU16<"Hwreg", NamedMatchClass<"Hwreg", 0>>;
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def exp_tgt : Operand<i8> {
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let PrintMethod = "printExpTgt";
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def exp_tgt : NamedOperandU8<"ExpTgt", NamedMatchClass<"ExpTgt", 0>> {
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}
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} // End OperandType = "OPERAND_IMMEDIATE"
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@ -531,8 +568,9 @@ class EXP_Helper<bit done, SDPatternOperator node = null_frag> : EXPCommon<
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exp_vm:$vm, exp_compr:$compr, i8imm:$en),
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"exp$tgt $src0, $src1, $src2, $src3"#!if(done, " done", "")#"$compr$vm",
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[(node (i8 timm:$en), (i1 timm:$vm), (i8 timm:$tgt), (i1 timm:$compr),
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f32:$src0, f32:$src1, f32:$src2, f32:$src3)]
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>;
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f32:$src0, f32:$src1, f32:$src2, f32:$src3)]> {
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let AsmMatchConverter = "cvtExp";
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}
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// Split EXP instruction into EXP and EXP_DONE so we can set
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// mayLoad for done=1.
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@ -449,24 +449,3 @@ def VRegSrc_32 : RegisterOperand<VGPR_32> {
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//===----------------------------------------------------------------------===//
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defm VCSrc : RegInlineOperand<"VS", "VCSrc">;
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// ===----------------------------------------------------------------------===//
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// ExpSrc* Special cases for exp src operands which are printed as
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// "off" depending on en operand.
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// ===----------------------------------------------------------------------===//
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def ExpSrc0 : RegisterOperand<VGPR_32> {
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let PrintMethod = "printExpSrc0";
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}
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def ExpSrc1 : RegisterOperand<VGPR_32> {
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let PrintMethod = "printExpSrc1";
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}
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def ExpSrc2 : RegisterOperand<VGPR_32> {
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let PrintMethod = "printExpSrc2";
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}
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def ExpSrc3 : RegisterOperand<VGPR_32> {
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let PrintMethod = "printExpSrc3";
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}
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@ -0,0 +1,107 @@
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// RUN: not llvm-mc -arch=amdgcn -show-encoding %s 2>&1 | FileCheck -check-prefix=GCN %s
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// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s 2>&1 | FileCheck -check-prefix=GCN %s
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exp mrt8 v3, v2, v1, v0
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// GCN: :5: error: invalid exp target
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exp pos4 v3, v2, v1, v0
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// GCN: :5: error: invalid exp target
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exp param32 v3, v2, v1, v0
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// GCN: :5: error: invalid exp target
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exp invalid_target_10 v3, v2, v1, v0
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// GCN: :5: error: invalid exp target
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exp invalid_target_10 v3, v2, v1, v0 done
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// GCN: :5: error: invalid exp target
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exp invalid_target_11 v3, v2, v1, v0
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// GCN: :5: error: invalid exp target
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exp invalid_target_11 v3, v2, v1, v0 done
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// GCN: :5: error: invalid exp target
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exp mrt-1 v3, v2, v1, v0
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// GCN: :5: error: failed parsing operand
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exp mrtX v3, v2, v1, v0
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// GCN: :5: error: failed parsing operand
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exp pos-1 v3, v2, v1, v0
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// GCN: :5: error: failed parsing operand
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exp posX v3, v2, v1, v0
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// GCN: :5: error: failed parsing operand
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exp param-1 v3, v2, v1, v0
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// GCN: :5: error: failed parsing operand
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exp paramX v3, v2, v1, v0
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// GCN: :5: error: failed parsing operand
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exp invalid_target_-1 v3, v2, v1, v0
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// GCN: :5: error: failed parsing operand
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exp invalid_target_X v3, v2, v1, v0
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// GCN: :5: error: failed parsing operand
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exp mrt0 s0, v0, v0, v0
|
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// GCN: 10: error: invalid operand for instruction
|
||||
|
||||
exp mrt0 v0, s0, v0, v0
|
||||
// GCN: 14: error: invalid operand for instruction
|
||||
|
||||
exp mrt0 v0, v0, s0, v0
|
||||
// GCN: 18: error: invalid operand for instruction
|
||||
|
||||
exp mrt0 v0, v0, v0, s0
|
||||
// GCN: 22: error: invalid operand for instruction
|
||||
|
||||
exp mrt0 v[0:1], v0, v0, v0
|
||||
// GCN: 10: error: invalid operand for instruction
|
||||
|
||||
exp mrt0 v0, v[0:1], v0, v0
|
||||
// GCN: 14: error: invalid operand for instruction
|
||||
|
||||
exp mrt0 v0, v0, v[0:1], v0
|
||||
// GCN: 18: error: invalid operand for instruction
|
||||
|
||||
exp mrt0 v0, v0, v0, v[0:1]
|
||||
// GCN: 22: error: invalid operand for instruction
|
||||
|
||||
exp mrt0 1.0, v0, v0, v0
|
||||
// GCN: 10: error: invalid operand for instruction
|
||||
|
||||
exp mrt0 v0, 1.0, v0, v0
|
||||
// GCN: 14: error: invalid operand for instruction
|
||||
|
||||
exp mrt0 v0, v0, 1.0, v0
|
||||
// GCN: 18: error: invalid operand for instruction
|
||||
|
||||
exp mrt0 v0, v0, v0, 1.0
|
||||
// GCN: 22: error: invalid operand for instruction
|
||||
|
||||
exp mrt0 7, v0, v0, v0
|
||||
// GCN: 10: error: invalid operand for instruction
|
||||
|
||||
exp mrt0 v0, 7, v0, v0
|
||||
// GCN: 14: error: invalid operand for instruction
|
||||
|
||||
exp mrt0 v0, v0, 7, v0
|
||||
// GCN: 18: error: invalid operand for instruction
|
||||
|
||||
exp mrt0 v0, v0, v0, 7
|
||||
// GCN: 22: error: invalid operand for instruction
|
||||
|
||||
exp mrt0 0x12345678, v0, v0, v0
|
||||
// GCN: 10: error: invalid operand for instruction
|
||||
|
||||
exp mrt0 v0, 0x12345678, v0, v0
|
||||
// GCN: 14: error: invalid operand for instruction
|
||||
|
||||
exp mrt0 v0, v0, 0x12345678, v0
|
||||
// GCN: 18: error: invalid operand for instruction
|
||||
|
||||
exp mrt0 v0, v0, v0, 0x12345678
|
||||
// GCN: 22: error: invalid operand for instruction
|
||||
|
|
@ -0,0 +1,86 @@
|
|||
// RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
|
||||
// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
|
||||
|
||||
exp mrt0 off, off, off, off
|
||||
// GCN: exp mrt0 off, off, off, off ; encoding: [0x00,0x00,0x00,0xf8,0x00,0x00,0x00,0x00]
|
||||
|
||||
exp mrt0 off, off, off, off done
|
||||
// GCN: exp mrt0 off, off, off, off done ; encoding: [0x00,0x08,0x00,0xf8,0x00,0x00,0x00,0x00]
|
||||
|
||||
exp mrt0 v4, off, off, off done
|
||||
// GCN: exp mrt0 v4, off, off, off done ; encoding: [0x01,0x08,0x00,0xf8,0x04,0x00,0x00,0x00]
|
||||
|
||||
exp mrt0 off, v3, off, off done
|
||||
// GCN: exp mrt0 off, v3, off, off done ; encoding: [0x02,0x08,0x00,0xf8,0x00,0x03,0x00,0x00]
|
||||
|
||||
exp mrt0 off, off, v2, off done
|
||||
// GCN: exp mrt0 off, off, v2, off done ; encoding: [0x04,0x08,0x00,0xf8,0x00,0x00,0x02,0x00]
|
||||
|
||||
exp mrt0 off, off, off, v1 done
|
||||
// GCN: exp mrt0 off, off, off, v1 done ; encoding: [0x08,0x08,0x00,0xf8,0x00,0x00,0x00,0x01]
|
||||
|
||||
exp mrt0 v4, v3, off, off done
|
||||
// GCN: exp mrt0 v4, v3, off, off done ; encoding: [0x03,0x08,0x00,0xf8,0x04,0x03,0x00,0x00]
|
||||
|
||||
exp mrt0 v4, off, v2, off done
|
||||
// GCN: exp mrt0 v4, off, v2, off done ; encoding: [0x05,0x08,0x00,0xf8,0x04,0x00,0x02,0x00]
|
||||
|
||||
exp mrt0 v4, off, off, v1
|
||||
// GCN: exp mrt0 v4, off, off, v1 ; encoding: [0x09,0x00,0x00,0xf8,0x04,0x00,0x00,0x01]
|
||||
|
||||
exp mrt0 v4, off, off, v1 done
|
||||
// GCN: exp mrt0 v4, off, off, v1 done ; encoding: [0x09,0x08,0x00,0xf8,0x04,0x00,0x00,0x01]
|
||||
|
||||
exp mrt0 v4, v3, v2, v1
|
||||
// GCN: exp mrt0 v4, v3, v2, v1 ; encoding: [0x0f,0x00,0x00,0xf8,0x04,0x03,0x02,0x01]
|
||||
|
||||
exp mrt0 v4, v3, v2, v1 done
|
||||
// GCN: exp mrt0 v4, v3, v2, v1 done ; encoding: [0x0f,0x08,0x00,0xf8,0x04,0x03,0x02,0x01]
|
||||
|
||||
exp mrt7 v1, v1, v1, v1
|
||||
// GCN: exp mrt7 v1, v1, v1, v1 ; encoding: [0x7f,0x00,0x00,0xf8,0x01,0x01,0x01,0x01]
|
||||
|
||||
exp mrt7 v1, v1, v1, v1 done
|
||||
// GCN: exp mrt7 v1, v1, v1, v1 done ; encoding: [0x7f,0x08,0x00,0xf8,0x01,0x01,0x01,0x01]
|
||||
|
||||
exp mrtz v4, v3, v2, v1
|
||||
// GCN: exp mrtz v4, v3, v2, v1 ; encoding: [0x8f,0x00,0x00,0xf8,0x04,0x03,0x02,0x01]
|
||||
|
||||
exp mrtz v4, v3, v2, v1 done
|
||||
// GCN: exp mrtz v4, v3, v2, v1 done ; encoding: [0x8f,0x08,0x00,0xf8,0x04,0x03,0x02,0x01]
|
||||
|
||||
exp null v4, v3, v2, v1
|
||||
// GCN: exp null v4, v3, v2, v1 ; encoding: [0x9f,0x00,0x00,0xf8,0x04,0x03,0x02,0x01]
|
||||
|
||||
exp null v4, v3, v2, v1 done
|
||||
// GCN: exp null v4, v3, v2, v1 done ; encoding: [0x9f,0x08,0x00,0xf8,0x04,0x03,0x02,0x01]
|
||||
|
||||
exp pos0 v4, v3, v2, v1
|
||||
// GCN: exp pos0 v4, v3, v2, v1 ; encoding: [0xcf,0x00,0x00,0xf8,0x04,0x03,0x02,0x01]
|
||||
|
||||
exp pos0 v4, v3, v2, v1 done
|
||||
// GCN: exp pos0 v4, v3, v2, v1 done ; encoding: [0xcf,0x08,0x00,0xf8,0x04,0x03,0x02,0x01]
|
||||
|
||||
exp pos3 v4, v3, v2, v1
|
||||
// GCN: exp pos3 v4, v3, v2, v1 ; encoding: [0xff,0x00,0x00,0xf8,0x04,0x03,0x02,0x01]
|
||||
|
||||
exp pos3 v4, v3, v2, v1 done
|
||||
// GCN: exp pos3 v4, v3, v2, v1 done ; encoding: [0xff,0x08,0x00,0xf8,0x04,0x03,0x02,0x01]
|
||||
|
||||
exp param0 v4, v3, v2, v1
|
||||
// GCN: exp param0 v4, v3, v2, v1 ; encoding: [0x0f,0x02,0x00,0xf8,0x04,0x03,0x02,0x01]
|
||||
|
||||
exp param0 v4, v3, v2, v1 done
|
||||
// GCN: exp param0 v4, v3, v2, v1 done ; encoding: [0x0f,0x0a,0x00,0xf8,0x04,0x03,0x02,0x01]
|
||||
|
||||
exp param31 v4, v3, v2, v1
|
||||
// GCN: exp param31 v4, v3, v2, v1 ; encoding: [0xff,0x03,0x00,0xf8,0x04,0x03,0x02,0x01]
|
||||
|
||||
exp param31 v4, v3, v2, v1 done
|
||||
// GCN: exp param31 v4, v3, v2, v1 done ; encoding: [0xff,0x0b,0x00,0xf8,0x04,0x03,0x02,0x01]
|
||||
|
||||
exp mrt0 v4, v3, v2, v1 vm
|
||||
// GCN: exp mrt0 v4, v3, v2, v1 vm ; encoding: [0x0f,0x10,0x00,0xf8,0x04,0x03,0x02,0x01]
|
||||
|
||||
exp mrt0 v4, v3, v2, v1 done vm
|
||||
// GCN: exp mrt0 v4, v3, v2, v1 done vm ; encoding: [0x0f,0x18,0x00,0xf8,0x04,0x03,0x02,0x01]
|
||||
Loading…
Reference in New Issue