forked from OSchip/llvm-project
[ARM] GlobalISel: Support array returns
These are a bit rare in practice, but they don't require anything special compared to array parameters, so support them as well. llvm-svn: 304137
This commit is contained in:
Diana Picus
parent
d9fb2842e7
commit
bf4aed2c38
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@ -214,8 +214,9 @@ bool ARMCallLowering::lowerReturnVal(MachineIRBuilder &MIRBuilder,
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SmallVector<ArgInfo, 4> SplitVTs;
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ArgInfo RetInfo(VReg, Val->getType());
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setArgFlags(RetInfo, AttributeList::ReturnIndex, DL, F);
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splitToValueTypes(RetInfo, SplitVTs, MF,
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[&](unsigned Reg, uint64_t Offset) {});
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splitToValueTypes(RetInfo, SplitVTs, MF, [&](unsigned Reg, uint64_t Offset) {
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MIRBuilder.buildExtract(Reg, VReg, Offset);
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});
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CCAssignFn *AssignFn =
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TLI.CCAssignFnForReturn(F.getCallingConv(), F.isVarArg());
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@ -476,13 +477,34 @@ bool ARMCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
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return false;
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ArgInfos.clear();
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SmallVector<uint64_t, 8> RegOffsets;
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SmallVector<unsigned, 8> SplitRegs;
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splitToValueTypes(OrigRet, ArgInfos, MF,
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[&](unsigned Reg, uint64_t Offset) {});
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[&](unsigned Reg, uint64_t Offset) {
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RegOffsets.push_back(Offset);
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SplitRegs.push_back(Reg);
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});
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auto RetAssignFn = TLI.CCAssignFnForReturn(CallConv, /*IsVarArg=*/false);
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CallReturnHandler RetHandler(MIRBuilder, MRI, MIB, RetAssignFn);
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if (!handleAssignments(MIRBuilder, ArgInfos, RetHandler))
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return false;
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if (!RegOffsets.empty()) {
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// We have split the value and allocated each individual piece, now build
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// it up again.
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LLT Ty = MRI.getType(OrigRet.Reg);
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unsigned Dst = MRI.createGenericVirtualRegister(Ty);
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MIRBuilder.buildUndef(Dst);
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for (unsigned i = 0; i < SplitRegs.size(); ++i) {
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unsigned Tmp = MRI.createGenericVirtualRegister(Ty);
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MIRBuilder.buildInsert(Tmp, Dst, SplitRegs[i], RegOffsets[i]);
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Dst = Tmp;
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}
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MIRBuilder.buildCopy(OrigRet.Reg, Dst);
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}
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}
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// We now know the size of the stack - update the ADJCALLSTACKDOWN
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@ -620,9 +620,9 @@ entry:
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ret float %r
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}
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declare arm_aapcscc void @tiny_int_arrays_target([2 x i32])
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declare arm_aapcscc [3 x i32] @tiny_int_arrays_target([2 x i32])
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define arm_aapcscc void @test_tiny_int_arrays([2 x i32] %arr) {
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define arm_aapcscc [3 x i32] @test_tiny_int_arrays([2 x i32] %arr) {
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; CHECK-LABEL: name: test_tiny_int_arrays
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; CHECK: liveins: %r0, %r1
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; CHECK: [[R0:%[0-9]+]](s32) = COPY %r0
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@ -636,12 +636,29 @@ define arm_aapcscc void @test_tiny_int_arrays([2 x i32] %arr) {
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; CHECK: [[R1:%[0-9]+]](s32) = G_EXTRACT [[ARG_ARR]](s64), 32
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; CHECK: %r0 = COPY [[R0]]
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; CHECK: %r1 = COPY [[R1]]
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; CHECK: BLX @tiny_int_arrays_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1
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; CHECK: BLX @tiny_int_arrays_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit-def %r0, implicit-def %r1
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; CHECK: [[R0:%[0-9]+]](s32) = COPY %r0
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; CHECK: [[R1:%[0-9]+]](s32) = COPY %r1
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; CHECK: [[R2:%[0-9]+]](s32) = COPY %r2
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; CHECK: [[RES_ARR0:%[0-9]+]](s96) = IMPLICIT_DEF
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; CHECK: [[RES_ARR1:%[0-9]+]](s96) = G_INSERT [[RES_ARR0]], [[R0]](s32), 0
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; CHECK: [[RES_ARR2:%[0-9]+]](s96) = G_INSERT [[RES_ARR1]], [[R1]](s32), 32
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; CHECK: [[RES_ARR3:%[0-9]+]](s96) = G_INSERT [[RES_ARR2]], [[R2]](s32), 64
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; CHECK: [[RES_ARR:%[0-9]+]](s96) = COPY [[RES_ARR3]]
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; CHECK: ADJCALLSTACKUP 0, 0, 14, _, implicit-def %sp, implicit %sp
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; CHECK: BX_RET 14, _
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; CHECK: [[R0:%[0-9]+]](s32) = G_EXTRACT [[RES_ARR]](s96), 0
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; CHECK: [[R1:%[0-9]+]](s32) = G_EXTRACT [[RES_ARR]](s96), 32
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; CHECK: [[R2:%[0-9]+]](s32) = G_EXTRACT [[RES_ARR]](s96), 64
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; FIXME: This doesn't seem correct with regard to the AAPCS docs (which say
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; that composite types larger than 4 bytes should be passed through memory),
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; but it's what DAGISel does. We should fix it in the common code for both.
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; CHECK: %r0 = COPY [[R0]]
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; CHECK: %r1 = COPY [[R1]]
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; CHECK: %r2 = COPY [[R2]]
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; CHECK: BX_RET 14, _, implicit %r0, implicit %r1, implicit %r2
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entry:
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notail call arm_aapcscc void @tiny_int_arrays_target([2 x i32] %arr)
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ret void
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%r = notail call arm_aapcscc [3 x i32] @tiny_int_arrays_target([2 x i32] %arr)
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ret [3 x i32] %r
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}
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declare arm_aapcscc void @multiple_int_arrays_target([2 x i32], [2 x i32])
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@ -662,6 +679,14 @@ define arm_aapcscc void @test_multiple_int_arrays([2 x i32] %arr0, [2 x i32] %ar
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; CHECK: [[ARG_ARR1_2:%[0-9]+]](s64) = G_INSERT [[ARG_ARR1_1]], [[R3]](s32), 32
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; CHECK: [[ARG_ARR1:%[0-9]+]](s64) = COPY [[ARG_ARR1_2]]
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; CHECK: ADJCALLSTACKDOWN 0, 0, 14, _, implicit-def %sp, implicit %sp
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; CHECK: [[R0:%[0-9]+]](s32) = G_EXTRACT [[ARG_ARR0]](s64), 0
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; CHECK: [[R1:%[0-9]+]](s32) = G_EXTRACT [[ARG_ARR0]](s64), 32
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; CHECK: [[R2:%[0-9]+]](s32) = G_EXTRACT [[ARG_ARR1]](s64), 0
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; CHECK: [[R3:%[0-9]+]](s32) = G_EXTRACT [[ARG_ARR1]](s64), 32
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; CHECK: %r0 = COPY [[R0]]
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; CHECK: %r1 = COPY [[R1]]
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; CHECK: %r2 = COPY [[R2]]
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; CHECK: %r3 = COPY [[R3]]
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; CHECK: BLX @multiple_int_arrays_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit %r3
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; CHECK: ADJCALLSTACKUP 0, 0, 14, _, implicit-def %sp, implicit %sp
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; CHECK: BX_RET 14, _
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@ -725,9 +750,9 @@ entry:
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ret void
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}
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declare arm_aapcscc void @fp_arrays_aapcs_target([3 x double])
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declare arm_aapcscc [2 x float] @fp_arrays_aapcs_target([3 x double])
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define arm_aapcscc void @test_fp_arrays_aapcs([3 x double] %arr) {
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define arm_aapcscc [2 x float] @test_fp_arrays_aapcs([3 x double] %arr) {
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; CHECK-LABEL: name: test_fp_arrays_aapcs
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; CHECK: fixedStack:
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; CHECK: id: [[ARR2_ID:[0-9]+]], offset: 0, size: 8
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@ -767,17 +792,27 @@ define arm_aapcscc void @test_fp_arrays_aapcs([3 x double] %arr) {
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; CHECK: [[ARR2_OFFSET:%[0-9]+]](s32) = G_CONSTANT i32 0
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; CHECK: [[ARR2_ADDR:%[0-9]+]](p0) = G_GEP [[SP]], [[ARR2_OFFSET]](s32)
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; CHECK: G_STORE [[ARR2]](s64), [[ARR2_ADDR]](p0){{.*}}store 8
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; CHECK: BLX @fp_arrays_aapcs_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit %r3
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; CHECK: BLX @fp_arrays_aapcs_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1
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; CHECK: [[R0:%[0-9]+]](s32) = COPY %r0
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; CHECK: [[R1:%[0-9]+]](s32) = COPY %r1
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; CHECK: [[R_MERGED_0:%[0-9]+]](s64) = IMPLICIT_DEF
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; CHECK: [[R_MERGED_1:%[0-9]+]](s64) = G_INSERT [[R_MERGED_0]], [[R0]](s32), 0
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; CHECK: [[R_MERGED_2:%[0-9]+]](s64) = G_INSERT [[R_MERGED_1]], [[R1]](s32), 32
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; CHECK: [[R_MERGED:%[0-9]+]](s64) = COPY [[R_MERGED_2]]
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; CHECK: ADJCALLSTACKUP 8, 0, 14, _, implicit-def %sp, implicit %sp
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; CHECK: BX_RET 14, _
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; CHECK: [[R0:%[0-9]+]](s32) = G_EXTRACT [[R_MERGED]](s64), 0
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; CHECK: [[R1:%[0-9]+]](s32) = G_EXTRACT [[R_MERGED]](s64), 32
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; CHECK: %r0 = COPY [[R0]]
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; CHECK: %r1 = COPY [[R1]]
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; CHECK: BX_RET 14, _, implicit %r0, implicit %r1
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entry:
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notail call arm_aapcscc void @fp_arrays_aapcs_target([3 x double] %arr)
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ret void
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%r = notail call arm_aapcscc [2 x float] @fp_arrays_aapcs_target([3 x double] %arr)
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ret [2 x float] %r
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}
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declare arm_aapcs_vfpcc void @fp_arrays_aapcs_vfp_target([3 x double], [3 x float], [4 x double])
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declare arm_aapcs_vfpcc [4 x float] @fp_arrays_aapcs_vfp_target([3 x double], [3 x float], [4 x double])
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define arm_aapcs_vfpcc void @test_fp_arrays_aapcs_vfp([3 x double] %x, [3 x float] %y, [4 x double] %z) {
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define arm_aapcs_vfpcc [4 x float] @test_fp_arrays_aapcs_vfp([3 x double] %x, [3 x float] %y, [4 x double] %z) {
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; CHECK-LABEL: name: test_fp_arrays_aapcs_vfp
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; CHECK: fixedStack:
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; CHECK-DAG: id: [[Z0_ID:[0-9]+]], offset: 0, size: 8
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@ -848,17 +883,35 @@ define arm_aapcs_vfpcc void @test_fp_arrays_aapcs_vfp([3 x double] %x, [3 x floa
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; CHECK: [[Z3_OFFSET:%[0-9]+]](s32) = G_CONSTANT i32 24
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; CHECK: [[Z3_ADDR:%[0-9]+]](p0) = G_GEP [[SP]], [[Z3_OFFSET]](s32)
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; CHECK: G_STORE [[Z3]](s64), [[Z3_ADDR]](p0){{.*}}store 8
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; CHECK: BLX @fp_arrays_aapcs_vfp_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %d0, implicit %d1, implicit %d2, implicit %s6, implicit %s7, implicit %s8
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; CHECK: BLX @fp_arrays_aapcs_vfp_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %d0, implicit %d1, implicit %d2, implicit %s6, implicit %s7, implicit %s8, implicit-def %s0, implicit-def %s1, implicit-def %s2, implicit-def %s3
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; CHECK: [[R0:%[0-9]+]](s32) = COPY %s0
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; CHECK: [[R1:%[0-9]+]](s32) = COPY %s1
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; CHECK: [[R2:%[0-9]+]](s32) = COPY %s2
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; CHECK: [[R3:%[0-9]+]](s32) = COPY %s3
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; CHECK: [[R_MERGED_0:%[0-9]+]](s128) = IMPLICIT_DEF
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; CHECK: [[R_MERGED_1:%[0-9]+]](s128) = G_INSERT [[R_MERGED_0]], [[R0]](s32), 0
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; CHECK: [[R_MERGED_2:%[0-9]+]](s128) = G_INSERT [[R_MERGED_1]], [[R1]](s32), 32
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; CHECK: [[R_MERGED_3:%[0-9]+]](s128) = G_INSERT [[R_MERGED_2]], [[R2]](s32), 64
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; CHECK: [[R_MERGED_4:%[0-9]+]](s128) = G_INSERT [[R_MERGED_3]], [[R3]](s32), 96
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; CHECK: [[R_MERGED:%[0-9]+]](s128) = COPY [[R_MERGED_4]]
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; CHECK: ADJCALLSTACKUP 32, 0, 14, _, implicit-def %sp, implicit %sp
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; CHECK: BX_RET 14, _
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; CHECK: [[R0:%[0-9]+]](s32) = G_EXTRACT [[R_MERGED]](s128), 0
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; CHECK: [[R1:%[0-9]+]](s32) = G_EXTRACT [[R_MERGED]](s128), 32
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; CHECK: [[R2:%[0-9]+]](s32) = G_EXTRACT [[R_MERGED]](s128), 64
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; CHECK: [[R3:%[0-9]+]](s32) = G_EXTRACT [[R_MERGED]](s128), 96
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; CHECK: %s0 = COPY [[R0]]
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; CHECK: %s1 = COPY [[R1]]
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; CHECK: %s2 = COPY [[R2]]
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; CHECK: %s3 = COPY [[R3]]
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; CHECK: BX_RET 14, _, implicit %s0, implicit %s1, implicit %s2, implicit %s3
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entry:
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notail call arm_aapcs_vfpcc void @fp_arrays_aapcs_vfp_target([3 x double] %x, [3 x float] %y, [4 x double] %z)
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ret void
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%r = notail call arm_aapcs_vfpcc [4 x float] @fp_arrays_aapcs_vfp_target([3 x double] %x, [3 x float] %y, [4 x double] %z)
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ret [4 x float] %r
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}
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declare arm_aapcscc void @tough_arrays_target([6 x [4 x i32]] %arr)
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declare arm_aapcscc [2 x i32*] @tough_arrays_target([6 x [4 x i32]] %arr)
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define arm_aapcscc void @test_tough_arrays([6 x [4 x i32]] %arr) {
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define arm_aapcscc [2 x i32*] @test_tough_arrays([6 x [4 x i32]] %arr) {
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; CHECK-LABEL: name: test_tough_arrays
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; CHECK: fixedStack:
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; The parameters live in separate stack locations, one for each element that
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@ -903,12 +956,22 @@ define arm_aapcscc void @test_tough_arrays([6 x [4 x i32]] %arr) {
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; CHECK: [[OFF_LAST_ELEMENT:%[0-9]+]](s32) = G_CONSTANT i32 76
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; CHECK: [[LAST_STACK_ARG_ADDR:%[0-9]+]](p0) = G_GEP [[SP]], [[OFF_LAST_ELEMENT]](s32)
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; CHECK: G_STORE [[LAST_STACK_ELEMENT]](s32), [[LAST_STACK_ARG_ADDR]]{{.*}}store 4
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; CHECK: BLX @tough_arrays_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit %r3
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; CHECK: BLX @tough_arrays_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1
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; CHECK: [[R0:%[0-9]+]](s32) = COPY %r0
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; CHECK: [[R1:%[0-9]+]](s32) = COPY %r1
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; CHECK: [[RES_ARR0:%[0-9]+]](s64) = IMPLICIT_DEF
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; CHECK: [[RES_ARR1:%[0-9]+]](s64) = G_INSERT [[RES_ARR0]], [[R0]](s32), 0
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; CHECK: [[RES_ARR2:%[0-9]+]](s64) = G_INSERT [[RES_ARR1]], [[R1]](s32), 32
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; CHECK: [[RES_ARR:%[0-9]+]](s64) = COPY [[RES_ARR2]]
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; CHECK: ADJCALLSTACKUP 80, 0, 14, _, implicit-def %sp, implicit %sp
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; CHECK: BX_RET 14, _
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; CHECK: [[R0:%[0-9]+]](s32) = G_EXTRACT [[RES_ARR]](s64), 0
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; CHECK: [[R1:%[0-9]+]](s32) = G_EXTRACT [[RES_ARR]](s64), 32
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; CHECK: %r0 = COPY [[R0]]
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; CHECK: %r1 = COPY [[R1]]
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; CHECK: BX_RET 14, _, implicit %r0, implicit %r1
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entry:
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notail call arm_aapcscc void @tough_arrays_target([6 x [4 x i32]] %arr)
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ret void
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%r = notail call arm_aapcscc [2 x i32*] @tough_arrays_target([6 x [4 x i32]] %arr)
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ret [2 x i32*] %r
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}
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define i32 @test_shufflevector_s32_v2s32(i32 %arg) {
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