forked from OSchip/llvm-project
This patch implements the thread local storage. Implemented are General
Dynamic, Initial Exec and Local Exec TLS models. Patch by Sasa Stankovic llvm-svn: 132322
This commit is contained in:
Bruno Cardoso Lopes
parent
4503e20ae6
commit
bf3c1251e0
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@ -318,6 +318,10 @@ void MipsAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
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case MipsII::MO_GOT: O << "%got("; break;
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case MipsII::MO_ABS_HI: O << "%hi("; break;
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case MipsII::MO_ABS_LO: O << "%lo("; break;
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case MipsII::MO_TLSGD: O << "%tlsgd("; break;
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case MipsII::MO_GOTTPREL: O << "%gottprel("; break;
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case MipsII::MO_TPREL_HI: O << "%tprel_hi("; break;
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case MipsII::MO_TPREL_LO: O << "%tprel_lo("; break;
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}
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switch (MO.getType()) {
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@ -128,6 +128,11 @@ SelectAddr(SDValue Addr, SDValue &Offset, SDValue &Base) {
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if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
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Addr.getOpcode() == ISD::TargetGlobalAddress))
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return false;
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else if (Addr.getOpcode() == ISD::TargetGlobalTLSAddress) {
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Base = CurDAG->getRegister(Mips::GP, MVT::i32);
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Offset = Addr;
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return true;
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}
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}
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// Operand is a result from an ADD.
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@ -441,6 +446,18 @@ SDNode* MipsDAGToDAGISel::Select(SDNode *Node) {
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return ResNode;
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// Other cases are autogenerated.
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break;
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case MipsISD::ThreadPointer: {
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unsigned SrcReg = Mips::HWR29;
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unsigned DestReg = Mips::V1;
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SDNode *Rdhwr = CurDAG->getMachineNode(Mips::RDHWR, Node->getDebugLoc(),
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Node->getValueType(0), CurDAG->getRegister(SrcReg, MVT::i32));
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SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, DestReg,
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SDValue(Rdhwr, 0));
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SDValue ResNode = CurDAG->getCopyFromReg(Chain, dl, DestReg, MVT::i32);
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ReplaceUses(SDValue(Node, 0), ResNode);
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return ResNode.getNode();
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}
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}
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// Select the default instruction
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@ -41,6 +41,10 @@ const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
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case MipsISD::Hi: return "MipsISD::Hi";
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case MipsISD::Lo: return "MipsISD::Lo";
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case MipsISD::GPRel: return "MipsISD::GPRel";
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case MipsISD::TlsGd: return "MipsISD::TlsGd";
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case MipsISD::TprelHi: return "MipsISD::TprelHi";
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case MipsISD::TprelLo: return "MipsISD::TprelLo";
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case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer";
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case MipsISD::Ret: return "MipsISD::Ret";
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case MipsISD::FPBrcond: return "MipsISD::FPBrcond";
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case MipsISD::FPCmp: return "MipsISD::FPCmp";
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@ -822,8 +826,60 @@ SDValue MipsTargetLowering::LowerBlockAddress(SDValue Op,
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SDValue MipsTargetLowering::
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LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
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{
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llvm_unreachable("TLS not implemented for MIPS.");
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return SDValue(); // Not reached
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// If the relocation model is PIC, use the General Dynamic TLS Model,
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// otherwise use the Initial Exec or Local Exec TLS Model.
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// TODO: implement Local Dynamic TLS model
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GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
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DebugLoc dl = GA->getDebugLoc();
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const GlobalValue *GV = GA->getGlobal();
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EVT PtrVT = getPointerTy();
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if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
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// General Dynamic TLS Model
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SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32,
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0, MipsII::MO_TLSGD);
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SDValue Tlsgd = DAG.getNode(MipsISD::TlsGd, dl, MVT::i32, TGA);
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SDValue GP = DAG.getRegister(Mips::GP, MVT::i32);
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SDValue Argument = DAG.getNode(ISD::ADD, dl, MVT::i32, GP, Tlsgd);
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ArgListTy Args;
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ArgListEntry Entry;
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Entry.Node = Argument;
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Entry.Ty = (const Type *) Type::getInt32Ty(*DAG.getContext());
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Args.push_back(Entry);
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std::pair<SDValue, SDValue> CallResult =
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LowerCallTo(DAG.getEntryNode(),
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(const Type *) Type::getInt32Ty(*DAG.getContext()),
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false, false, false, false,
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0, CallingConv::C, false, true,
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DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl);
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return CallResult.first;
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} else {
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SDValue Offset;
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if (GV->isDeclaration()) {
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// Initial Exec TLS Model
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SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
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MipsII::MO_GOTTPREL);
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Offset = DAG.getLoad(MVT::i32, dl,
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DAG.getEntryNode(), TGA, MachinePointerInfo(),
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false, false, 0);
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} else {
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// Local Exec TLS Model
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SDVTList VTs = DAG.getVTList(MVT::i32);
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SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
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MipsII::MO_TPREL_HI);
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SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
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MipsII::MO_TPREL_LO);
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SDValue Hi = DAG.getNode(MipsISD::TprelHi, dl, VTs, &TGAHi, 1);
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SDValue Lo = DAG.getNode(MipsISD::TprelLo, dl, MVT::i32, TGALo);
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Offset = DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, Lo);
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}
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SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, dl, PtrVT);
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return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
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}
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}
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SDValue MipsTargetLowering::
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@ -40,6 +40,16 @@ namespace llvm {
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// Handle gp_rel (small data/bss sections) relocation.
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GPRel,
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// General Dynamic TLS
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TlsGd,
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// Local Exec TLS
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TprelHi,
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TprelLo,
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// Thread Pointer
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ThreadPointer,
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// Floating Point Branch Conditional
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FPBrcond,
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@ -146,7 +146,21 @@ namespace MipsII {
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/// MO_ABS_HI/LO - Represents the hi or low part of an absolute symbol
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/// address.
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MO_ABS_HI,
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MO_ABS_LO
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MO_ABS_LO,
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/// MO_TLSGD - Represents the offset into the global offset table at which
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// the module ID and TSL block offset reside during execution (General
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// Dynamic TLS).
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MO_TLSGD,
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/// MO_GOTTPREL - Represents the offset from the thread pointer (Initial
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// Exec TLS).
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MO_GOTTPREL,
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/// MO_TPREL_HI/LO - Represents the hi and low part of the offset from
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// the thread pointer (Local Exec TLS).
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MO_TPREL_HI,
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MO_TPREL_LO
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};
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}
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@ -37,6 +37,8 @@ def SDT_MipsDivRem : SDTypeProfile<0, 2,
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[SDTCisVT<0, i32>,
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SDTCisSameAs<0, 1>]>;
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def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
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// Call
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def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
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[SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
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@ -49,6 +51,16 @@ def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
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def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
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def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
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// TlsGd node is used to handle General Dynamic TLS
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def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
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// TprelHi and TprelLo nodes are used to handle Local Exec TLS
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def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
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def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
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// Thread pointer
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def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
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// Return
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def MipsRet : SDNode<"MipsISD::Ret", SDT_MipsRet, [SDNPHasChain,
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SDNPOptInGlue]>;
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@ -353,6 +365,13 @@ class CondMov<bits<6> func, string instr_asm, PatLeaf MovCode>:
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CPURegs:$cond), !strconcat(instr_asm, "\t$dst, $T, $cond"),
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[], NoItinerary>;
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// Read Hardware
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class ReadHardware: FR<0x1f, 0x3b, (outs CPURegs:$dst), (ins HWRegs:$src),
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"rdhwr\t$dst, $src", [], IIAlu> {
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let rs = 0;
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let shamt = 0;
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}
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//===----------------------------------------------------------------------===//
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// Pseudo instructions
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//===----------------------------------------------------------------------===//
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@ -540,6 +559,8 @@ def MSUBU : MArithR<5, "msubu", MipsMSubu>;
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// it is a real instruction.
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def MUL : ArithR<0x1c, 0x02, "mul", mul, IIImul, 1>, Requires<[IsMips32]>;
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def RDHWR : ReadHardware;
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//===----------------------------------------------------------------------===//
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// Arbitrary patterns that map to one or more instructions
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//===----------------------------------------------------------------------===//
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@ -592,6 +613,15 @@ def : Pat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)),
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def : Pat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)),
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(ADDiu CPURegs:$gp, tconstpool:$in)>;
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// tlsgd
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def : Pat<(add CPURegs:$gp, (MipsTlsGd tglobaltlsaddr:$in)),
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(ADDiu CPURegs:$gp, tglobaltlsaddr:$in)>;
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// tprel hi/lo
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def : Pat<(MipsTprelHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
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def : Pat<(add CPURegs:$hi, (MipsTprelLo tglobaltlsaddr:$lo)),
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(ADDiu CPURegs:$hi, tglobaltlsaddr:$lo)>;
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// wrapper_pic
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class WrapperPICPat<SDNode node>:
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Pat<(MipsWrapperPIC node:$in),
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@ -44,6 +44,11 @@ class AFPR<bits<5> num, string n, list<Register> subregs>
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let SubRegIndices = [sub_fpeven, sub_fpodd];
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}
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// Mips Hardware Registers
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class HWR<bits<5> num, string n> : MipsReg<n> {
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let Num = num;
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}
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//===----------------------------------------------------------------------===//
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// Registers
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//===----------------------------------------------------------------------===//
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@ -143,6 +148,9 @@ let Namespace = "Mips" in {
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// Status flags register
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def FCR31 : Register<"31">;
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// Hardware register $29
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def HWR29 : Register<"29">;
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}
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//===----------------------------------------------------------------------===//
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@ -262,3 +270,5 @@ def CCR : RegisterClass<"Mips", [i32], 32, [FCR31]>;
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// Hi/Lo Registers
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def HILO : RegisterClass<"Mips", [i32], 32, [HI, LO]>;
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// Hardware registers
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def HWRegs : RegisterClass<"Mips", [i32], 32, [HWR29]>;
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@ -0,0 +1,46 @@
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; RUN: llc -march=mipsel -mcpu=mips2 < %s | FileCheck %s -check-prefix=PIC
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; RUN: llc -march=mipsel -mcpu=mips2 -relocation-model=static < %s \
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; RUN: | FileCheck %s -check-prefix=STATIC
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@t1 = thread_local global i32 0, align 4
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define i32 @f1() nounwind {
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entry:
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%tmp = load i32* @t1, align 4
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ret i32 %tmp
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; CHECK: f1:
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; PIC: lw $25, %call16(__tls_get_addr)($gp)
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; PIC: addiu $4, $gp, %tlsgd(t1)
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; PIC: jalr $25
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; PIC: lw $2, 0($2)
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; STATIC: rdhwr $3, $29
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; STATIC: lui $[[R0:[0-9]+]], %tprel_hi(t1)
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; STATIC: addiu $[[R1:[0-9]+]], $[[R0]], %tprel_lo(t1)
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; STATIC: addu $[[R2:[0-9]+]], $3, $[[R1]]
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; STATIC: lw $2, 0($[[R2]])
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}
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@t2 = external thread_local global i32
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define i32 @f2() nounwind {
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entry:
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%tmp = load i32* @t2, align 4
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ret i32 %tmp
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; CHECK: f2:
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; PIC: lw $25, %call16(__tls_get_addr)($gp)
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; PIC: addiu $4, $gp, %tlsgd(t2)
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; PIC: jalr $25
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; PIC: lw $2, 0($2)
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; STATIC: rdhwr $3, $29
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; STATIC: lw $[[R0:[0-9]+]], %gottprel(t2)($gp)
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; STATIC: addu $[[R1:[0-9]+]], $3, $[[R0]]
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; STATIC: lw $2, 0($[[R1]])
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}
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