forked from OSchip/llvm-project
So that we can include target lowering in the subtarget, remove include
circular dependency with the subtarget by inlining accessor methods and outlining a routine. llvm-svn: 212234
This commit is contained in:
Eric Christopher
parent
5899e19def
commit
bf33a3cf70
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@ -251,7 +251,7 @@ MipsTargetLowering::MipsTargetLowering(MipsTargetMachine &TM)
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setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
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setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
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if (isGP64bit()) {
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if (Subtarget->isGP64bit()) {
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setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
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setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
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setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
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@ -263,14 +263,14 @@ MipsTargetLowering::MipsTargetLowering(MipsTargetMachine &TM)
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setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
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}
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if (!isGP64bit()) {
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if (!Subtarget->isGP64bit()) {
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setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
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setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
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setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
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}
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setOperationAction(ISD::ADD, MVT::i32, Custom);
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if (isGP64bit())
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if (Subtarget->isGP64bit())
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setOperationAction(ISD::ADD, MVT::i64, Custom);
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setOperationAction(ISD::SDIV, MVT::i32, Expand);
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@ -369,7 +369,7 @@ MipsTargetLowering::MipsTargetLowering(MipsTargetMachine &TM)
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if (!Subtarget->hasMips64r2())
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setOperationAction(ISD::BSWAP, MVT::i64, Expand);
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if (isGP64bit()) {
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if (Subtarget->isGP64bit()) {
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setLoadExtAction(ISD::SEXTLOAD, MVT::i32, Custom);
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setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Custom);
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setLoadExtAction(ISD::EXTLOAD, MVT::i32, Custom);
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@ -385,12 +385,13 @@ MipsTargetLowering::MipsTargetLowering(MipsTargetMachine &TM)
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setTargetDAGCombine(ISD::OR);
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setTargetDAGCombine(ISD::ADD);
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setMinFunctionAlignment(isGP64bit() ? 3 : 2);
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setMinFunctionAlignment(Subtarget->isGP64bit() ? 3 : 2);
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setStackPointerRegisterToSaveRestore(isN64() ? Mips::SP_64 : Mips::SP);
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setStackPointerRegisterToSaveRestore(Subtarget->isABI_N64() ? Mips::SP_64
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: Mips::SP);
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setExceptionPointerRegister(isN64() ? Mips::A0_64 : Mips::A0);
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setExceptionSelectorRegister(isN64() ? Mips::A1_64 : Mips::A1);
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setExceptionPointerRegister(Subtarget->isABI_N64() ? Mips::A0_64 : Mips::A0);
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setExceptionSelectorRegister(Subtarget->isABI_N64() ? Mips::A1_64 : Mips::A1);
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MaxStoresPerMemcpy = 16;
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@ -1484,7 +1485,8 @@ SDValue MipsTargetLowering::lowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
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0);
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Chain = Addr.getValue(1);
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if ((getTargetMachine().getRelocationModel() == Reloc::PIC_) || isN64()) {
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if ((getTargetMachine().getRelocationModel() == Reloc::PIC_) ||
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Subtarget->isABI_N64()) {
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// For PIC, the sequence is:
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// BRIND(load(Jumptable + index) + RelocBase)
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// RelocBase can be JumpTable, GOT or some sort of global base.
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@ -1568,7 +1570,8 @@ SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op,
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GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op);
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const GlobalValue *GV = N->getGlobal();
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if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !isN64()) {
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if (getTargetMachine().getRelocationModel() != Reloc::PIC_ &&
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!Subtarget->isABI_N64()) {
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const MipsTargetObjectFile &TLOF =
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(const MipsTargetObjectFile&)getObjFileLowering();
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@ -1587,15 +1590,18 @@ SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op,
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}
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if (GV->hasInternalLinkage() || (GV->hasLocalLinkage() && !isa<Function>(GV)))
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return getAddrLocal(N, Ty, DAG, isN32() || isN64());
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return getAddrLocal(N, Ty, DAG,
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Subtarget->isABI_N32() || Subtarget->isABI_N64());
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if (LargeGOT)
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return getAddrGlobalLargeGOT(N, Ty, DAG, MipsII::MO_GOT_HI16,
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MipsII::MO_GOT_LO16, DAG.getEntryNode(),
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MachinePointerInfo::getGOT());
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return getAddrGlobal(N, Ty, DAG, (isN32() || isN64()) ? MipsII::MO_GOT_DISP
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: MipsII::MO_GOT16,
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return getAddrGlobal(N, Ty, DAG,
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(Subtarget->isABI_N32() || Subtarget->isABI_N64())
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? MipsII::MO_GOT_DISP
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: MipsII::MO_GOT16,
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DAG.getEntryNode(), MachinePointerInfo::getGOT());
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}
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@ -1604,10 +1610,12 @@ SDValue MipsTargetLowering::lowerBlockAddress(SDValue Op,
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BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op);
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EVT Ty = Op.getValueType();
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if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !isN64())
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if (getTargetMachine().getRelocationModel() != Reloc::PIC_ &&
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!Subtarget->isABI_N64())
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return getAddrNonPIC(N, Ty, DAG);
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return getAddrLocal(N, Ty, DAG, isN32() || isN64());
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return getAddrLocal(N, Ty, DAG,
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Subtarget->isABI_N32() || Subtarget->isABI_N64());
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}
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SDValue MipsTargetLowering::
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@ -1695,10 +1703,12 @@ lowerJumpTable(SDValue Op, SelectionDAG &DAG) const
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JumpTableSDNode *N = cast<JumpTableSDNode>(Op);
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EVT Ty = Op.getValueType();
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if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !isN64())
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if (getTargetMachine().getRelocationModel() != Reloc::PIC_ &&
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!Subtarget->isABI_N64())
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return getAddrNonPIC(N, Ty, DAG);
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return getAddrLocal(N, Ty, DAG, isN32() || isN64());
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return getAddrLocal(N, Ty, DAG,
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Subtarget->isABI_N32() || Subtarget->isABI_N64());
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}
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SDValue MipsTargetLowering::
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@ -1716,10 +1726,12 @@ lowerConstantPool(SDValue Op, SelectionDAG &DAG) const
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ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
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EVT Ty = Op.getValueType();
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if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !isN64())
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if (getTargetMachine().getRelocationModel() != Reloc::PIC_ &&
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!Subtarget->isABI_N64())
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return getAddrNonPIC(N, Ty, DAG);
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return getAddrLocal(N, Ty, DAG, isN32() || isN64());
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return getAddrLocal(N, Ty, DAG,
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Subtarget->isABI_N32() || Subtarget->isABI_N64());
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}
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SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const {
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@ -1850,8 +1862,9 @@ lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
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MFI->setFrameAddressIsTaken(true);
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EVT VT = Op.getValueType();
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SDLoc DL(Op);
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SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), DL,
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isN64() ? Mips::FP_64 : Mips::FP, VT);
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SDValue FrameAddr =
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DAG.getCopyFromReg(DAG.getEntryNode(), DL,
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Subtarget->isABI_N64() ? Mips::FP_64 : Mips::FP, VT);
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return FrameAddr;
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}
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@ -1867,7 +1880,7 @@ SDValue MipsTargetLowering::lowerRETURNADDR(SDValue Op,
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MachineFunction &MF = DAG.getMachineFunction();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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MVT VT = Op.getSimpleValueType();
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unsigned RA = isN64() ? Mips::RA_64 : Mips::RA;
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unsigned RA = Subtarget->isABI_N64() ? Mips::RA_64 : Mips::RA;
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MFI->setReturnAddressIsTaken(true);
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// Return RA, which contains the return address. Mark it an implicit live-in.
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@ -1889,12 +1902,12 @@ SDValue MipsTargetLowering::lowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
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SDValue Offset = Op.getOperand(1);
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SDValue Handler = Op.getOperand(2);
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SDLoc DL(Op);
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EVT Ty = isN64() ? MVT::i64 : MVT::i32;
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EVT Ty = Subtarget->isABI_N64() ? MVT::i64 : MVT::i32;
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// Store stack offset in V1, store jump target in V0. Glue CopyToReg and
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// EH_RETURN nodes, so that instructions are emitted back-to-back.
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unsigned OffsetReg = isN64() ? Mips::V1_64 : Mips::V1;
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unsigned AddrReg = isN64() ? Mips::V0_64 : Mips::V0;
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unsigned OffsetReg = Subtarget->isABI_N64() ? Mips::V1_64 : Mips::V1;
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unsigned AddrReg = Subtarget->isABI_N64() ? Mips::V0_64 : Mips::V0;
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Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue());
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Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1));
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return DAG.getNode(MipsISD::EH_RETURN, DL, MVT::Other, Chain,
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@ -2322,8 +2335,8 @@ getOpndList(SmallVectorImpl<SDValue> &Ops,
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// in PIC mode) allow symbols to be resolved via lazy binding.
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// The lazy binding stub requires GP to point to the GOT.
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if (IsPICCall && !InternalLinkage) {
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unsigned GPReg = isN64() ? Mips::GP_64 : Mips::GP;
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EVT Ty = isN64() ? MVT::i64 : MVT::i32;
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unsigned GPReg = Subtarget->isABI_N64() ? Mips::GP_64 : Mips::GP;
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EVT Ty = Subtarget->isABI_N64() ? MVT::i64 : MVT::i32;
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RegsToPass.push_back(std::make_pair(GPReg, getGlobalReg(CLI.DAG, Ty)));
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}
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@ -2392,8 +2405,8 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
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getTargetMachine(), ArgLocs, *DAG.getContext());
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MipsCC::SpecialCallingConvType SpecialCallingConv =
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getSpecialCallingConv(Callee);
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MipsCC MipsCCInfo(CallConv, isO32(), Subtarget->isFP64bit(), CCInfo,
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SpecialCallingConv);
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MipsCC MipsCCInfo(CallConv, Subtarget->isABI_O32(), Subtarget->isFP64bit(),
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CCInfo, SpecialCallingConv);
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MipsCCInfo.analyzeCallOperands(Outs, IsVarArg,
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Subtarget->mipsSEUsesSoftFloat(),
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@ -2426,7 +2439,8 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
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Chain = DAG.getCALLSEQ_START(Chain, NextStackOffsetVal, DL);
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SDValue StackPtr = DAG.getCopyFromReg(
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Chain, DL, isN64() ? Mips::SP_64 : Mips::SP, getPointerTy());
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Chain, DL, Subtarget->isABI_N64() ? Mips::SP_64 : Mips::SP,
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getPointerTy());
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// With EABI is it possible to have 16 args on registers.
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std::deque< std::pair<unsigned, SDValue> > RegsToPass;
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@ -2512,8 +2526,9 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
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// If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
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// direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
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// node so that legalize doesn't hack it.
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bool IsPICCall = (isN64() || IsPIC); // true if calls are translated to
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// jalr $25
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bool IsPICCall =
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(Subtarget->isABI_N64() || IsPIC); // true if calls are translated to
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// jalr $25
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bool GlobalOrExternal = false, InternalLinkage = false;
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SDValue CalleeLo;
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EVT Ty = Callee.getValueType();
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@ -2524,7 +2539,8 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
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InternalLinkage = Val->hasInternalLinkage();
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if (InternalLinkage)
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Callee = getAddrLocal(G, Ty, DAG, isN32() || isN64());
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Callee = getAddrLocal(G, Ty, DAG,
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Subtarget->isABI_N32() || Subtarget->isABI_N64());
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else if (LargeGOT)
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Callee = getAddrGlobalLargeGOT(G, Ty, DAG, MipsII::MO_CALL_HI16,
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MipsII::MO_CALL_LO16, Chain,
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@ -2540,7 +2556,7 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
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else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
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const char *Sym = S->getSymbol();
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if (!isN64() && !IsPIC) // !N64 && static
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if (!Subtarget->isABI_N64() && !IsPIC) // !N64 && static
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Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(),
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MipsII::MO_NO_FLAG);
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else if (LargeGOT)
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@ -2591,7 +2607,8 @@ MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
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SmallVector<CCValAssign, 16> RVLocs;
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CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
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getTargetMachine(), RVLocs, *DAG.getContext());
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MipsCC MipsCCInfo(CallConv, isO32(), Subtarget->isFP64bit(), CCInfo);
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MipsCC MipsCCInfo(CallConv, Subtarget->isABI_O32(), Subtarget->isFP64bit(),
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CCInfo);
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MipsCCInfo.analyzeCallResult(Ins, Subtarget->mipsSEUsesSoftFloat(),
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CallNode, RetTy);
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@ -2638,7 +2655,8 @@ MipsTargetLowering::LowerFormalArguments(SDValue Chain,
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SmallVector<CCValAssign, 16> ArgLocs;
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CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
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getTargetMachine(), ArgLocs, *DAG.getContext());
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MipsCC MipsCCInfo(CallConv, isO32(), Subtarget->isFP64bit(), CCInfo);
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MipsCC MipsCCInfo(CallConv, Subtarget->isABI_O32(), Subtarget->isFP64bit(),
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CCInfo);
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Function::const_arg_iterator FuncArg =
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DAG.getMachineFunction().getFunction()->arg_begin();
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bool UseSoftFloat = Subtarget->mipsSEUsesSoftFloat();
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@ -2700,7 +2718,8 @@ MipsTargetLowering::LowerFormalArguments(SDValue Chain,
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(RegVT == MVT::i64 && ValVT == MVT::f64) ||
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(RegVT == MVT::f64 && ValVT == MVT::i64))
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ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue);
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else if (isO32() && RegVT == MVT::i32 && ValVT == MVT::f64) {
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else if (Subtarget->isABI_O32() && RegVT == MVT::i32 &&
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ValVT == MVT::f64) {
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unsigned Reg2 = addLiveIn(DAG.getMachineFunction(),
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getNextIntArgReg(ArgReg), RC);
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SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT);
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@ -2738,7 +2757,7 @@ MipsTargetLowering::LowerFormalArguments(SDValue Chain,
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unsigned Reg = MipsFI->getSRetReturnReg();
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if (!Reg) {
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Reg = MF.getRegInfo().createVirtualRegister(
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getRegClassFor(isN64() ? MVT::i64 : MVT::i32));
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getRegClassFor(Subtarget->isABI_N64() ? MVT::i64 : MVT::i32));
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MipsFI->setSRetReturnReg(Reg);
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}
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SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[i]);
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@ -2789,7 +2808,8 @@ MipsTargetLowering::LowerReturn(SDValue Chain,
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// CCState - Info about the registers and stack slot.
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CCState CCInfo(CallConv, IsVarArg, MF, getTargetMachine(), RVLocs,
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*DAG.getContext());
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MipsCC MipsCCInfo(CallConv, isO32(), Subtarget->isFP64bit(), CCInfo);
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MipsCC MipsCCInfo(CallConv, Subtarget->isABI_O32(), Subtarget->isFP64bit(),
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CCInfo);
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// Analyze return values.
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MipsCCInfo.analyzeReturn(Outs, Subtarget->mipsSEUsesSoftFloat(),
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@ -2825,7 +2845,7 @@ MipsTargetLowering::LowerReturn(SDValue Chain,
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if (!Reg)
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llvm_unreachable("sret virtual register not created in the entry block");
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SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy());
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unsigned V0 = isN64() ? Mips::V0_64 : Mips::V0;
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unsigned V0 = Subtarget->isABI_N64() ? Mips::V0_64 : Mips::V0;
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Chain = DAG.getCopyToReg(Chain, DL, V0, Val, Flag);
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Flag = Chain.getValue(1);
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@ -3046,9 +3066,9 @@ getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const
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return std::make_pair(0U, &Mips::CPU16RegsRegClass);
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return std::make_pair(0U, &Mips::GPR32RegClass);
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}
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if (VT == MVT::i64 && !isGP64bit())
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if (VT == MVT::i64 && !Subtarget->isGP64bit())
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return std::make_pair(0U, &Mips::GPR32RegClass);
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if (VT == MVT::i64 && isGP64bit())
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if (VT == MVT::i64 && Subtarget->isGP64bit())
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return std::make_pair(0U, &Mips::GPR64RegClass);
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// This will generate an error message
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return std::make_pair(0U, nullptr);
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@ -3235,7 +3255,7 @@ bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
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}
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unsigned MipsTargetLowering::getJumpTableEncoding() const {
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if (isN64())
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if (Subtarget->isABI_N64())
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return MachineJumpTableInfo::EK_GPRel64BlockAddress;
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return TargetLowering::getJumpTableEncoding();
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@ -17,7 +17,6 @@
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#include "MCTargetDesc/MipsBaseInfo.h"
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#include "Mips.h"
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#include "MipsSubtarget.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/IR/Function.h"
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@ -210,6 +209,7 @@ namespace llvm {
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// TargetLowering Implementation
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//===--------------------------------------------------------------------===//
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class MipsFunctionInfo;
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class MipsSubtarget;
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class MipsTargetLowering : public TargetLowering {
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bool isMicroMips;
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@ -438,12 +438,6 @@ namespace llvm {
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// Subtarget Info
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const MipsSubtarget *Subtarget;
|
||||
|
||||
bool hasMips64() const { return Subtarget->hasMips64(); }
|
||||
bool isGP64bit() const { return Subtarget->isGP64bit(); }
|
||||
bool isO32() const { return Subtarget->isABI_O32(); }
|
||||
bool isN32() const { return Subtarget->isABI_N32(); }
|
||||
bool isN64() const { return Subtarget->isABI_N64(); }
|
||||
|
||||
private:
|
||||
// Create a TargetGlobalAddress node.
|
||||
SDValue getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
|
||||
|
|
|
|||
|
|
@ -39,7 +39,7 @@ MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM)
|
|||
// Set up the register classes
|
||||
addRegisterClass(MVT::i32, &Mips::GPR32RegClass);
|
||||
|
||||
if (isGP64bit())
|
||||
if (Subtarget->isGP64bit())
|
||||
addRegisterClass(MVT::i64, &Mips::GPR64RegClass);
|
||||
|
||||
if (Subtarget->hasDSP() || Subtarget->hasMSA()) {
|
||||
|
|
@ -120,10 +120,10 @@ MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM)
|
|||
|
||||
if (Subtarget->hasCnMips())
|
||||
setOperationAction(ISD::MUL, MVT::i64, Legal);
|
||||
else if (isGP64bit())
|
||||
else if (Subtarget->isGP64bit())
|
||||
setOperationAction(ISD::MUL, MVT::i64, Custom);
|
||||
|
||||
if (isGP64bit()) {
|
||||
if (Subtarget->isGP64bit()) {
|
||||
setOperationAction(ISD::MULHS, MVT::i64, Custom);
|
||||
setOperationAction(ISD::MULHU, MVT::i64, Custom);
|
||||
}
|
||||
|
|
@ -230,6 +230,14 @@ llvm::createMipsSETargetLowering(MipsTargetMachine &TM) {
|
|||
return new MipsSETargetLowering(TM);
|
||||
}
|
||||
|
||||
const TargetRegisterClass *
|
||||
MipsSETargetLowering::getRepRegClassFor(MVT VT) const {
|
||||
if (VT == MVT::Untyped)
|
||||
return Subtarget->hasDSP() ? &Mips::ACC64DSPRegClass : &Mips::ACC64RegClass;
|
||||
|
||||
return TargetLowering::getRepRegClassFor(VT);
|
||||
}
|
||||
|
||||
// Enable MSA support for the given integer type and Register class.
|
||||
void MipsSETargetLowering::
|
||||
addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
|
||||
|
|
@ -1724,7 +1732,7 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
|
|||
case Intrinsic::mips_copy_s_w:
|
||||
return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_SEXT_ELT);
|
||||
case Intrinsic::mips_copy_s_d:
|
||||
if (hasMips64())
|
||||
if (Subtarget->hasMips64())
|
||||
// Lower directly into VEXTRACT_SEXT_ELT since i64 is legal on Mips64.
|
||||
return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_SEXT_ELT);
|
||||
else {
|
||||
|
|
@ -1739,7 +1747,7 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
|
|||
case Intrinsic::mips_copy_u_w:
|
||||
return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_ZEXT_ELT);
|
||||
case Intrinsic::mips_copy_u_d:
|
||||
if (hasMips64())
|
||||
if (Subtarget->hasMips64())
|
||||
// Lower directly into VEXTRACT_ZEXT_ELT since i64 is legal on Mips64.
|
||||
return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_ZEXT_ELT);
|
||||
else {
|
||||
|
|
@ -3016,8 +3024,8 @@ MipsSETargetLowering::emitINSERT_DF_VIDX(MachineInstr *MI,
|
|||
unsigned SrcValReg = MI->getOperand(3).getReg();
|
||||
|
||||
const TargetRegisterClass *VecRC = nullptr;
|
||||
const TargetRegisterClass *GPRRC = isGP64bit() ? &Mips::GPR64RegClass
|
||||
: &Mips::GPR32RegClass;
|
||||
const TargetRegisterClass *GPRRC =
|
||||
Subtarget->isGP64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
|
||||
unsigned EltLog2Size;
|
||||
unsigned InsertOp = 0;
|
||||
unsigned InsveOp = 0;
|
||||
|
|
|
|||
|
|
@ -46,13 +46,7 @@ namespace llvm {
|
|||
return false;
|
||||
}
|
||||
|
||||
const TargetRegisterClass *getRepRegClassFor(MVT VT) const override {
|
||||
if (VT == MVT::Untyped)
|
||||
return Subtarget->hasDSP() ? &Mips::ACC64DSPRegClass :
|
||||
&Mips::ACC64RegClass;
|
||||
|
||||
return TargetLowering::getRepRegClassFor(VT);
|
||||
}
|
||||
const TargetRegisterClass *getRepRegClassFor(MVT VT) const override;
|
||||
|
||||
private:
|
||||
bool isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
|
||||
|
|
|
|||
Loading…
Reference in New Issue