forked from OSchip/llvm-project
[LSR] Fix for pre-indexed generated constant offset
This patch changed the isLegalUse check to ensure that LSRInstance::GenerateConstantOffsetsImpl generates an offset that results in a legal addressing mode and formula. The check is changed to look similar to the assert check used for illegal formulas. Differential Revision: https://reviews.llvm.org/D100383 Change-Id: Iffb9e32d59df96b8f072c00f6c339108159a009a
This commit is contained in:
parent
17cec07184
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bf147c4653
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@ -3792,8 +3792,7 @@ void LSRInstance::GenerateConstantOffsetsImpl(
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Formula F = Base;
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F.BaseOffset = (uint64_t)Base.BaseOffset - Offset;
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if (isLegalUse(TTI, LU.MinOffset - Offset, LU.MaxOffset - Offset, LU.Kind,
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LU.AccessTy, F)) {
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if (isLegalUse(TTI, LU.MinOffset, LU.MaxOffset, LU.Kind, LU.AccessTy, F)) {
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// Add the offset to the base register.
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const SCEV *NewG = SE.getAddExpr(SE.getConstant(G->getType(), Offset), G);
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// If it cancelled out, drop the base register, otherwise update it.
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@ -2,7 +2,7 @@
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; RUN: llc -march=amdgcn -verify-machineinstrs -O0 < %s
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; GCN-LABEL: {{^}}test_loop:
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; GCN: s_and_b64 vcc, exec, -1
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; GCN: s_and_b64 s[0:1], exec, -1
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; GCN: [[LABEL:BB[0-9]+_[0-9]+]]: ; %for.body{{$}}
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; GCN: ds_read_b32
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; GCN: ds_write_b32
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@ -97,10 +97,10 @@ for.body:
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; GCN-LABEL: {{^}}loop_arg_0:
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; GCN: v_and_b32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}}
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; GCN: v_cmp_eq_u32{{[^,]*}}, 1,
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; GCN: s_add_i32 s2, s0, 0x80
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; GCN: [[LOOPBB:BB[0-9]+_[0-9]+]]
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; GCN: s_add_i32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80
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; GCN: s_add_i32 s{{[0-9]+}}, s{{[0-9]+}}, 4
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; GCN: _add_i32_e32 v0, vcc, 4, v0
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; GCN: s_cbranch_{{vccz|vccnz}} [[LOOPBB]]
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; GCN-NEXT: ; %bb.2
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@ -0,0 +1,53 @@
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; RUN: llc -mtriple=aarch64-none-eabi -lsr-preferred-addressing-mode=preindexed %s -o - | FileCheck %s
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; In LSR for constant offsets and steps, we can generate pre-inc
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; accesses by having the offset equal the step and generate a reuse
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; formula. However, there are cases where the step, results in an
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; illegal addressing mode.
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; In this test, we set the preferred addressing mode to be preindexed,
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; in order to test a scenario where the step results in an illegal
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; addressing mode and because of that it should not generate a reuse formula.
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; This test was created in order to reproduce a bug that was observed
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; when building a bootstrap build on an AArch64 machine, where the
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; preferred addresing mode is preindexed.
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%"Type" = type <{[166 x [338 x i8]]}>
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define void @test_lsr_pre_inc_offset_check(%"Type"* %p) {
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; CHECK-LABEL: test_lsr_pre_inc_offset_check:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: add x8, x0, #340 // =340
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; CHECK-NEXT: mov w9, #165
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; CHECK-NEXT: mov w10, #2
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; CHECK-NEXT: .LBB0_1: // %main
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; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: stur wzr, [x8, #-1]
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; CHECK-NEXT: strb w10, [x8]
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; CHECK-NEXT: subs x9, x9, #1 // =1
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; CHECK-NEXT: add x8, x8, #338 // =338
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; CHECK-NEXT: b.ne .LBB0_1
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; CHECK-NEXT: // %bb.2: // %exit
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; CHECK-NEXT: ret
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entry:
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br label %main
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exit:
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ret void
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if.then:
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%arrayidx.i = getelementptr inbounds %"Type", %"Type"* %p, i64 0, i32 0, i64 %indvars, i64 1
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%0 = bitcast i8* %arrayidx.i to i32*
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store i32 0, i32* %0, align 1
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br label %if.end
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if.end:
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%arrayidx.p = getelementptr inbounds %"Type", %"Type"* %p, i64 0, i32 0, i64 %indvars, i64 2
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store i8 2, i8* %arrayidx.p, align 1
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%indvars.iv.next = add nuw nsw i64 %indvars, 1
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%add.i = add nuw i8 %begin, 1
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%cmp.i.not = icmp eq i64 %indvars.iv.next, 166
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br i1 %cmp.i.not, label %exit, label %main
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main:
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%begin = phi i8 [ 1, %entry ], [ %add.i, %if.end ]
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%indvars = phi i64 [ 1, %entry ], [ %indvars.iv.next, %if.end ]
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br label %if.then
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}
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@ -6,16 +6,17 @@ target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:3
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; OPT-LABEL: @test_local_atomicrmw_addressing_loop_uniform_index_max_offset_i32(
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; OPT-NOT: getelementptr
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; OPT: .lr.ph.preheader:
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; OPT: %scevgep2 = getelementptr i32, i32 addrspace(3)* %arg1, i32 16383
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; OPT: br label %.lr.ph
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; OPT: .lr.ph:
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; OPT: %lsr.iv2 = phi i32 addrspace(3)* [ %scevgep3, %.lr.ph ], [ %arg1, %.lr.ph.preheader ]
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; OPT: %lsr.iv3 = phi i32 addrspace(3)* [ %scevgep4, %.lr.ph ], [ %scevgep2, %.lr.ph.preheader ]
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; OPT: %lsr.iv1 = phi i32 addrspace(3)* [ %scevgep, %.lr.ph ], [ %arg0, %.lr.ph.preheader ]
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; OPT: %lsr.iv = phi i32 [ %lsr.iv.next, %.lr.ph ], [ %n, %.lr.ph.preheader ]
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; OPT: %scevgep4 = getelementptr i32, i32 addrspace(3)* %lsr.iv2, i32 16383
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; OPT: %tmp4 = atomicrmw add i32 addrspace(3)* %scevgep4, i32 undef seq_cst
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; OPT: %tmp7 = atomicrmw add i32 addrspace(3)* %lsr.iv1, i32 undef seq_cst
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; OPT: %0 = atomicrmw add i32 addrspace(3)* %lsr.iv1, i32 %tmp8 seq_cst
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; OPT: %tmp4 = atomicrmw add i32 addrspace(3)* %lsr.iv3, i32 undef seq_cst, align 4
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; OPT: %tmp7 = atomicrmw add i32 addrspace(3)* %lsr.iv1, i32 undef seq_cst, align 4
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; OPT: %0 = atomicrmw add i32 addrspace(3)* %lsr.iv1, i32 %tmp8 seq_cst, align 4
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; OPT: %scevgep4 = getelementptr i32, i32 addrspace(3)* %lsr.iv3, i32 1
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; OPT: br i1 %exitcond
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define amdgpu_kernel void @test_local_atomicrmw_addressing_loop_uniform_index_max_offset_i32(i32 addrspace(3)* noalias nocapture %arg0, i32 addrspace(3)* noalias nocapture readonly %arg1, i32 %n) #0 {
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bb:
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}
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; OPT-LABEL: test_local_cmpxchg_addressing_loop_uniform_index_max_offset_i32(
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; OPT-NOT: getelementptr
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; OPT: .lr.ph.preheader:
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; OPT: %scevgep2 = getelementptr i32, i32 addrspace(3)* %arg1, i32 16383
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; OPT: br label %.lr.ph
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; OPT: .lr.ph:
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; OPT: %lsr.iv2 = phi i32 addrspace(3)* [ %scevgep3, %.lr.ph ], [ %arg1, %.lr.ph.preheader ]
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; OPT: %lsr.iv3 = phi i32 addrspace(3)* [ %scevgep4, %.lr.ph ], [ %scevgep2, %.lr.ph.preheader ]
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; OPT: %lsr.iv1 = phi i32 addrspace(3)* [ %scevgep, %.lr.ph ], [ %arg0, %.lr.ph.preheader ]
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; OPT: %lsr.iv = phi i32 [ %lsr.iv.next, %.lr.ph ], [ %n, %.lr.ph.preheader ]
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; OPT: %scevgep4 = getelementptr i32, i32 addrspace(3)* %lsr.iv2, i32 16383
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; OPT: %tmp4 = cmpxchg i32 addrspace(3)* %scevgep4, i32 undef, i32 undef seq_cst monotonic
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; OPT: %tmp4 = cmpxchg i32 addrspace(3)* %lsr.iv3, i32 undef, i32 undef seq_cst monotonic, align 4
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; OPT: %scevgep4 = getelementptr i32, i32 addrspace(3)* %lsr.iv3, i32 1
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define amdgpu_kernel void @test_local_cmpxchg_addressing_loop_uniform_index_max_offset_i32(i32 addrspace(3)* noalias nocapture %arg0, i32 addrspace(3)* noalias nocapture readonly %arg1, i32 %n) #0 {
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bb:
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%tmp = icmp sgt i32 %n, 0
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}
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; OPT-LABEL: @test_local_atomicinc_addressing_loop_uniform_index_max_offset_i32(
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; OPT-NOT: getelementptr
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; OPT: .lr.ph.preheader:
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; OPT: %scevgep2 = getelementptr i32, i32 addrspace(3)* %arg1, i32 16383
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; OPT: br label %.lr.ph
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; OPT: .lr.ph:
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; OPT: %lsr.iv2 = phi i32 addrspace(3)* [ %scevgep3, %.lr.ph ], [ %arg1, %.lr.ph.preheader ]
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; OPT: %lsr.iv3 = phi i32 addrspace(3)* [ %scevgep4, %.lr.ph ], [ %scevgep2, %.lr.ph.preheader ]
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; OPT: %lsr.iv1 = phi i32 addrspace(3)* [ %scevgep, %.lr.ph ], [ %arg0, %.lr.ph.preheader ]
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; OPT: %lsr.iv = phi i32 [ %lsr.iv.next, %.lr.ph ], [ %n, %.lr.ph.preheader ]
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; OPT: %scevgep4 = getelementptr i32, i32 addrspace(3)* %lsr.iv2, i32 16383
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; OPT: %tmp4 = call i32 @llvm.amdgcn.atomic.inc.i32.p3i32(i32 addrspace(3)* %scevgep4, i32 undef, i32 0, i32 0, i1 false)
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; OPT: %tmp4 = call i32 @llvm.amdgcn.atomic.inc.i32.p3i32(i32 addrspace(3)* %lsr.iv3, i32 undef, i32 0, i32 0, i1 false)
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; OPT: %tmp7 = call i32 @llvm.amdgcn.atomic.inc.i32.p3i32(i32 addrspace(3)* %lsr.iv1, i32 undef, i32 0, i32 0, i1 false)
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; OPT: %scevgep4 = getelementptr i32, i32 addrspace(3)* %lsr.iv3, i32 1
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define amdgpu_kernel void @test_local_atomicinc_addressing_loop_uniform_index_max_offset_i32(i32 addrspace(3)* noalias nocapture %arg0, i32 addrspace(3)* noalias nocapture readonly %arg1, i32 %n) #0 {
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bb:
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%tmp = icmp sgt i32 %n, 0
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}
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; OPT-LABEL: @test_local_atomicdec_addressing_loop_uniform_index_max_offset_i32(
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; OPT-NOT: getelementptr
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; OPT: .lr.ph.preheader:
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; OPT: %scevgep2 = getelementptr i32, i32 addrspace(3)* %arg1, i32 16383
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; OPT: br label %.lr.ph
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; OPT: .lr.ph:
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; OPT: %lsr.iv2 = phi i32 addrspace(3)* [ %scevgep3, %.lr.ph ], [ %arg1, %.lr.ph.preheader ]
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; OPT: %lsr.iv3 = phi i32 addrspace(3)* [ %scevgep4, %.lr.ph ], [ %scevgep2, %.lr.ph.preheader ]
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; OPT: %lsr.iv1 = phi i32 addrspace(3)* [ %scevgep, %.lr.ph ], [ %arg0, %.lr.ph.preheader ]
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; OPT: %lsr.iv = phi i32 [ %lsr.iv.next, %.lr.ph ], [ %n, %.lr.ph.preheader ]
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; OPT: %scevgep4 = getelementptr i32, i32 addrspace(3)* %lsr.iv2, i32 16383
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; OPT: %tmp4 = call i32 @llvm.amdgcn.atomic.dec.i32.p3i32(i32 addrspace(3)* %scevgep4, i32 undef, i32 0, i32 0, i1 false)
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; OPT: %tmp4 = call i32 @llvm.amdgcn.atomic.dec.i32.p3i32(i32 addrspace(3)* %lsr.iv3, i32 undef, i32 0, i32 0, i1 false)
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; OPT: %tmp7 = call i32 @llvm.amdgcn.atomic.dec.i32.p3i32(i32 addrspace(3)* %lsr.iv1, i32 undef, i32 0, i32 0, i1 false)
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; OPT: %scevgep4 = getelementptr i32, i32 addrspace(3)* %lsr.iv3, i32 1
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define amdgpu_kernel void @test_local_atomicdec_addressing_loop_uniform_index_max_offset_i32(i32 addrspace(3)* noalias nocapture %arg0, i32 addrspace(3)* noalias nocapture readonly %arg1, i32 %n) #0 {
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bb:
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%tmp = icmp sgt i32 %n, 0
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@ -6,10 +6,13 @@
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target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"
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; OPT-LABEL: @test_global_addressing_loop_uniform_index_max_offset_i32(
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; OPT: .lr.ph.preheader:
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; OPT: %scevgep2 = getelementptr i8, i8 addrspace(1)* %arg1, i64 4095
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; OPT: br label %.lr.ph
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; OPT: {{^}}.lr.ph:
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; OPT: %lsr.iv2 = phi i8 addrspace(1)* [ %scevgep3, %.lr.ph ], [ %arg1, %.lr.ph.preheader ]
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; OPT: %scevgep4 = getelementptr i8, i8 addrspace(1)* %lsr.iv2, i64 4095
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; OPT: load i8, i8 addrspace(1)* %scevgep4, align 1
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; OPT: %lsr.iv3 = phi i8 addrspace(1)* [ %scevgep4, %.lr.ph ], [ %scevgep2, %.lr.ph.preheader ]
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; OPT: load i8, i8 addrspace(1)* %lsr.iv3, align 1
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; OPT: %scevgep4 = getelementptr i8, i8 addrspace(1)* %lsr.iv3, i64 1
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define amdgpu_kernel void @test_global_addressing_loop_uniform_index_max_offset_i32(i32 addrspace(1)* noalias nocapture %arg0, i8 addrspace(1)* noalias nocapture readonly %arg1, i32 %n) #0 {
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bb:
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%tmp = icmp sgt i32 %n, 0
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}
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; OPT-LABEL: @test_local_addressing_loop_uniform_index_max_offset_i32(
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; OPT: .lr.ph.preheader:
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; OPT: %scevgep2 = getelementptr i8, i8 addrspace(3)* %arg1, i32 65535
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; OPT: br label %.lr.ph
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; OPT: {{^}}.lr.ph
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; OPT: %lsr.iv2 = phi i8 addrspace(3)* [ %scevgep3, %.lr.ph ], [ %arg1, %.lr.ph.preheader ]
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; OPT: %scevgep4 = getelementptr i8, i8 addrspace(3)* %lsr.iv2, i32 65535
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; OPT: %tmp4 = load i8, i8 addrspace(3)* %scevgep4, align 1
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; OPT: %lsr.iv3 = phi i8 addrspace(3)* [ %scevgep4, %.lr.ph ], [ %scevgep2, %.lr.ph.preheader ]
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; OPT: %tmp4 = load i8, i8 addrspace(3)* %lsr.iv3, align 1
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; OPT: %scevgep4 = getelementptr i8, i8 addrspace(3)* %lsr.iv3, i32 1
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define amdgpu_kernel void @test_local_addressing_loop_uniform_index_max_offset_i32(i32 addrspace(1)* noalias nocapture %arg0, i8 addrspace(3)* noalias nocapture readonly %arg1, i32 %n) #0 {
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bb:
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%tmp = icmp sgt i32 %n, 0
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