From bef777206ef99b7d81c3007b82037ee4421f8445 Mon Sep 17 00:00:00 2001 From: Ahmed Bougacha Date: Thu, 28 Oct 2021 10:20:11 -0700 Subject: [PATCH] [AArch64] Rename some timm predicates for consistency. NFC. timm isn't the common case, and TImmLeafs should make it clear what they are. We're adding a plain ImmLeaf for 0_65535, so rename i64_imm0_65535 to timm64_0_65535, and imm32_0_7 to timm32_0_7. --- llvm/lib/Target/AArch64/AArch64InstrFormats.td | 14 +++++++------- llvm/lib/Target/AArch64/AArch64InstrInfo.td | 14 +++++++------- llvm/lib/Target/AArch64/SVEInstrFormats.td | 14 +++++++------- 3 files changed, 21 insertions(+), 21 deletions(-) diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td index ecd89b64b8ea..056ef33466ba 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td +++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td @@ -846,13 +846,13 @@ def logical_imm64_not : Operand { let ParserMatchClass = LogicalImm64NotOperand; } -// iXX_imm0_65535 predicates - True if the immediate is in the range [0,65535]. +// immXX_0_65535 predicates - True if the immediate is in the range [0,65535]. let ParserMatchClass = AsmImmRange<0, 65535>, PrintMethod = "printImmHex" in { -def i32_imm0_65535 : Operand, TImmLeaf, TImmLeaf; -def i64_imm0_65535 : Operand, TImmLeaf, TImmLeaf; } @@ -956,8 +956,8 @@ def imm0_3 : Operand, ImmLeaf, TImmLeaf, TImmLeaf { let ParserMatchClass = Imm0_7Operand; @@ -1426,7 +1426,7 @@ class TMSystemINoOperand CRm, string asm, list pattern> // System instructions for exit from transactions class TMSystemException op1, string asm, list pattern> - : I<(outs), (ins i64_imm0_65535:$imm), asm, "\t$imm", "", pattern>, + : I<(outs), (ins timm64_0_65535:$imm), asm, "\t$imm", "", pattern>, Sched<[WriteSys]> { bits<16> imm; let Inst{31-24} = 0b11010100; @@ -4511,7 +4511,7 @@ multiclass MemTagStore opc1, string insn> { let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in class ExceptionGeneration op1, bits<2> ll, string asm> - : I<(outs), (ins i32_imm0_65535:$imm), asm, "\t$imm", "", []>, + : I<(outs), (ins timm32_0_65535:$imm), asm, "\t$imm", "", []>, Sched<[WriteSys]> { bits<16> imm; let Inst{31-24} = 0b11010100; diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td index 6fa4c8d1886b..6cfd2a51743a 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td @@ -1369,7 +1369,7 @@ def TSTART : TMSystemI<0b0000, "tstart", def TCOMMIT : TMSystemINoOperand<0b0000, "tcommit", [(int_aarch64_tcommit)]>; def TCANCEL : TMSystemException<0b011, "tcancel", - [(int_aarch64_tcancel i64_imm0_65535:$imm)]>; + [(int_aarch64_tcancel timm64_0_65535:$imm)]>; def TTEST : TMSystemI<0b0001, "ttest", [(set GPR64:$Rt, (int_aarch64_ttest))]> { let mayLoad = 0; @@ -1388,12 +1388,12 @@ let PostEncoderMethod = "fixMOVZ" in defm MOVZ : MoveImmediate<0b10, "movz">; // First group of aliases covers an implicit "lsl #0". -def : InstAlias<"movk $dst, $imm", (MOVKWi GPR32:$dst, i32_imm0_65535:$imm, 0), 0>; -def : InstAlias<"movk $dst, $imm", (MOVKXi GPR64:$dst, i32_imm0_65535:$imm, 0), 0>; -def : InstAlias<"movn $dst, $imm", (MOVNWi GPR32:$dst, i32_imm0_65535:$imm, 0)>; -def : InstAlias<"movn $dst, $imm", (MOVNXi GPR64:$dst, i32_imm0_65535:$imm, 0)>; -def : InstAlias<"movz $dst, $imm", (MOVZWi GPR32:$dst, i32_imm0_65535:$imm, 0)>; -def : InstAlias<"movz $dst, $imm", (MOVZXi GPR64:$dst, i32_imm0_65535:$imm, 0)>; +def : InstAlias<"movk $dst, $imm", (MOVKWi GPR32:$dst, timm32_0_65535:$imm, 0), 0>; +def : InstAlias<"movk $dst, $imm", (MOVKXi GPR64:$dst, timm32_0_65535:$imm, 0), 0>; +def : InstAlias<"movn $dst, $imm", (MOVNWi GPR32:$dst, timm32_0_65535:$imm, 0)>; +def : InstAlias<"movn $dst, $imm", (MOVNXi GPR64:$dst, timm32_0_65535:$imm, 0)>; +def : InstAlias<"movz $dst, $imm", (MOVZWi GPR32:$dst, timm32_0_65535:$imm, 0)>; +def : InstAlias<"movz $dst, $imm", (MOVZXi GPR64:$dst, timm32_0_65535:$imm, 0)>; // Next, we have various ELF relocations with the ":XYZ_g0:sym" syntax. def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movw_symbol_g3:$sym, 48)>; diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td index fcb96c3b19db..c61bc24ce3bd 100644 --- a/llvm/lib/Target/AArch64/SVEInstrFormats.td +++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td @@ -1837,7 +1837,7 @@ multiclass sve_fp_2op_p_zds_zeroing_hsd { } class sve_fp_ftmad sz, string asm, ZPRRegOp zprty> -: I<(outs zprty:$Zdn), (ins zprty:$_Zdn, zprty:$Zm, imm32_0_7:$imm3), +: I<(outs zprty:$Zdn), (ins zprty:$_Zdn, zprty:$Zm, timm32_0_7:$imm3), asm, "\t$Zdn, $_Zdn, $Zm, $imm3", "", []>, Sched<[]> { @@ -1862,12 +1862,12 @@ multiclass sve_fp_ftmad { def _S : sve_fp_ftmad<0b10, asm, ZPR32>; def _D : sve_fp_ftmad<0b11, asm, ZPR64>; - def : Pat<(nxv8f16 (op (nxv8f16 ZPR16:$Zn), (nxv8f16 ZPR16:$Zm), (i32 imm32_0_7:$imm))), - (!cast(NAME # _H) ZPR16:$Zn, ZPR16:$Zm, imm32_0_7:$imm)>; - def : Pat<(nxv4f32 (op (nxv4f32 ZPR32:$Zn), (nxv4f32 ZPR32:$Zm), (i32 imm32_0_7:$imm))), - (!cast(NAME # _S) ZPR32:$Zn, ZPR32:$Zm, imm32_0_7:$imm)>; - def : Pat<(nxv2f64 (op (nxv2f64 ZPR64:$Zn), (nxv2f64 ZPR64:$Zm), (i32 imm32_0_7:$imm))), - (!cast(NAME # _D) ZPR64:$Zn, ZPR64:$Zm, imm32_0_7:$imm)>; + def : Pat<(nxv8f16 (op (nxv8f16 ZPR16:$Zn), (nxv8f16 ZPR16:$Zm), (i32 timm32_0_7:$imm))), + (!cast(NAME # _H) ZPR16:$Zn, ZPR16:$Zm, timm32_0_7:$imm)>; + def : Pat<(nxv4f32 (op (nxv4f32 ZPR32:$Zn), (nxv4f32 ZPR32:$Zm), (i32 timm32_0_7:$imm))), + (!cast(NAME # _S) ZPR32:$Zn, ZPR32:$Zm, timm32_0_7:$imm)>; + def : Pat<(nxv2f64 (op (nxv2f64 ZPR64:$Zn), (nxv2f64 ZPR64:$Zm), (i32 timm32_0_7:$imm))), + (!cast(NAME # _D) ZPR64:$Zn, ZPR64:$Zm, timm32_0_7:$imm)>; } multiclass sve_fp_2op_i_p_zds_hfd {