forked from OSchip/llvm-project
[MachineSink] Inline getRegUnits
Reg unit sets are uniqued, so no need to wrap it in a set.
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@ -1081,8 +1081,7 @@ using MIRegs = std::pair<MachineInstr *, SmallVector<unsigned, 2>>;
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/// Sink an instruction and its associated debug instructions.
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/// Sink an instruction and its associated debug instructions.
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static void performSink(MachineInstr &MI, MachineBasicBlock &SuccToSinkTo,
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static void performSink(MachineInstr &MI, MachineBasicBlock &SuccToSinkTo,
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MachineBasicBlock::iterator InsertPos,
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MachineBasicBlock::iterator InsertPos,
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SmallVectorImpl<MIRegs> &DbgValuesToSink) {
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ArrayRef<MIRegs> DbgValuesToSink) {
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// If we cannot find a location to use (merge with), then we erase the debug
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// If we cannot find a location to use (merge with), then we erase the debug
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// location to prevent debug-info driven tools from potentially reporting
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// location to prevent debug-info driven tools from potentially reporting
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// wrong location information.
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// wrong location information.
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@ -1101,7 +1100,7 @@ static void performSink(MachineInstr &MI, MachineBasicBlock &SuccToSinkTo,
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// DBG_VALUE location as 'undef', indicating that any earlier variable
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// DBG_VALUE location as 'undef', indicating that any earlier variable
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// location should be terminated as we've optimised away the value at this
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// location should be terminated as we've optimised away the value at this
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// point.
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// point.
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for (auto DbgValueToSink : DbgValuesToSink) {
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for (const auto &DbgValueToSink : DbgValuesToSink) {
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MachineInstr *DbgMI = DbgValueToSink.first;
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MachineInstr *DbgMI = DbgValueToSink.first;
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MachineInstr *NewDbgMI = DbgMI->getMF()->CloneMachineInstr(DbgMI);
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MachineInstr *NewDbgMI = DbgMI->getMF()->CloneMachineInstr(DbgMI);
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SuccToSinkTo.insert(InsertPos, NewDbgMI);
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SuccToSinkTo.insert(InsertPos, NewDbgMI);
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@ -1684,14 +1683,6 @@ static bool hasRegisterDependency(MachineInstr *MI,
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return HasRegDependency;
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return HasRegDependency;
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}
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}
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static SmallSet<MCRegister, 4> getRegUnits(MCRegister Reg,
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const TargetRegisterInfo *TRI) {
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SmallSet<MCRegister, 4> RegUnits;
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for (auto RI = MCRegUnitIterator(Reg, TRI); RI.isValid(); ++RI)
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RegUnits.insert(*RI);
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return RegUnits;
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}
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bool PostRAMachineSinking::tryToSinkCopy(MachineBasicBlock &CurBB,
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bool PostRAMachineSinking::tryToSinkCopy(MachineBasicBlock &CurBB,
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MachineFunction &MF,
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MachineFunction &MF,
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const TargetRegisterInfo *TRI,
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const TargetRegisterInfo *TRI,
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@ -1737,14 +1728,15 @@ bool PostRAMachineSinking::tryToSinkCopy(MachineBasicBlock &CurBB,
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}
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}
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// Record debug use of each reg unit.
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// Record debug use of each reg unit.
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SmallSet<MCRegister, 4> RegUnits = getRegUnits(MO.getReg(), TRI);
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for (auto RI = MCRegUnitIterator(MO.getReg(), TRI); RI.isValid();
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for (MCRegister Reg : RegUnits)
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++RI)
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MIUnits[Reg].push_back(MO.getReg());
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MIUnits[*RI].push_back(MO.getReg());
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}
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}
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}
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}
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if (IsValid) {
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if (IsValid) {
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for (auto RegOps : MIUnits)
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for (auto &RegOps : MIUnits)
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SeenDbgInstrs[RegOps.first].push_back({&MI, RegOps.second});
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SeenDbgInstrs[RegOps.first].emplace_back(&MI,
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std::move(RegOps.second));
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}
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}
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continue;
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continue;
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}
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}
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@ -1791,17 +1783,15 @@ bool PostRAMachineSinking::tryToSinkCopy(MachineBasicBlock &CurBB,
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if (!MO.isReg() || !MO.isDef())
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if (!MO.isReg() || !MO.isDef())
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continue;
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continue;
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SmallSet<MCRegister, 4> Units = getRegUnits(MO.getReg(), TRI);
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for (auto RI = MCRegUnitIterator(MO.getReg(), TRI); RI.isValid(); ++RI) {
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for (MCRegister Reg : Units) {
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for (const auto &MIRegs : SeenDbgInstrs.lookup(*RI)) {
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for (auto MIRegs : SeenDbgInstrs.lookup(Reg)) {
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auto &Regs = DbgValsToSinkMap[MIRegs.first];
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auto &Regs = DbgValsToSinkMap[MIRegs.first];
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for (unsigned Reg : MIRegs.second)
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for (unsigned Reg : MIRegs.second)
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Regs.push_back(Reg);
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Regs.push_back(Reg);
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}
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}
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}
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}
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}
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}
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SmallVector<MIRegs, 4> DbgValsToSink(DbgValsToSinkMap.begin(),
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auto DbgValsToSink = DbgValsToSinkMap.takeVector();
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DbgValsToSinkMap.end());
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// Clear the kill flag if SrcReg is killed between MI and the end of the
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// Clear the kill flag if SrcReg is killed between MI and the end of the
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// block.
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// block.
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