forked from OSchip/llvm-project
[ARM] Constant fold VCTP intrinsics
We can sometimes get into the situation where the operand to a vctp intrinsic becomes constant, such as after a loop is fully unrolled. This adds the constant folding needed for them, allowing them to simplify away and hopefully simplifying remaining instructions. Differential Revision: https://reviews.llvm.org/D84110
This commit is contained in:
David Green
parent
e37b220442
commit
becaa6803a
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@ -41,6 +41,7 @@
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#include "llvm/IR/IntrinsicInst.h"
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#include "llvm/IR/Intrinsics.h"
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#include "llvm/IR/IntrinsicsAMDGPU.h"
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#include "llvm/IR/IntrinsicsARM.h"
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#include "llvm/IR/IntrinsicsX86.h"
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#include "llvm/IR/Operator.h"
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#include "llvm/IR/Type.h"
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@ -1456,6 +1457,11 @@ bool llvm::canConstantFoldCallTo(const CallBase *Call, const Function *F) {
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case Intrinsic::experimental_vector_reduce_smax:
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case Intrinsic::experimental_vector_reduce_umin:
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case Intrinsic::experimental_vector_reduce_umax:
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// Target intrinsics
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case Intrinsic::arm_mve_vctp8:
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case Intrinsic::arm_mve_vctp16:
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case Intrinsic::arm_mve_vctp32:
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case Intrinsic::arm_mve_vctp64:
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return true;
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// Floating point operations cannot be folded in strictfp functions in
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@ -2719,7 +2725,8 @@ static Constant *ConstantFoldVectorCall(StringRef Name,
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SmallVector<Constant *, 4> Lane(Operands.size());
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Type *Ty = FVTy->getElementType();
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if (IntrinsicID == Intrinsic::masked_load) {
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switch (IntrinsicID) {
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case Intrinsic::masked_load: {
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auto *SrcPtr = Operands[0];
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auto *Mask = Operands[2];
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auto *Passthru = Operands[3];
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@ -2757,6 +2764,32 @@ static Constant *ConstantFoldVectorCall(StringRef Name,
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return nullptr;
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return ConstantVector::get(NewElements);
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}
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case Intrinsic::arm_mve_vctp8:
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case Intrinsic::arm_mve_vctp16:
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case Intrinsic::arm_mve_vctp32:
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case Intrinsic::arm_mve_vctp64: {
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if (auto *Op = dyn_cast<ConstantInt>(Operands[0])) {
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unsigned Lanes = FVTy->getNumElements();
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uint64_t Limit = Op->getZExtValue();
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// vctp64 are currently modelled as returning a v4i1, not a v2i1. Make
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// sure we get the limit right in that case and set all relevant lanes.
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if (IntrinsicID == Intrinsic::arm_mve_vctp64)
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Limit *= 2;
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SmallVector<Constant *, 16> NCs;
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for (unsigned i = 0; i < Lanes; i++) {
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if (i < Limit)
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NCs.push_back(ConstantInt::getTrue(Ty));
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else
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NCs.push_back(ConstantInt::getFalse(Ty));
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}
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return ConstantVector::get(NCs);
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}
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break;
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}
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default:
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break;
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}
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for (unsigned I = 0, E = FVTy->getNumElements(); I != E; ++I) {
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// Gather a column of constants.
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@ -0,0 +1,2 @@
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if not 'ARM' in config.root.targets:
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config.unsupported = True
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@ -0,0 +1,267 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -instsimplify -S -o - %s | FileCheck %s
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target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
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define <16 x i1> @vctp8_0() {
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; CHECK-LABEL: @vctp8_0(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: ret <16 x i1> zeroinitializer
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;
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entry:
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%int = call <16 x i1> @llvm.arm.mve.vctp8(i32 0)
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ret <16 x i1> %int
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}
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define <16 x i1> @vctp8_1() {
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; CHECK-LABEL: @vctp8_1(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: ret <16 x i1> <i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>
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;
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entry:
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%int = call <16 x i1> @llvm.arm.mve.vctp8(i32 1)
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ret <16 x i1> %int
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}
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define <16 x i1> @vctp8_8() {
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; CHECK-LABEL: @vctp8_8(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: ret <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>
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;
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entry:
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%int = call <16 x i1> @llvm.arm.mve.vctp8(i32 8)
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ret <16 x i1> %int
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}
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define <16 x i1> @vctp8_15() {
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; CHECK-LABEL: @vctp8_15(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: ret <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false>
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;
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entry:
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%int = call <16 x i1> @llvm.arm.mve.vctp8(i32 15)
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ret <16 x i1> %int
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}
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define <16 x i1> @vctp8_16() {
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; CHECK-LABEL: @vctp8_16(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: ret <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>
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;
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entry:
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%int = call <16 x i1> @llvm.arm.mve.vctp8(i32 16)
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ret <16 x i1> %int
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}
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define <16 x i1> @vctp8_100() {
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; CHECK-LABEL: @vctp8_100(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: ret <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>
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;
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entry:
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%int = call <16 x i1> @llvm.arm.mve.vctp8(i32 100)
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ret <16 x i1> %int
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}
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define <16 x i1> @vctp8_m1() {
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; CHECK-LABEL: @vctp8_m1(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: ret <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>
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;
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entry:
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%int = call <16 x i1> @llvm.arm.mve.vctp8(i32 -1)
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ret <16 x i1> %int
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}
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define <8 x i1> @vctp16_0() {
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; CHECK-LABEL: @vctp16_0(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: ret <8 x i1> zeroinitializer
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;
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entry:
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%int = call <8 x i1> @llvm.arm.mve.vctp16(i32 0)
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ret <8 x i1> %int
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}
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define <8 x i1> @vctp16_1() {
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; CHECK-LABEL: @vctp16_1(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: ret <8 x i1> <i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>
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;
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entry:
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%int = call <8 x i1> @llvm.arm.mve.vctp16(i32 1)
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ret <8 x i1> %int
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}
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define <8 x i1> @vctp16_4() {
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; CHECK-LABEL: @vctp16_4(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: ret <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false>
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;
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entry:
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%int = call <8 x i1> @llvm.arm.mve.vctp16(i32 4)
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ret <8 x i1> %int
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}
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define <8 x i1> @vctp16_7() {
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; CHECK-LABEL: @vctp16_7(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: ret <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false>
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;
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entry:
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%int = call <8 x i1> @llvm.arm.mve.vctp16(i32 7)
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ret <8 x i1> %int
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}
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define <8 x i1> @vctp16_8() {
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; CHECK-LABEL: @vctp16_8(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: ret <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>
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;
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entry:
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%int = call <8 x i1> @llvm.arm.mve.vctp16(i32 8)
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ret <8 x i1> %int
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}
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define <8 x i1> @vctp16_100() {
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; CHECK-LABEL: @vctp16_100(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: ret <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>
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;
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entry:
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%int = call <8 x i1> @llvm.arm.mve.vctp16(i32 100)
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ret <8 x i1> %int
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}
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define <8 x i1> @vctp16_m1() {
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; CHECK-LABEL: @vctp16_m1(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: ret <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>
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;
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entry:
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%int = call <8 x i1> @llvm.arm.mve.vctp16(i32 -1)
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ret <8 x i1> %int
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}
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define <4 x i1> @vctp32_0() {
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; CHECK-LABEL: @vctp32_0(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: ret <4 x i1> zeroinitializer
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;
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entry:
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%int = call <4 x i1> @llvm.arm.mve.vctp32(i32 0)
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ret <4 x i1> %int
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}
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define <4 x i1> @vctp32_1() {
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; CHECK-LABEL: @vctp32_1(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: ret <4 x i1> <i1 true, i1 false, i1 false, i1 false>
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;
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entry:
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%int = call <4 x i1> @llvm.arm.mve.vctp32(i32 1)
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ret <4 x i1> %int
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}
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define <4 x i1> @vctp32_3() {
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; CHECK-LABEL: @vctp32_3(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: ret <4 x i1> <i1 true, i1 true, i1 true, i1 false>
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;
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entry:
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%int = call <4 x i1> @llvm.arm.mve.vctp32(i32 3)
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ret <4 x i1> %int
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}
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define <4 x i1> @vctp32_4() {
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; CHECK-LABEL: @vctp32_4(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: ret <4 x i1> <i1 true, i1 true, i1 true, i1 true>
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;
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entry:
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%int = call <4 x i1> @llvm.arm.mve.vctp32(i32 4)
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ret <4 x i1> %int
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}
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define <4 x i1> @vctp32_100() {
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; CHECK-LABEL: @vctp32_100(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: ret <4 x i1> <i1 true, i1 true, i1 true, i1 true>
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;
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entry:
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%int = call <4 x i1> @llvm.arm.mve.vctp32(i32 100)
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ret <4 x i1> %int
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}
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define <4 x i1> @vctp32_m1() {
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; CHECK-LABEL: @vctp32_m1(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: ret <4 x i1> <i1 true, i1 true, i1 true, i1 true>
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;
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entry:
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%int = call <4 x i1> @llvm.arm.mve.vctp32(i32 -1)
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ret <4 x i1> %int
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}
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define <4 x i1> @vctp64_0() {
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; CHECK-LABEL: @vctp64_0(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: ret <4 x i1> zeroinitializer
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;
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entry:
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%int = call <4 x i1> @llvm.arm.mve.vctp64(i32 0)
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ret <4 x i1> %int
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}
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define <4 x i1> @vctp64_1() {
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; CHECK-LABEL: @vctp64_1(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: ret <4 x i1> <i1 true, i1 true, i1 false, i1 false>
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;
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entry:
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%int = call <4 x i1> @llvm.arm.mve.vctp64(i32 1)
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ret <4 x i1> %int
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}
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define <4 x i1> @vctp64_2() {
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; CHECK-LABEL: @vctp64_2(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: ret <4 x i1> <i1 true, i1 true, i1 true, i1 true>
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;
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entry:
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%int = call <4 x i1> @llvm.arm.mve.vctp64(i32 2)
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ret <4 x i1> %int
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}
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define <4 x i1> @vctp64_100() {
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; CHECK-LABEL: @vctp64_100(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: ret <4 x i1> <i1 true, i1 true, i1 true, i1 true>
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;
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entry:
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%int = call <4 x i1> @llvm.arm.mve.vctp64(i32 100)
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ret <4 x i1> %int
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}
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define <4 x i1> @vctp64_m1() {
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; CHECK-LABEL: @vctp64_m1(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: ret <4 x i1> <i1 true, i1 true, i1 true, i1 true>
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;
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entry:
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%int = call <4 x i1> @llvm.arm.mve.vctp64(i32 -1)
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ret <4 x i1> %int
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}
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declare <4 x i1> @llvm.arm.mve.vctp64(i32)
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declare <4 x i1> @llvm.arm.mve.vctp32(i32)
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declare <8 x i1> @llvm.arm.mve.vctp16(i32)
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declare <16 x i1> @llvm.arm.mve.vctp8(i32)
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