forked from OSchip/llvm-project
[X86][AVX2] Add support for target shuffle combining to BROADCAST
Only support broadcast from vector register so far - memory folding support will have to wait. llvm-svn: 274572
This commit is contained in:
Simon Pilgrim
parent
48adedffb7
commit
bec6543d17
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@ -24717,13 +24717,10 @@ static bool matchUnaryVectorShuffle(MVT SrcVT, ArrayRef<int> Mask,
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return true;
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}
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if (!FloatDomain)
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return false;
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// Check if we have SSE3 which will let us use MOVDDUP etc. The
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// instructions are no slower than UNPCKLPD but has the option to
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// fold the input operand into even an unaligned memory load.
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if (SrcVT.is128BitVector() && Subtarget.hasSSE3()) {
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if (SrcVT.is128BitVector() && Subtarget.hasSSE3() && FloatDomain) {
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if (isTargetShuffleEquivalent(Mask, {0, 0})) {
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Shuffle = X86ISD::MOVDDUP;
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ShuffleVT = MVT::v2f64;
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@ -24741,7 +24738,7 @@ static bool matchUnaryVectorShuffle(MVT SrcVT, ArrayRef<int> Mask,
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}
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}
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if (SrcVT.is256BitVector()) {
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if (SrcVT.is256BitVector() && FloatDomain) {
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assert(Subtarget.hasAVX() && "AVX required for 256-bit vector shuffles");
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if (isTargetShuffleEquivalent(Mask, {0, 0, 2, 2})) {
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Shuffle = X86ISD::MOVDDUP;
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@ -24760,7 +24757,7 @@ static bool matchUnaryVectorShuffle(MVT SrcVT, ArrayRef<int> Mask,
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}
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}
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if (SrcVT.is512BitVector()) {
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if (SrcVT.is512BitVector() && FloatDomain) {
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assert(Subtarget.hasAVX512() &&
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"AVX512 required for 512-bit vector shuffles");
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if (isTargetShuffleEquivalent(Mask, {0, 0, 2, 2, 4, 4, 6, 6})) {
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@ -24782,6 +24779,23 @@ static bool matchUnaryVectorShuffle(MVT SrcVT, ArrayRef<int> Mask,
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}
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}
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// Attempt to match against broadcast-from-vector.
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if (Subtarget.hasAVX2()) {
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for (MVT SVT :
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{MVT::i8, MVT::i16, MVT::i32, MVT::i64, MVT::f32, MVT::f64}) {
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if (FloatDomain != SVT.isFloatingPoint())
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continue;
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unsigned NumElts = SrcVT.getSizeInBits() / SVT.getSizeInBits();
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SmallVector<int, 64> BroadcastMask(NumElts, 0);
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if (isTargetShuffleEquivalent(Mask, BroadcastMask)) {
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Shuffle = X86ISD::VBROADCAST;
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ShuffleVT = MVT::getVectorVT(SVT, NumElts);
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return true;
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}
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}
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}
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return false;
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}
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@ -3,6 +3,7 @@
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declare <8 x i32> @llvm.x86.avx2.permd(<8 x i32>, <8 x i32>)
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declare <8 x float> @llvm.x86.avx2.permps(<8 x float>, <8 x i32>)
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declare <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8>, <16 x i8>)
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declare <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8>, <32 x i8>)
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define <32 x i8> @combine_pshufb_pslldq(<32 x i8> %a0) {
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@ -59,3 +60,126 @@ define <4 x i64> @combine_permq_pshufb(<4 x i64> %a0) {
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%4 = bitcast <32 x i8> %3 to <4 x i64>
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ret <4 x i64> %4
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}
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define <16 x i8> @combine_pshufb_as_vpbroadcastb128(<16 x i8> %a) {
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; CHECK-LABEL: combine_pshufb_as_vpbroadcastb128:
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; CHECK: # BB#0:
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; CHECK-NEXT: vpbroadcastb %xmm0, %xmm0
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; CHECK-NEXT: retq
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%1 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %a, <16 x i8> zeroinitializer)
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ret <16 x i8> %1
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}
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define <32 x i8> @combine_pshufb_as_vpbroadcastb256(<2 x i64> %a) {
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; CHECK-LABEL: combine_pshufb_as_vpbroadcastb256:
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; CHECK: # BB#0:
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; CHECK-NEXT: vpbroadcastb %xmm0, %ymm0
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; CHECK-NEXT: retq
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%1 = shufflevector <2 x i64> %a, <2 x i64> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
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%2 = bitcast <4 x i64> %1 to <32 x i8>
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%3 = call <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8> %2, <32 x i8> zeroinitializer)
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%4 = bitcast <32 x i8> %3 to <8 x i32>
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%5 = call <8 x i32> @llvm.x86.avx2.permd(<8 x i32> %4, <8 x i32> zeroinitializer)
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%6 = bitcast <8 x i32> %5 to <32 x i8>
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ret <32 x i8> %6
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}
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define <16 x i8> @combine_pshufb_as_vpbroadcastw128(<16 x i8> %a) {
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; CHECK-LABEL: combine_pshufb_as_vpbroadcastw128:
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; CHECK: # BB#0:
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; CHECK-NEXT: vpbroadcastw %xmm0, %xmm0
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; CHECK-NEXT: retq
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%1 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %a, <16 x i8> <i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1>)
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ret <16 x i8> %1
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}
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define <32 x i8> @combine_pshufb_as_vpbroadcastw256(<2 x i64> %a) {
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; CHECK-LABEL: combine_pshufb_as_vpbroadcastw256:
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; CHECK: # BB#0:
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; CHECK-NEXT: vpbroadcastw %xmm0, %ymm0
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; CHECK-NEXT: retq
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%1 = shufflevector <2 x i64> %a, <2 x i64> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
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%2 = bitcast <4 x i64> %1 to <32 x i8>
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%3 = call <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8> %2, <32 x i8> <i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1>)
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%4 = bitcast <32 x i8> %3 to <8 x i32>
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%5 = call <8 x i32> @llvm.x86.avx2.permd(<8 x i32> %4, <8 x i32> zeroinitializer)
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%6 = bitcast <8 x i32> %5 to <32 x i8>
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ret <32 x i8> %6
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}
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define <16 x i8> @combine_pshufb_as_vpbroadcastd128(<16 x i8> %a) {
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; CHECK-LABEL: combine_pshufb_as_vpbroadcastd128:
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; CHECK: # BB#0:
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; CHECK-NEXT: vpbroadcastd %xmm0, %xmm0
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; CHECK-NEXT: vpaddb {{.*}}(%rip), %xmm0, %xmm0
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; CHECK-NEXT: retq
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%1 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %a, <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 0, i8 1, i8 2, i8 3, i8 0, i8 1, i8 2, i8 3, i8 0, i8 1, i8 2, i8 3>)
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%2 = add <16 x i8> %1, <i8 0, i8 1, i8 2, i8 3, i8 0, i8 1, i8 2, i8 3, i8 0, i8 1, i8 2, i8 3, i8 0, i8 1, i8 2, i8 3>
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ret <16 x i8> %2
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}
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define <8 x i32> @combine_permd_as_vpbroadcastd256(<4 x i32> %a) {
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; CHECK-LABEL: combine_permd_as_vpbroadcastd256:
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; CHECK: # BB#0:
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; CHECK-NEXT: vpbroadcastd %xmm0, %ymm0
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; CHECK-NEXT: vpaddd {{.*}}(%rip), %ymm0, %ymm0
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; CHECK-NEXT: retq
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%1 = shufflevector <4 x i32> %a, <4 x i32> undef, <8 x i32> <i32 0, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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%2 = call <8 x i32> @llvm.x86.avx2.permd(<8 x i32> %1, <8 x i32> zeroinitializer)
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%3 = add <8 x i32> %2, <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
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ret <8 x i32> %3
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}
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define <16 x i8> @combine_pshufb_as_vpbroadcastq128(<16 x i8> %a) {
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; CHECK-LABEL: combine_pshufb_as_vpbroadcastq128:
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; CHECK: # BB#0:
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; CHECK-NEXT: vpbroadcastq %xmm0, %xmm0
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; CHECK-NEXT: retq
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%1 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %a, <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7>)
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ret <16 x i8> %1
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}
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define <8 x i32> @combine_permd_as_vpbroadcastq256(<4 x i32> %a) {
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; CHECK-LABEL: combine_permd_as_vpbroadcastq256:
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; CHECK: # BB#0:
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; CHECK-NEXT: vpbroadcastq %xmm0, %ymm0
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; CHECK-NEXT: vpaddd {{.*}}(%rip), %ymm0, %ymm0
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; CHECK-NEXT: retq
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%1 = shufflevector <4 x i32> %a, <4 x i32> undef, <8 x i32> <i32 0, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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%2 = call <8 x i32> @llvm.x86.avx2.permd(<8 x i32> %1, <8 x i32> <i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1>)
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%3 = add <8 x i32> %2, <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
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ret <8 x i32> %3
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}
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define <4 x float> @combine_pshufb_as_vpbroadcastss128(<4 x float> %a) {
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; CHECK-LABEL: combine_pshufb_as_vpbroadcastss128:
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; CHECK: # BB#0:
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; CHECK-NEXT: vbroadcastss %xmm0, %xmm0
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; CHECK-NEXT: retq
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%1 = bitcast <4 x float> %a to <16 x i8>
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%2 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %1, <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 0, i8 1, i8 2, i8 3, i8 0, i8 1, i8 2, i8 3, i8 0, i8 1, i8 2, i8 3>)
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%3 = bitcast <16 x i8> %2 to <4 x float>
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ret <4 x float> %3
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}
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define <8 x float> @combine_permd_as_vpbroadcastss256(<4 x float> %a) {
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; CHECK-LABEL: combine_permd_as_vpbroadcastss256:
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; CHECK: # BB#0:
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; CHECK-NEXT: vbroadcastss %xmm0, %ymm0
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; CHECK-NEXT: retq
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%1 = shufflevector <4 x float> %a, <4 x float> undef, <8 x i32> <i32 0, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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%2 = call <8 x float> @llvm.x86.avx2.permps(<8 x float> %1, <8 x i32> zeroinitializer)
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ret <8 x float> %2
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}
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define <4 x double> @combine_permd_as_vpbroadcastsd256(<2 x double> %a) {
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; CHECK-LABEL: combine_permd_as_vpbroadcastsd256:
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; CHECK: # BB#0:
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; CHECK-NEXT: vbroadcastsd %xmm0, %ymm0
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; CHECK-NEXT: retq
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%1 = shufflevector <2 x double> %a, <2 x double> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
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%2 = bitcast <4 x double> %1 to <8 x float>
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%3 = call <8 x float> @llvm.x86.avx2.permps(<8 x float> %2, <8 x i32> <i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1>)
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%4 = bitcast <8 x float> %3 to <4 x double>
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ret <4 x double> %4
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}
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@ -5,6 +5,8 @@ declare <64 x i8> @llvm.x86.avx512.mask.pshuf.b.512(<64 x i8>, <64 x i8>, <64 x
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declare <8 x double> @llvm.x86.avx512.mask.permvar.df.512(<8 x double>, <8 x i64>, <8 x double>, i8)
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declare <8 x i64> @llvm.x86.avx512.mask.permvar.di.512(<8 x i64>, <8 x i64>, <8 x i64>, i8)
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declare <16 x i32> @llvm.x86.avx512.mask.permvar.si.512(<16 x i32>, <16 x i32>, <16 x i32>, i16)
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declare <32 x i16> @llvm.x86.avx512.mask.permvar.hi.512(<32 x i16>, <32 x i16>, <32 x i16>, i32)
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declare <8 x double> @llvm.x86.avx512.maskz.vpermt2var.pd.512(<8 x i64>, <8 x double>, <8 x double>, i8)
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declare <16 x float> @llvm.x86.avx512.maskz.vpermt2var.ps.512(<16 x i32>, <16 x float>, <16 x float>, i16)
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@ -369,3 +371,31 @@ define <64 x i8> @combine_pshufb_identity_mask(<64 x i8> %x0, i64 %m) {
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%res1 = call <64 x i8> @llvm.x86.avx512.mask.pshuf.b.512(<64 x i8> %res0, <64 x i8> %mask, <64 x i8> %select, i64 %m)
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ret <64 x i8> %res1
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}
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define <32 x i16> @combine_permvar_as_vpbroadcastw512(<32 x i16> %x0) {
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; CHECK-LABEL: combine_permvar_as_vpbroadcastw512:
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; CHECK: # BB#0:
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; CHECK-NEXT: vpbroadcastw %xmm0, %zmm0
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; CHECK-NEXT: retq
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%1 = call <32 x i16> @llvm.x86.avx512.mask.permvar.hi.512(<32 x i16> %x0, <32 x i16> zeroinitializer, <32 x i16> undef, i32 -1)
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ret <32 x i16> %1
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}
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define <16 x i32> @combine_permvar_as_vpbroadcastd512(<16 x i32> %x0) {
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; CHECK-LABEL: combine_permvar_as_vpbroadcastd512:
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; CHECK: # BB#0:
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; CHECK-NEXT: vpbroadcastd %xmm0, %zmm0
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; CHECK-NEXT: retq
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%1 = call <16 x i32> @llvm.x86.avx512.mask.permvar.si.512(<16 x i32> %x0, <16 x i32> zeroinitializer, <16 x i32> undef, i16 -1)
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ret <16 x i32> %1
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}
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define <8 x i64> @combine_permvar_as_vpbroadcastq512(<8 x i64> %x0) {
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; CHECK-LABEL: combine_permvar_as_vpbroadcastq512:
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; CHECK: # BB#0:
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; CHECK-NEXT: vpxord %zmm1, %zmm1, %zmm1
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; CHECK-NEXT: vpermq %zmm0, %zmm1, %zmm0
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; CHECK-NEXT: retq
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%1 = call <8 x i64> @llvm.x86.avx512.mask.permvar.di.512(<8 x i64> %x0, <8 x i64> zeroinitializer, <8 x i64> undef, i8 -1)
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ret <8 x i64> %1
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}
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