maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

[MCA][InstrBuilder] Check for the presence of flag VariadicOpsAreDefs. 

This patch fixes the logic that checks for variadic register definitions,

Before llvm-svn 348114 (commit 4cf35b4ab0), it was not possible to explicitly
mark variadic operands as definitions. By default, variadic operands of an
MCInst were always assumed to be uses. A number of had-hoc checks were
introduced in the InstrBuilder to fix the processing of variadic register
operands of ARM ldm/stm variants.

This patch simply replaces those old (and buggy) checks with a much simpler (and
correct) check for MCID::Flag::VariadicOpsAreDefs.
This commit is contained in:
Andrea Di Biagio 2021-06-15 00:52:16 +01:00
parent 13f0b85212
commit beb5213a2e
2 changed files with 4 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
llvm/lib/MCA/InstrBuilder.cpp
View File

@ -391,15 +391,7 @@ void InstrBuilder::populateWrites(InstrDesc &ID, const MCInst &MCI,
if (!NumVariadicOps)
return;
// FIXME: if an instruction opcode is flagged 'mayStore', and it has no
// "unmodeledSideEffects', then this logic optimistically assumes that any
// extra register operands in the variadic sequence is not a register
// definition.
//
// Otherwise, we conservatively assume that any register operand from the
// variadic sequence is both a register read and a register write.
bool AssumeUsesOnly = MCDesc.mayStore() && !MCDesc.mayLoad() &&
!MCDesc.hasUnmodeledSideEffects();
bool AssumeUsesOnly = !MCDesc.variadicOpsAreDefs();
CurrentDef = NumExplicitDefs + NumImplicitDefs + MCDesc.hasOptionalDef();
for (unsigned I = 0, OpIndex = MCDesc.getNumOperands();
I < NumVariadicOps && !AssumeUsesOnly; ++I, ++OpIndex) {
@ -466,12 +458,7 @@ void InstrBuilder::populateReads(InstrDesc &ID, const MCInst &MCI,
CurrentUse += NumImplicitUses;
// FIXME: If an instruction opcode is marked as 'mayLoad', and it has no
// "unmodeledSideEffects", then this logic optimistically assumes that any
// extra register operand in the variadic sequence is not a register
// definition.
bool AssumeDefsOnly = !MCDesc.mayStore() && MCDesc.mayLoad() &&
!MCDesc.hasUnmodeledSideEffects();
bool AssumeDefsOnly = MCDesc.variadicOpsAreDefs();
for (unsigned I = 0, OpIndex = MCDesc.getNumOperands();
I < NumVariadicOps && !AssumeDefsOnly; ++I, ++OpIndex) {
const MCOperand &Op = MCI.getOperand(OpIndex);

4
llvm/test/tools/llvm-mca/ARM/cortex-a57-carryover.s
View File

@ -80,6 +80,6 @@
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3]
# CHECK-NEXT: 0. 10 5.5 0.1 0.0 pop {r3, r4, r5, r6, r7, pc}
# CHECK-NEXT: 0. 10 5.5 2.7 0.0 pop {r3, r4, r5, r6, r7, pc}
# CHECK-NEXT: 1. 10 3.6 0.0 3.9 nop
# CHECK-NEXT: 10 4.6 0.1 2.0 <total>
# CHECK-NEXT: 10 4.6 1.4 2.0 <total>