forked from OSchip/llvm-project
[mips] Fix definitions of multiply, multiply-add/sub and divide instructions.
The new instructions have explicit register output operands and use table-gen patterns instead of C++ code to do instruction selection. Mips16's instructions are unaffected by this change. llvm-svn: 178403
This commit is contained in:
Akira Hatanaka
parent
b8cb8359ce
commit
be8612f6f4
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@ -1466,14 +1466,14 @@ def: Mips16Pat<(i32 immZExt16:$in), (LiRxImmX16 immZExt16:$in)>;
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// MipsDivRem
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//
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def: Mips16Pat
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<(MipsDivRem CPU16Regs:$rx, CPU16Regs:$ry),
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<(MipsDivRem16 CPU16Regs:$rx, CPU16Regs:$ry),
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(DivRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>;
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//
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// MipsDivRemU
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//
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def: Mips16Pat
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<(MipsDivRemU CPU16Regs:$rx, CPU16Regs:$ry),
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<(MipsDivRemU16 CPU16Regs:$rx, CPU16Regs:$ry),
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(DivuRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>;
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// signed a,b
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@ -187,10 +187,16 @@ def DMULT : Mult<"dmult", IIImul, CPU64RegsOpnd, [HI64, LO64]>,
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MULT_FM<0, 0x1c>;
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def DMULTu : Mult<"dmultu", IIImul, CPU64RegsOpnd, [HI64, LO64]>,
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MULT_FM<0, 0x1d>;
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def DSDIV : Div<MipsDivRem, "ddiv", IIIdiv, CPU64RegsOpnd, [HI64, LO64]>,
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MULT_FM<0, 0x1e>;
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def DUDIV : Div<MipsDivRemU, "ddivu", IIIdiv, CPU64RegsOpnd, [HI64, LO64]>,
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MULT_FM<0, 0x1f>;
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def PseudoDMULT : MultDivPseudo<DMULT, ACRegs128, CPU64RegsOpnd, MipsMult,
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IIImul>;
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def PseudoDMULTu : MultDivPseudo<DMULTu, ACRegs128, CPU64RegsOpnd, MipsMultu,
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IIImul>;
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def DSDIV : Div<"ddiv", IIIdiv, CPU64RegsOpnd, [HI64, LO64]>, MULT_FM<0, 0x1e>;
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def DUDIV : Div<"ddivu", IIIdiv, CPU64RegsOpnd, [HI64, LO64]>, MULT_FM<0, 0x1f>;
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def PseudoDSDIV : MultDivPseudo<DSDIV, ACRegs128, CPU64RegsOpnd, MipsDivRem,
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IIIdiv, 0>;
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def PseudoDUDIV : MultDivPseudo<DUDIV, ACRegs128, CPU64RegsOpnd, MipsDivRemU,
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IIIdiv, 0>;
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def MTHI64 : MoveToLOHI<"mthi", CPU64Regs, [HI64]>, MTLO_FM<0x11>;
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def MTLO64 : MoveToLOHI<"mtlo", CPU64Regs, [LO64]>, MTLO_FM<0x13>;
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@ -314,6 +320,10 @@ def : MipsPat<(i64 (sext_inreg CPU64Regs:$src, i32)),
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// bswap MipsPattern
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def : MipsPat<(bswap CPU64Regs:$rt), (DSHD (DSBH CPU64Regs:$rt))>;
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// mflo/hi patterns.
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def : MipsPat<(i64 (ExtractLOHI ACRegs128:$ac, imm:$lohi_idx)),
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(EXTRACT_SUBREG ACRegs128:$ac, imm:$lohi_idx)>;
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//===----------------------------------------------------------------------===//
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// Instruction aliases
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//===----------------------------------------------------------------------===//
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@ -461,28 +461,32 @@ static bool selectMADD(SDNode *ADDENode, SelectionDAG *CurDAG) {
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SDValue Chain = CurDAG->getEntryNode();
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DebugLoc DL = ADDENode->getDebugLoc();
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// Initialize accumulator.
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SDValue ACCIn = CurDAG->getNode(MipsISD::InsertLOHI, DL, MVT::Untyped,
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ADDCNode->getOperand(1),
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ADDENode->getOperand(1));
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// create MipsMAdd(u) node
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MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd;
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SDValue MAdd = CurDAG->getNode(MultOpc, DL, MVT::Glue,
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SDValue MAdd = CurDAG->getNode(MultOpc, DL, MVT::Untyped,
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MultNode->getOperand(0),// Factor 0
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MultNode->getOperand(1),// Factor 1
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ADDCNode->getOperand(1),// Lo0
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ADDENode->getOperand(1));// Hi0
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// create CopyFromReg nodes
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SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, DL, Mips::LO, MVT::i32,
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MAdd);
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SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), DL,
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Mips::HI, MVT::i32,
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CopyFromLo.getValue(2));
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ACCIn);
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// replace uses of adde and addc here
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if (!SDValue(ADDCNode, 0).use_empty())
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CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), CopyFromLo);
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if (!SDValue(ADDENode, 0).use_empty())
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CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), CopyFromHi);
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if (!SDValue(ADDCNode, 0).use_empty()) {
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SDValue LoIdx = CurDAG->getConstant(Mips::sub_lo, MVT::i32);
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SDValue LoOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MAdd,
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LoIdx);
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CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), LoOut);
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}
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if (!SDValue(ADDENode, 0).use_empty()) {
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SDValue HiIdx = CurDAG->getConstant(Mips::sub_hi, MVT::i32);
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SDValue HiOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MAdd,
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HiIdx);
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CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), HiOut);
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}
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return true;
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}
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@ -534,28 +538,32 @@ static bool selectMSUB(SDNode *SUBENode, SelectionDAG *CurDAG) {
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SDValue Chain = CurDAG->getEntryNode();
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DebugLoc DL = SUBENode->getDebugLoc();
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// Initialize accumulator.
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SDValue ACCIn = CurDAG->getNode(MipsISD::InsertLOHI, DL, MVT::Untyped,
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SUBCNode->getOperand(0),
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SUBENode->getOperand(0));
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// create MipsSub(u) node
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MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub;
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SDValue MSub = CurDAG->getNode(MultOpc, DL, MVT::Glue,
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MultNode->getOperand(0),// Factor 0
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MultNode->getOperand(1),// Factor 1
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SUBCNode->getOperand(0),// Lo0
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SUBENode->getOperand(0));// Hi0
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// create CopyFromReg nodes
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SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, DL, Mips::LO, MVT::i32,
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MSub);
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SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), DL,
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Mips::HI, MVT::i32,
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CopyFromLo.getValue(2));
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ACCIn);
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// replace uses of sube and subc here
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if (!SDValue(SUBCNode, 0).use_empty())
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CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), CopyFromLo);
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if (!SDValue(SUBENode, 0).use_empty())
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CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), CopyFromHi);
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if (!SDValue(SUBCNode, 0).use_empty()) {
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SDValue LoIdx = CurDAG->getConstant(Mips::sub_lo, MVT::i32);
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SDValue LoOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MSub,
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LoIdx);
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CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), LoOut);
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}
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if (!SDValue(SUBENode, 0).use_empty()) {
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SDValue HiIdx = CurDAG->getConstant(Mips::sub_hi, MVT::i32);
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SDValue HiOut = CurDAG->getNode(MipsISD::ExtractLOHI, DL, MVT::i32, MSub,
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HiIdx);
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CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), HiOut);
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}
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return true;
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}
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@ -595,8 +603,8 @@ static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG,
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EVT Ty = N->getValueType(0);
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unsigned LO = (Ty == MVT::i32) ? Mips::LO : Mips::LO64;
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unsigned HI = (Ty == MVT::i32) ? Mips::HI : Mips::HI64;
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unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem :
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MipsISD::DivRemU;
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unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 :
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MipsISD::DivRemU16;
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DebugLoc DL = N->getDebugLoc();
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SDValue DivRem = DAG.getNode(Opc, DL, MVT::Glue,
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@ -23,13 +23,16 @@ def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
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SDTCisInt<4>]>;
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def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
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def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
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def SDT_MipsMAddMSub : SDTypeProfile<0, 4,
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[SDTCisVT<0, i32>, SDTCisSameAs<0, 1>,
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SDTCisSameAs<1, 2>,
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SDTCisSameAs<2, 3>]>;
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def SDT_MipsDivRem : SDTypeProfile<0, 2,
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[SDTCisInt<0>,
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SDTCisSameAs<0, 1>]>;
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def SDT_ExtractLOHI : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVT<1, untyped>,
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SDTCisVT<2, i32>]>;
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def SDT_InsertLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
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SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
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def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>,
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SDTCisSameAs<1, 2>]>;
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def SDT_MipsMAddMSub : SDTypeProfile<1, 3,
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[SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
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SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
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def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
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def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
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@ -82,20 +85,27 @@ def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
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[SDNPHasChain, SDNPSideEffect,
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SDNPOptInGlue, SDNPOutGlue]>;
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// Node used to extract integer from LO/HI register.
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def ExtractLOHI : SDNode<"MipsISD::ExtractLOHI", SDT_ExtractLOHI>;
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// Node used to insert 32-bit integers to LOHI register pair.
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def InsertLOHI : SDNode<"MipsISD::InsertLOHI", SDT_InsertLOHI>;
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// Mult nodes.
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def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>;
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def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>;
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// MAdd*/MSub* nodes
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def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub,
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[SDNPOptInGlue, SDNPOutGlue]>;
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def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub,
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[SDNPOptInGlue, SDNPOutGlue]>;
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def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub,
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[SDNPOptInGlue, SDNPOutGlue]>;
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def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub,
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[SDNPOptInGlue, SDNPOutGlue]>;
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def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>;
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def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>;
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def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>;
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def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>;
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// DivRem(u) nodes
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def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsDivRem,
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[SDNPOutGlue]>;
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def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsDivRem,
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def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>;
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def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>;
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def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16, [SDNPOutGlue]>;
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def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16,
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[SDNPOutGlue]>;
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// Target constant nodes that are not part of any isel patterns and remain
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@ -382,10 +392,9 @@ class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
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}
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// Arithmetic Multiply ADD/SUB
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class MArithR<string opstr, SDPatternOperator op = null_frag, bit isComm = 0> :
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class MArithR<string opstr, bit isComm = 0> :
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InstSE<(outs), (ins CPURegsOpnd:$rs, CPURegsOpnd:$rt),
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!strconcat(opstr, "\t$rs, $rt"),
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[(op CPURegsOpnd:$rs, CPURegsOpnd:$rt, LO, HI)], IIImul, FrmR> {
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!strconcat(opstr, "\t$rs, $rt"), [], IIImul, FrmR> {
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let Defs = [HI, LO];
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let Uses = [HI, LO];
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let isCommutable = isComm;
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@ -629,11 +638,34 @@ class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
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let neverHasSideEffects = 1;
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}
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class Div<SDNode op, string opstr, InstrItinClass itin, RegisterOperand RO,
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// Pseudo multiply/divide instruction with explicit accumulator register
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// operands.
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class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1,
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SDPatternOperator OpNode, InstrItinClass Itin,
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bit IsComm = 1, bit HasSideEffects = 0> :
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PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt),
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[(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>,
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PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> {
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let isCommutable = IsComm;
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let hasSideEffects = HasSideEffects;
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}
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// Pseudo multiply add/sub instruction with explicit accumulator register
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// operands.
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class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode>
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: PseudoSE<(outs ACRegs:$ac),
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(ins CPURegsOpnd:$rs, CPURegsOpnd:$rt, ACRegs:$acin),
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[(set ACRegs:$ac,
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(OpNode CPURegsOpnd:$rs, CPURegsOpnd:$rt, ACRegs:$acin))],
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IIImul>,
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PseudoInstExpansion<(RealInst CPURegsOpnd:$rs, CPURegsOpnd:$rt)> {
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string Constraints = "$acin = $ac";
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}
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class Div<string opstr, InstrItinClass itin, RegisterOperand RO,
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list<Register> DefRegs> :
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InstSE<(outs), (ins RO:$rs, RO:$rt),
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!strconcat(opstr, "\t$$zero, $rs, $rt"), [(op RO:$rs, RO:$rt)], itin,
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FrmR> {
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InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"),
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[], itin, FrmR> {
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let Defs = DefRegs;
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}
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@ -934,10 +966,13 @@ let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in {
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/// Multiply and Divide Instructions.
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def MULT : Mult<"mult", IIImul, CPURegsOpnd, [HI, LO]>, MULT_FM<0, 0x18>;
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def MULTu : Mult<"multu", IIImul, CPURegsOpnd, [HI, LO]>, MULT_FM<0, 0x19>;
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def SDIV : Div<MipsDivRem, "div", IIIdiv, CPURegsOpnd, [HI, LO]>,
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MULT_FM<0, 0x1a>;
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def UDIV : Div<MipsDivRemU, "divu", IIIdiv, CPURegsOpnd, [HI, LO]>,
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MULT_FM<0, 0x1b>;
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def PseudoMULT : MultDivPseudo<MULT, ACRegs, CPURegsOpnd, MipsMult, IIImul>;
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def PseudoMULTu : MultDivPseudo<MULTu, ACRegs, CPURegsOpnd, MipsMultu, IIImul>;
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def SDIV : Div<"div", IIIdiv, CPURegsOpnd, [HI, LO]>, MULT_FM<0, 0x1a>;
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def UDIV : Div<"divu", IIIdiv, CPURegsOpnd, [HI, LO]>, MULT_FM<0, 0x1b>;
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def PseudoSDIV : MultDivPseudo<SDIV, ACRegs, CPURegsOpnd, MipsDivRem, IIIdiv, 0>;
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def PseudoUDIV : MultDivPseudo<UDIV, ACRegs, CPURegsOpnd, MipsDivRemU, IIIdiv,
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0>;
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def MTHI : MoveToLOHI<"mthi", CPURegs, [HI]>, MTLO_FM<0x11>;
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def MTLO : MoveToLOHI<"mtlo", CPURegs, [LO]>, MTLO_FM<0x13>;
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@ -965,10 +1000,14 @@ def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
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def LEA_ADDiu : EffectiveAddress<"addiu", CPURegs, mem_ea>, LW_FM<9>;
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// MADD*/MSUB*
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def MADD : MArithR<"madd", MipsMAdd, 1>, MULT_FM<0x1c, 0>;
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def MADDU : MArithR<"maddu", MipsMAddu, 1>, MULT_FM<0x1c, 1>;
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def MSUB : MArithR<"msub", MipsMSub>, MULT_FM<0x1c, 4>;
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def MSUBU : MArithR<"msubu", MipsMSubu>, MULT_FM<0x1c, 5>;
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def MADD : MArithR<"madd", 1>, MULT_FM<0x1c, 0>;
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def MADDU : MArithR<"maddu", 1>, MULT_FM<0x1c, 1>;
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def MSUB : MArithR<"msub">, MULT_FM<0x1c, 4>;
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def MSUBU : MArithR<"msubu">, MULT_FM<0x1c, 5>;
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def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd>;
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def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu>;
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def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub>;
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def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu>;
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def RDHWR : ReadHardware<CPURegs, HWRegsOpnd>, RDHWR_FM;
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@ -1240,6 +1279,10 @@ defm : SetgeImmPats<CPURegs, SLTi, SLTiu>;
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// bswap pattern
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def : MipsPat<(bswap CPURegs:$rt), (ROTR (WSBH CPURegs:$rt), 16)>;
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// mflo/hi patterns.
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def : MipsPat<(i32 (ExtractLOHI ACRegs:$ac, imm:$lohi_idx)),
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(EXTRACT_SUBREG ACRegs:$ac, imm:$lohi_idx)>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Floating Point Support
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
|
|
|||
|
|
@ -450,6 +450,19 @@ std::pair<bool, SDNode*> MipsSEDAGToDAGISel::selectNode(SDNode *Node) {
|
|||
ReplaceUses(SDValue(Node, 0), ResNode);
|
||||
return std::make_pair(true, ResNode.getNode());
|
||||
}
|
||||
|
||||
case MipsISD::InsertLOHI: {
|
||||
unsigned RCID = Subtarget.hasDSP() ? Mips::ACRegsDSPRegClassID :
|
||||
Mips::ACRegsRegClassID;
|
||||
SDValue RegClass = CurDAG->getTargetConstant(RCID, MVT::i32);
|
||||
SDValue LoIdx = CurDAG->getTargetConstant(Mips::sub_lo, MVT::i32);
|
||||
SDValue HiIdx = CurDAG->getTargetConstant(Mips::sub_hi, MVT::i32);
|
||||
const SDValue Ops[] = { RegClass, Node->getOperand(0), LoIdx,
|
||||
Node->getOperand(1), HiIdx };
|
||||
SDNode *Res = CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, DL,
|
||||
MVT::Untyped, Ops, 5);
|
||||
return std::make_pair(true, Res);
|
||||
}
|
||||
}
|
||||
|
||||
return std::make_pair(false, (SDNode*)NULL);
|
||||
|
|
|
|||
|
|
@ -60,6 +60,18 @@ MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM)
|
|||
}
|
||||
}
|
||||
|
||||
setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom);
|
||||
setOperationAction(ISD::UMUL_LOHI, MVT::i32, Custom);
|
||||
setOperationAction(ISD::MULHS, MVT::i32, Custom);
|
||||
setOperationAction(ISD::MULHU, MVT::i32, Custom);
|
||||
|
||||
if (HasMips64)
|
||||
setOperationAction(ISD::MUL, MVT::i64, Custom);
|
||||
|
||||
setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
|
||||
setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
|
||||
setOperationAction(ISD::SDIVREM, MVT::i64, Custom);
|
||||
setOperationAction(ISD::UDIVREM, MVT::i64, Custom);
|
||||
setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
|
||||
setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
|
||||
setOperationAction(ISD::LOAD, MVT::i32, Custom);
|
||||
|
|
@ -89,6 +101,21 @@ MipsSETargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const {
|
|||
}
|
||||
}
|
||||
|
||||
SDValue MipsSETargetLowering::LowerOperation(SDValue Op,
|
||||
SelectionDAG &DAG) const {
|
||||
switch(Op.getOpcode()) {
|
||||
case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG);
|
||||
case ISD::UMUL_LOHI: return lowerMulDiv(Op, MipsISD::Multu, true, true, DAG);
|
||||
case ISD::MULHS: return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG);
|
||||
case ISD::MULHU: return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG);
|
||||
case ISD::MUL: return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG);
|
||||
case ISD::SDIVREM: return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG);
|
||||
case ISD::UDIVREM: return lowerMulDiv(Op, MipsISD::DivRemU, true, true, DAG);
|
||||
}
|
||||
|
||||
return MipsTargetLowering::LowerOperation(Op, DAG);
|
||||
}
|
||||
|
||||
MachineBasicBlock *
|
||||
MipsSETargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
|
||||
MachineBasicBlock *BB) const {
|
||||
|
|
@ -133,6 +160,29 @@ getOpndList(SmallVectorImpl<SDValue> &Ops,
|
|||
InternalLinkage, CLI, Callee, Chain);
|
||||
}
|
||||
|
||||
SDValue MipsSETargetLowering::lowerMulDiv(SDValue Op, unsigned NewOpc,
|
||||
bool HasLo, bool HasHi,
|
||||
SelectionDAG &DAG) const {
|
||||
EVT Ty = Op.getOperand(0).getValueType();
|
||||
DebugLoc DL = Op.getDebugLoc();
|
||||
SDValue Mult = DAG.getNode(NewOpc, DL, MVT::Untyped,
|
||||
Op.getOperand(0), Op.getOperand(1));
|
||||
SDValue Lo, Hi;
|
||||
|
||||
if (HasLo)
|
||||
Lo = DAG.getNode(MipsISD::ExtractLOHI, DL, Ty, Mult,
|
||||
DAG.getConstant(Mips::sub_lo, MVT::i32));
|
||||
if (HasHi)
|
||||
Hi = DAG.getNode(MipsISD::ExtractLOHI, DL, Ty, Mult,
|
||||
DAG.getConstant(Mips::sub_hi, MVT::i32));
|
||||
|
||||
if (!HasLo || !HasHi)
|
||||
return HasLo ? Lo : Hi;
|
||||
|
||||
SDValue Vals[] = { Lo, Hi };
|
||||
return DAG.getMergeValues(Vals, 2, DL);
|
||||
}
|
||||
|
||||
MachineBasicBlock * MipsSETargetLowering::
|
||||
emitBPOSGE32(MachineInstr *MI, MachineBasicBlock *BB) const{
|
||||
// $bb:
|
||||
|
|
|
|||
|
|
@ -24,6 +24,8 @@ namespace llvm {
|
|||
|
||||
virtual bool allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const;
|
||||
|
||||
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
|
||||
|
||||
virtual MachineBasicBlock *
|
||||
EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
|
||||
|
||||
|
|
@ -47,6 +49,9 @@ namespace llvm {
|
|||
bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
|
||||
CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const;
|
||||
|
||||
SDValue lowerMulDiv(SDValue Op, unsigned NewOpc, bool HasLo, bool HasHi,
|
||||
SelectionDAG &DAG) const;
|
||||
|
||||
MachineBasicBlock *emitBPOSGE32(MachineInstr *MI,
|
||||
MachineBasicBlock *BB) const;
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in New Issue