forked from OSchip/llvm-project
[AArch64][GlobalISel] Add a combine to fold away truncate in: G_ICMP EQ/NE (G_TRUNC(v), 0)
We try to do this optimization if we can determine that testing for the truncated bits with an eq/ne predicate results in the same thing as testing the lower bits. Differential Revision: https://reviews.llvm.org/D95645
This commit is contained in:
Amara Emerson
parent
e9dc94291e
commit
be62b3ba34
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@ -17,9 +17,17 @@ def fconstant_to_constant : GICombineRule<
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[{ return matchFConstantToConstant(*${root}, MRI); }]),
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(apply [{ applyFConstantToConstant(*${root}); }])>;
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def icmp_redundant_trunc_matchdata : GIDefMatchData<"Register">;
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def icmp_redundant_trunc : GICombineRule<
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(defs root:$root, icmp_redundant_trunc_matchdata:$matchinfo),
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(match (wip_match_opcode G_ICMP):$root,
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[{ return matchICmpRedundantTrunc(*${root}, MRI, Helper.getKnownBits(), ${matchinfo}); }]),
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(apply [{ applyICmpRedundantTrunc(*${root}, MRI, B, Observer, ${matchinfo}); }])>;
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def AArch64PreLegalizerCombinerHelper: GICombinerHelper<
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"AArch64GenPreLegalizerCombinerHelper", [all_combines,
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fconstant_to_constant]> {
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fconstant_to_constant,
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icmp_redundant_trunc]> {
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let DisableRuleOption = "aarch64prelegalizercombiner-disable-rule";
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let StateClass = "AArch64PreLegalizerCombinerHelperState";
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let AdditionalArguments = [];
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@ -17,9 +17,13 @@
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#include "llvm/CodeGen/GlobalISel/CombinerInfo.h"
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#include "llvm/CodeGen/GlobalISel/GISelKnownBits.h"
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#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
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#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#include "llvm/IR/Instructions.h"
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#include "llvm/Support/Debug.h"
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#define DEBUG_TYPE "aarch64-prelegalizer-combiner"
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@ -53,6 +57,56 @@ static void applyFConstantToConstant(MachineInstr &MI) {
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MI.eraseFromParent();
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}
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/// Try to match a G_ICMP of a G_TRUNC with zero, in which the truncated bits
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/// are sign bits. In this case, we can transform the G_ICMP to directly compare
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/// the wide value with a zero.
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static bool matchICmpRedundantTrunc(MachineInstr &MI, MachineRegisterInfo &MRI,
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GISelKnownBits *KB, Register &MatchInfo) {
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assert(MI.getOpcode() == TargetOpcode::G_ICMP && KB);
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auto Pred = (CmpInst::Predicate)MI.getOperand(1).getPredicate();
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if (!ICmpInst::isEquality(Pred))
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return false;
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Register LHS = MI.getOperand(2).getReg();
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LLT LHSTy = MRI.getType(LHS);
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if (!LHSTy.isScalar())
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return false;
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Register RHS = MI.getOperand(3).getReg();
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Register WideReg;
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if (!mi_match(LHS, MRI, m_GTrunc(m_Reg(WideReg))) ||
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!mi_match(RHS, MRI, m_SpecificICst(0)))
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return false;
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LLT WideTy = MRI.getType(WideReg);
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if (KB->computeNumSignBits(WideReg) <=
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WideTy.getSizeInBits() - LHSTy.getSizeInBits())
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return false;
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MatchInfo = WideReg;
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return true;
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}
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static bool applyICmpRedundantTrunc(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &Builder,
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GISelChangeObserver &Observer,
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Register &WideReg) {
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assert(MI.getOpcode() == TargetOpcode::G_ICMP);
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LLT WideTy = MRI.getType(WideReg);
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// We're going to directly use the wide register as the LHS, and then use an
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// equivalent size zero for RHS.
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Builder.setInstrAndDebugLoc(MI);
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auto WideZero = Builder.buildConstant(WideTy, 0);
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Observer.changingInstr(MI);
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MI.getOperand(2).setReg(WideReg);
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MI.getOperand(3).setReg(WideZero.getReg(0));
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Observer.changedInstr(MI);
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return true;
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}
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class AArch64PreLegalizerCombinerHelperState {
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protected:
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CombinerHelper &Helper;
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@ -0,0 +1,107 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple aarch64-apple-ios -run-pass=aarch64-prelegalizer-combiner %s -o - -verify-machineinstrs | FileCheck %s
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# This test checks the optimization to remove the G_TRUNC if we can determine it's redundant.
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---
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name: icmp_trunc_sextload
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $x0
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; CHECK-LABEL: name: icmp_trunc_sextload
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; CHECK: liveins: $x0
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; CHECK: %v:_(p0) = COPY $x0
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; CHECK: %load:_(s64) = G_SEXTLOAD %v(p0) :: (load 4)
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; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
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; CHECK: %cmp:_(s1) = G_ICMP intpred(ne), %load(s64), [[C]]
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; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT %cmp(s1)
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; CHECK: $w0 = COPY [[ANYEXT]](s32)
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; CHECK: RET_ReallyLR implicit $w0
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%v:_(p0) = COPY $x0
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%load:_(s64) = G_SEXTLOAD %v:_(p0) :: (load 4)
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%trunc:_(s32) = G_TRUNC %load(s64)
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%zero:_(s32) = G_CONSTANT i32 0
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%cmp:_(s1) = G_ICMP intpred(ne), %trunc(s32), %zero
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%5:_(s32) = G_ANYEXT %cmp
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$w0 = COPY %5(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: icmp_trunc_sextload_eq
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $x0
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; CHECK-LABEL: name: icmp_trunc_sextload_eq
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; CHECK: liveins: $x0
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; CHECK: %v:_(p0) = COPY $x0
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; CHECK: %load:_(s64) = G_SEXTLOAD %v(p0) :: (load 4)
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; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
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; CHECK: %cmp:_(s1) = G_ICMP intpred(eq), %load(s64), [[C]]
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; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT %cmp(s1)
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; CHECK: $w0 = COPY [[ANYEXT]](s32)
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; CHECK: RET_ReallyLR implicit $w0
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%v:_(p0) = COPY $x0
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%load:_(s64) = G_SEXTLOAD %v:_(p0) :: (load 4)
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%trunc:_(s32) = G_TRUNC %load(s64)
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%zero:_(s32) = G_CONSTANT i32 0
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%cmp:_(s1) = G_ICMP intpred(eq), %trunc(s32), %zero
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%5:_(s32) = G_ANYEXT %cmp
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$w0 = COPY %5(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: icmp_trunc_sextload_wrongpred
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $x0
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; CHECK-LABEL: name: icmp_trunc_sextload_wrongpred
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; CHECK: liveins: $x0
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; CHECK: %v:_(p0) = COPY $x0
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; CHECK: %load:_(s64) = G_SEXTLOAD %v(p0) :: (load 4)
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; CHECK: %trunc:_(s32) = G_TRUNC %load(s64)
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; CHECK: %zero:_(s32) = G_CONSTANT i32 0
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; CHECK: %cmp:_(s1) = G_ICMP intpred(slt), %trunc(s32), %zero
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; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT %cmp(s1)
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; CHECK: $w0 = COPY [[ANYEXT]](s32)
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; CHECK: RET_ReallyLR implicit $w0
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%v:_(p0) = COPY $x0
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%load:_(s64) = G_SEXTLOAD %v:_(p0) :: (load 4)
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%trunc:_(s32) = G_TRUNC %load(s64)
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%zero:_(s32) = G_CONSTANT i32 0
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%cmp:_(s1) = G_ICMP intpred(slt), %trunc(s32), %zero
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%5:_(s32) = G_ANYEXT %cmp
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$w0 = COPY %5(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: icmp_trunc_sextload_extend_mismatch
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $x0
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; CHECK-LABEL: name: icmp_trunc_sextload_extend_mismatch
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; CHECK: liveins: $x0
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; CHECK: %v:_(p0) = COPY $x0
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; CHECK: %load:_(s64) = G_SEXTLOAD %v(p0) :: (load 4)
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; CHECK: %trunc:_(s16) = G_TRUNC %load(s64)
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; CHECK: %zero:_(s16) = G_CONSTANT i16 0
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; CHECK: %cmp:_(s1) = G_ICMP intpred(ne), %trunc(s16), %zero
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; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT %cmp(s1)
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; CHECK: $w0 = COPY [[ANYEXT]](s32)
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; CHECK: RET_ReallyLR implicit $w0
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%v:_(p0) = COPY $x0
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%load:_(s64) = G_SEXTLOAD %v:_(p0) :: (load 4)
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%trunc:_(s16) = G_TRUNC %load(s64)
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%zero:_(s16) = G_CONSTANT i16 0
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%cmp:_(s1) = G_ICMP intpred(ne), %trunc(s16), %zero
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%5:_(s32) = G_ANYEXT %cmp
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$w0 = COPY %5(s32)
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RET_ReallyLR implicit $w0
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...
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