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Fixed CodeGen/captured-statements-nested.c test 

llvm-svn: 212024
This commit is contained in:
Alexey Bataev 2014-06-30 08:17:11 +00:00
parent 0091a0758b
commit be5af7b9c7
1 changed files with 23 additions and 26 deletions
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49
clang/test/CodeGen/captured-statements-nested.c
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@ -1,20 +1,19 @@
// RUN: %clang_cc1 -fblocks -emit-llvm %s -o %t
// RUN: FileCheck %s -input-file=%t -check-prefix=CHECK1
// RUN: FileCheck %s -input-file=%t -check-prefix=CHECK2
// REQUIRES:disabled
struct A {
int a;
long a;
float b;
char c;
};
void test_nest_captured_stmt(int param, int size, int param_arr[size]) {
void test_nest_captured_stmt(int param, long size, int param_arr[size]) {
int w;
int arr[param][size];
// CHECK1: %struct.anon{{.*}} = type { i32*, i32*, i32*, i32**, i32* }
// CHECK1: %struct.anon{{.*}} = type { i32*, i32*, i32**, i32*, i32*, i32**, i32* }
// CHECK1: [[T:%struct.anon.*]] = type { i32*, i32*, %struct.A*, i32**, i32*, i32*, i32**, i32* }
// CHECK1: %struct.anon{{.*}} = type { i32*, i32*, i{{.+}}*, i32**, i32* }
// CHECK1: %struct.anon{{.*}} = type { i32*, i32*, i32**, i32*, i{{.+}}*, i32**, i32* }
// CHECK1: [[T:%struct.anon.*]] = type { i32*, i32*, %struct.A*, i32**, i32*, i{{.+}}*, i32**, i32* }
#pragma clang __debug captured
{
int x;
@ -36,7 +35,7 @@ void test_nest_captured_stmt(int param, int size, int param_arr[size]) {
// CHECK1: getelementptr inbounds [[T]]* {{.*}}, i32 0, i32 2
// CHECK1-NEXT: load %struct.A**
// CHECK1-NEXT: getelementptr inbounds %struct.A*
// CHECK1-NEXT: store i32 1
// CHECK1-NEXT: store i{{.+}} 1
//
// CHECK1: getelementptr inbounds [[T]]* {{.*}}, i32 0, i32 1
// CHECK1-NEXT: load i32**
@ -64,28 +63,26 @@ void test_nest_captured_stmt(int param, int size, int param_arr[size]) {
// CHECK1-NEXT: getelementptr inbounds %struct.A*
// CHECK1-NEXT: store i8 99
//
// CHECK1: [[SIZE_ADDR_REF:%.*]] = getelementptr inbounds [[T]]* {{.*}}, i32 0, i32 5
// CHECK1-DAG: [[SIZE_ADDR:%.*]] = load i32** [[SIZE_ADDR_REF]]
// CHECK1-DAG: [[SIZE:%.*]] = load i32* [[SIZE_ADDR]]
// CHECK1-DAG: [[SIZE_MINUS_1:%.*]] = sub nsw i32 [[SIZE]], 1
// CHECK1-DAG: [[PARAM_ARR_IDX:%.*]] = {{.*}} [[SIZE_MINUS_1]]
// CHECK1-DAG: [[PARAM_ARR_ADDR_REF:%.*]] = getelementptr inbounds [[T]]* {{.*}}, i32 0, i32 6
// CHECK1-DAG: [[PARAM_ARR_ADDR:%.*]] = load i32*** [[PARAM_ARR_ADDR_REF]]
// CHECK1-DAG: [[PARAM_ARR:%.*]] = load i32** [[PARAM_ARR_ADDR]]
// CHECK1-DAG: [[PARAM_ARR_SIZE_MINUS_1_ADDR:%.*]] = getelementptr inbounds i32* [[PARAM_ARR]], i{{.*}} [[PARAM_ARR_IDX]]
// CHECK1: store i32 2, i32* [[PARAM_ARR_SIZE_MINUS_1_ADDR]]
// CHECK1: [[SIZE_ADDR_REF:%.*]] = getelementptr inbounds [[T]]* {{.*}}, i{{.+}} 0, i{{.+}} 5
// CHECK1-DAG: [[SIZE_ADDR:%.*]] = load i{{.+}}** [[SIZE_ADDR_REF]]
// CHECK1-DAG: [[SIZE:%.*]] = load i{{.+}}* [[SIZE_ADDR]]
// CHECK1-DAG: [[PARAM_ARR_IDX:%.*]] = sub nsw i{{.+}} [[SIZE]], 1
// CHECK1-DAG: [[PARAM_ARR_ADDR_REF:%.*]] = getelementptr inbounds [[T]]* {{.*}}, i{{.+}} 0, i{{.+}} 6
// CHECK1-DAG: [[PARAM_ARR_ADDR:%.*]] = load i{{.+}}*** [[PARAM_ARR_ADDR_REF]]
// CHECK1-DAG: [[PARAM_ARR:%.*]] = load i{{.+}}** [[PARAM_ARR_ADDR]]
// CHECK1-DAG: [[PARAM_ARR_SIZE_MINUS_1_ADDR:%.*]] = getelementptr inbounds i{{.+}}* [[PARAM_ARR]], i{{.*}} [[PARAM_ARR_IDX]]
// CHECK1: store i{{.+}} 2, i{{.+}}* [[PARAM_ARR_SIZE_MINUS_1_ADDR]]
//
// CHECK1: [[Z_ADDR_REF:%.*]] = getelementptr inbounds [[T]]* {{.*}}, i32 0, i32 2
// CHECK1: [[Z_ADDR_REF:%.*]] = getelementptr inbounds [[T]]* {{.*}}, i{{.+}} 0, i{{.+}} 2
// CHECK1-DAG: [[Z_ADDR:%.*]] = load %struct.A** [[Z_ADDR_REF]]
// CHECK1-DAG: [[Z_A_ADDR:%.*]] = getelementptr inbounds %struct.A* [[Z_ADDR]], i32 0, i32 0
// CHECK1-DAG: [[Z_A:%.*]] = load i32* [[Z_A_ADDR]]
// CHECK1-DAG: [[ARR_IDX_2:%.*]] = {{.*}} [[Z_A]]
// CHECK1-DAG: [[ARR_ADDR_REF:%.*]] = getelementptr inbounds [[T]]* {{.*}}, i32 0, i32 7
// CHECK1-DAG: [[ARR_ADDR:%.*]] = load i32** [[ARR_ADDR_REF]]
// CHECK1-DAG: [[Z_A_ADDR:%.*]] = getelementptr inbounds %struct.A* [[Z_ADDR]], i{{.+}} 0, i{{.+}} 0
// CHECK1-DAG: [[ARR_IDX_2:%.*]] = load i{{.+}}* [[Z_A_ADDR]]
// CHECK1-DAG: [[ARR_ADDR_REF:%.*]] = getelementptr inbounds [[T]]* {{.*}}, i{{.+}} 0, i{{.+}} 7
// CHECK1-DAG: [[ARR_ADDR:%.*]] = load i{{.+}}** [[ARR_ADDR_REF]]
// CHECK1-DAG: [[ARR_IDX_1:%.*]] = mul {{.*}} 10
// CHECK1-DAG: [[ARR_10_ADDR:%.*]] = getelementptr inbounds i32* [[ARR_ADDR]], i{{.*}} [[ARR_IDX_1]]
// CHECK1-DAG: [[ARR_10_Z_A_ADDR:%.*]] = getelementptr inbounds i32* [[ARR_10_ADDR]], i{{.*}} [[ARR_IDX_2]]
// CHECK1: store i32 12, i32* [[ARR_10_Z_A_ADDR]]
// CHECK1-DAG: [[ARR_10_ADDR:%.*]] = getelementptr inbounds i{{.+}}* [[ARR_ADDR]], i{{.*}} [[ARR_IDX_1]]
// CHECK1-DAG: [[ARR_10_Z_A_ADDR:%.*]] = getelementptr inbounds i{{.+}}* [[ARR_10_ADDR]], i{{.*}} [[ARR_IDX_2]]
// CHECK1: store i{{.+}} 12, i{{.+}}* [[ARR_10_Z_A_ADDR]]
}
}
}