forked from OSchip/llvm-project
[AMDGPU] gfx11 VOPC instructions
Supports encoding existing instrutions on gfx11 and MC support for the new VOPC dpp instructions. Patch 19/N for upstreaming of AMDGPU gfx11 architecture Depends on D126978 Reviewed By: rampitec, #amdgpu Differential Revision: https://reviews.llvm.org/D126989
This commit is contained in:
Joe Nash
parent
25c8a061c5
commit
be1082c6d5
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@ -1762,9 +1762,24 @@ public:
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AMDGPUOperand::Ptr defaultBoundCtrl() const;
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AMDGPUOperand::Ptr defaultFI() const;
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void cvtDPP(MCInst &Inst, const OperandVector &Operands, bool IsDPP8 = false);
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void cvtDPP8(MCInst &Inst, const OperandVector &Operands) { cvtDPP(Inst, Operands, true); }
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void cvtVOP3DPP(MCInst &Inst, const OperandVector &Operands, bool IsDPP8 = false);
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void cvtVOP3DPP8(MCInst &Inst, const OperandVector &Operands) { cvtVOP3DPP(Inst, Operands, true); }
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void cvtDPP8(MCInst &Inst, const OperandVector &Operands) {
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cvtDPP(Inst, Operands, true);
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}
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void cvtVOPCNoDstDPP(MCInst &Inst, const OperandVector &Operands,
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bool IsDPP8 = false);
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void cvtVOPCNoDstDPP8(MCInst &Inst, const OperandVector &Operands) {
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cvtVOPCNoDstDPP(Inst, Operands, true);
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}
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void cvtVOP3DPP(MCInst &Inst, const OperandVector &Operands,
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bool IsDPP8 = false);
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void cvtVOP3DPP8(MCInst &Inst, const OperandVector &Operands) {
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cvtVOP3DPP(Inst, Operands, true);
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}
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void cvtVOPC64NoDstDPP(MCInst &Inst, const OperandVector &Operands,
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bool IsDPP8 = false);
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void cvtVOPC64NoDstDPP8(MCInst &Inst, const OperandVector &Operands) {
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cvtVOPC64NoDstDPP(Inst, Operands, true);
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}
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OperandMatchResultTy parseSDWASel(OperandVector &Operands, StringRef Prefix,
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AMDGPUOperand::ImmTy Type);
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@ -8594,6 +8609,14 @@ AMDGPUOperand::Ptr AMDGPUAsmParser::defaultFI() const {
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return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyDppFi);
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}
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// Add dummy $old operand
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void AMDGPUAsmParser::cvtVOPC64NoDstDPP(MCInst &Inst,
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const OperandVector &Operands,
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bool IsDPP8) {
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Inst.addOperand(MCOperand::createReg(0));
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cvtVOP3DPP(Inst, Operands, IsDPP8);
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}
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void AMDGPUAsmParser::cvtVOP3DPP(MCInst &Inst, const OperandVector &Operands, bool IsDPP8) {
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OptionalImmIndexMap OptionalIdx;
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unsigned Opc = Inst.getOpcode();
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@ -8660,6 +8683,14 @@ void AMDGPUAsmParser::cvtVOP3DPP(MCInst &Inst, const OperandVector &Operands, bo
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}
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}
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// Add dummy $old operand
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void AMDGPUAsmParser::cvtVOPCNoDstDPP(MCInst &Inst,
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const OperandVector &Operands,
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bool IsDPP8) {
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Inst.addOperand(MCOperand::createReg(0));
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cvtDPP(Inst, Operands, IsDPP8);
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}
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void AMDGPUAsmParser::cvtDPP(MCInst &Inst, const OperandVector &Operands, bool IsDPP8) {
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OptionalImmIndexMap OptionalIdx;
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@ -444,6 +444,8 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
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if (Res) {
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if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3P)
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convertVOP3PDPPInst(MI);
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else if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOPC)
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convertVOPCDPPInst(MI);
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break;
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}
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}
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@ -479,8 +481,11 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
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if (Res) break;
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Res = tryDecodeInst(DecoderTableDPPGFX1164, MI, QW, Address);
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if (Res)
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if (Res) {
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if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOPC)
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convertVOPCDPPInst(MI);
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break;
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}
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Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address);
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if (Res) { IsSDWA = true; break; }
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@ -734,6 +739,8 @@ DecodeStatus AMDGPUDisassembler::convertDPP8Inst(MCInst &MI) const {
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unsigned DescNumOps = MCII->get(Opc).getNumOperands();
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if (MCII->get(Opc).TSFlags & SIInstrFlags::VOP3P) {
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convertVOP3PDPPInst(MI);
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} else if (MCII->get(Opc).TSFlags & SIInstrFlags::VOPC) {
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convertVOPCDPPInst(MI);
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} else {
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// Insert dummy unused src modifiers.
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if (MI.getNumOperands() < DescNumOps &&
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@ -937,6 +944,27 @@ DecodeStatus AMDGPUDisassembler::convertVOP3PDPPInst(MCInst &MI) const {
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return MCDisassembler::Success;
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}
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// Create dummy old operand and insert optional operands
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DecodeStatus AMDGPUDisassembler::convertVOPCDPPInst(MCInst &MI) const {
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unsigned Opc = MI.getOpcode();
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unsigned DescNumOps = MCII->get(Opc).getNumOperands();
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if (MI.getNumOperands() < DescNumOps &&
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AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::old) != -1)
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insertNamedMCOperand(MI, MCOperand::createReg(0), AMDGPU::OpName::old);
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if (MI.getNumOperands() < DescNumOps &&
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AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers) != -1)
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insertNamedMCOperand(MI, MCOperand::createImm(0),
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AMDGPU::OpName::src0_modifiers);
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if (MI.getNumOperands() < DescNumOps &&
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AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers) != -1)
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insertNamedMCOperand(MI, MCOperand::createImm(0),
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AMDGPU::OpName::src1_modifiers);
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return MCDisassembler::Success;
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}
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DecodeStatus AMDGPUDisassembler::convertFMAanyK(MCInst &MI,
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int ImmLitIdx) const {
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assert(HasLiteral && "Should have decoded a literal");
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@ -163,6 +163,7 @@ public:
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DecodeStatus convertDPP8Inst(MCInst &MI) const;
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DecodeStatus convertMIMGInst(MCInst &MI) const;
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DecodeStatus convertVOP3PDPPInst(MCInst &MI) const;
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DecodeStatus convertVOPCDPPInst(MCInst &MI) const;
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MCOperand decodeOperand_VGPR_32(unsigned Val) const;
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MCOperand decodeOperand_VRegOrLds_32(unsigned Val) const;
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@ -382,7 +382,7 @@ void AMDGPUInstPrinter::printVOPDst(const MCInst *MI, unsigned OpNo,
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O << " ";
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}
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printOperand(MI, OpNo, STI, O);
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printRegularOperand(MI, OpNo, STI, O);
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// Print default vcc/vcc_lo operand.
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switch (Opcode) {
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@ -421,7 +421,7 @@ void AMDGPUInstPrinter::printVINTRPDst(const MCInst *MI, unsigned OpNo,
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else
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O << "_e32 ";
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printOperand(MI, OpNo, STI, O);
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printRegularOperand(MI, OpNo, STI, O);
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}
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void AMDGPUInstPrinter::printImmediateInt16(uint32_t Imm,
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@ -625,17 +625,41 @@ void AMDGPUInstPrinter::printWaitEXP(const MCInst *MI, unsigned OpNo,
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}
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}
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bool AMDGPUInstPrinter::needsImpliedVcc(const MCInstrDesc &Desc,
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unsigned OpNo) const {
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return OpNo == 1 && (Desc.TSFlags & SIInstrFlags::DPP) &&
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(Desc.TSFlags & SIInstrFlags::VOPC) &&
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(Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC) ||
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Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC_LO));
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}
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// Print default vcc/vcc_lo operand of VOPC.
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void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI,
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raw_ostream &O) {
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// Print default vcc/vcc_lo operand of VOPC.
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const MCInstrDesc &Desc = MII.get(MI->getOpcode());
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if (OpNo == 0 && (Desc.TSFlags & SIInstrFlags::VOPC) &&
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unsigned Opc = MI->getOpcode();
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const MCInstrDesc &Desc = MII.get(Opc);
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int ModIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers);
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// 0, 1 and 2 are the first printed operands in different cases
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// If there are printed modifiers, printOperandAndFPInputMods or
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// printOperandAndIntInputMods will be called instead
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if ((OpNo == 0 ||
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(OpNo == 1 && (Desc.TSFlags & SIInstrFlags::DPP)) ||
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(OpNo == 2 && (Desc.TSFlags & SIInstrFlags::DPP) && ModIdx != -1)) &&
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(Desc.TSFlags & SIInstrFlags::VOPC) &&
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(Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC) ||
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Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC_LO)))
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printDefaultVccOperand(true, STI, O);
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printRegularOperand(MI, OpNo, STI, O);
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}
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// Print operands after vcc or modifier handling.
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void AMDGPUInstPrinter::printRegularOperand(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI,
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raw_ostream &O) {
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const MCInstrDesc &Desc = MII.get(MI->getOpcode());
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if (OpNo >= MI->getNumOperands()) {
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O << "/*Missing OP" << OpNo << "*/";
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return;
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@ -788,6 +812,10 @@ void AMDGPUInstPrinter::printOperandAndFPInputMods(const MCInst *MI,
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unsigned OpNo,
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const MCSubtargetInfo &STI,
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raw_ostream &O) {
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const MCInstrDesc &Desc = MII.get(MI->getOpcode());
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if (needsImpliedVcc(Desc, OpNo))
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printDefaultVccOperand(true, STI, O);
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unsigned InputModifiers = MI->getOperand(OpNo).getImm();
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// Use 'neg(...)' instead of '-' to avoid ambiguity.
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@ -810,7 +838,7 @@ void AMDGPUInstPrinter::printOperandAndFPInputMods(const MCInst *MI,
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if (InputModifiers & SISrcMods::ABS)
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O << '|';
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printOperand(MI, OpNo + 1, STI, O);
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printRegularOperand(MI, OpNo + 1, STI, O);
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if (InputModifiers & SISrcMods::ABS)
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O << '|';
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@ -823,10 +851,14 @@ void AMDGPUInstPrinter::printOperandAndIntInputMods(const MCInst *MI,
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unsigned OpNo,
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const MCSubtargetInfo &STI,
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raw_ostream &O) {
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const MCInstrDesc &Desc = MII.get(MI->getOpcode());
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if (needsImpliedVcc(Desc, OpNo))
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printDefaultVccOperand(true, STI, O);
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unsigned InputModifiers = MI->getOperand(OpNo).getImm();
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if (InputModifiers & SISrcMods::SEXT)
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O << "sext(";
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printOperand(MI, OpNo + 1, STI, O);
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printRegularOperand(MI, OpNo + 1, STI, O);
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if (InputModifiers & SISrcMods::SEXT)
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O << ')';
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@ -1259,9 +1291,9 @@ void AMDGPUInstPrinter::printVGPRIndexMode(const MCInst *MI, unsigned OpNo,
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void AMDGPUInstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI,
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raw_ostream &O) {
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printOperand(MI, OpNo, STI, O);
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printRegularOperand(MI, OpNo, STI, O);
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O << ", ";
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printOperand(MI, OpNo + 1, STI, O);
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printRegularOperand(MI, OpNo + 1, STI, O);
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}
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void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo,
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@ -15,6 +15,7 @@
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#include "llvm/MC/MCInstPrinter.h"
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namespace llvm {
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class MCInstrDesc;
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class AMDGPUInstPrinter : public MCInstPrinter {
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public:
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@ -117,6 +118,8 @@ private:
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raw_ostream &O);
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void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
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raw_ostream &O);
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void printRegularOperand(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI, raw_ostream &O);
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void printOperand(const MCInst *MI, uint64_t /*Address*/, unsigned OpNum,
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const MCSubtargetInfo &STI, raw_ostream &O) {
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printOperand(MI, OpNum, STI, O);
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@ -173,6 +176,7 @@ private:
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raw_ostream &O);
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void printABID(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
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raw_ostream &O);
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bool needsImpliedVcc(const MCInstrDesc &Desc, unsigned OpNo) const;
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void printDefaultVccOperand(bool FirstOperand, const MCSubtargetInfo &STI,
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raw_ostream &O);
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void printWaitVDST(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
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@ -49,12 +49,36 @@ class VOPC_SDWA9e <bits<8> op, VOPProfile P> : VOP_SDWA9Be <P> {
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// an explicit $dst.
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class VOPC_Profile<list<SchedReadWrite> sched, ValueType vt0, ValueType vt1 = vt0> :
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VOPProfile <[i1, vt0, vt1, untyped]> {
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// We want to exclude instructions with 64bit operands
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let HasExtDPP = getHasVOP3DPP<DstVT, Src0VT, Src1VT, Src2VT>.ret;
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let Asm32 = "$src0, $src1";
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let AsmDPP = !if (HasModifiers,
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"$src0_modifiers, $src1_modifiers "
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"$dpp_ctrl$row_mask$bank_mask$bound_ctrl",
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"$src0, $src1 $dpp_ctrl$row_mask$bank_mask$bound_ctrl");
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let AsmDPP8 = "$src0, $src1 $dpp8$fi";
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let AsmDPP16 = AsmDPP#"$fi";
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let InsDPP = getInsDPP<VOPDstOperand<Src0DPP>, Src0DPP, Src1DPP, Src2DPP,
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NumSrcArgs, HasModifiers, Src0ModDPP, Src1ModDPP,
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Src2ModDPP>.ret;
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let InsDPP16 = getInsDPP16<VOPDstOperand<Src0DPP>, Src0DPP, Src1DPP, Src2DPP,
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NumSrcArgs, HasModifiers, Src0ModDPP, Src1ModDPP,
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Src2ModDPP>.ret;
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let InsDPP8 = getInsDPP8<VOPDstOperand<Src0DPP>, Src0DPP, Src1DPP, Src2DPP,
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NumSrcArgs, HasModifiers, Src0ModDPP, Src1ModDPP,
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Src2ModDPP>.ret;
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// The destination for 32-bit encoding is implicit.
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let HasDst32 = 0;
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// VOPC disallows dst_sel and dst_unused as they have no effect on destination
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let EmitDstSel = 0;
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let Outs64 = (outs VOPDstS64orS32:$sdst);
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let OutsVOP3DPP = Outs64;
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let OutsVOP3DPP8 = Outs64;
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let InsVOP3DPP = getInsVOP3DPP<InsVOP3Base, Src0VOP3DPP, NumSrcArgs>.ret;
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let InsVOP3DPP16 = getInsVOP3DPP16<InsVOP3Base, Src0VOP3DPP, NumSrcArgs>.ret;
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let InsVOP3DPP8 = getInsVOP3DPP8<InsVOP3Base, Src0VOP3DPP, NumSrcArgs>.ret;
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list<SchedReadWrite> Schedule = sched;
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}
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@ -62,12 +86,15 @@ class VOPC_NoSdst_Profile<list<SchedReadWrite> sched, ValueType vt0,
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ValueType vt1 = vt0> :
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VOPC_Profile<sched, vt0, vt1> {
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let Outs64 = (outs );
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let OutsVOP3DPP = Outs64;
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let OutsVOP3DPP8 = Outs64;
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let OutsSDWA = (outs );
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let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0,
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Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1,
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src0_sel:$src0_sel, src1_sel:$src1_sel);
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let Asm64 = !if(isFloatType<Src0VT>.ret, "$src0_modifiers, $src1_modifiers$clamp",
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"$src0, $src1");
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let AsmVOP3DPPBase = Asm64;
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let AsmSDWA9 = "$src0_modifiers, $src1_modifiers $src0_sel $src1_sel";
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let EmitDst = 0;
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}
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@ -100,8 +127,8 @@ class VOPC_Pseudo <string opName, VOPC_Profile P, list<dag> pattern=[],
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VOPProfile Pfl = P;
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}
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class VOPC_Real <VOPC_Pseudo ps, int EncodingFamily> :
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InstSI <ps.OutOperandList, ps.InOperandList, ps.PseudoInstr # " " # ps.AsmOperands, []>,
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class VOPC_Real <VOPC_Pseudo ps, int EncodingFamily, string asm_name = ps.PseudoInstr> :
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InstSI <ps.OutOperandList, ps.InOperandList, asm_name # " " # ps.AsmOperands, []>,
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SIMCInstr <ps.PseudoInstr, EncodingFamily> {
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let VALU = 1;
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@ -133,8 +160,9 @@ class VOPC_SDWA_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[]> :
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// This class is used only with VOPC instructions. Use $sdst for out operand
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class VOPCInstAlias <VOP3_Pseudo ps, Instruction inst,
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string Asm32 = ps.Pfl.Asm32, VOPProfile p = ps.Pfl> :
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InstAlias <ps.OpName#" "#Asm32, (inst)>, PredicateControl {
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string Asm32 = ps.Pfl.Asm32, string real_name = ps.OpName,
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VOPProfile p = ps.Pfl> :
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InstAlias <real_name#" "#Asm32, (inst)>, PredicateControl {
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field bit isCompare;
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field bit isCommutable;
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@ -167,27 +195,32 @@ class VOPCInstAlias <VOP3_Pseudo ps, Instruction inst,
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let SubtargetPredicate = AssemblerPredicate;
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}
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multiclass VOPCInstAliases <string OpName, string Arch> {
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def : VOPCInstAlias <!cast<VOP3_Pseudo>(OpName#"_e64"),
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!cast<Instruction>(OpName#"_e32_"#Arch)>;
|
||||
multiclass VOPCInstAliases <string old_name, string Arch, string real_name = old_name> {
|
||||
def : VOPCInstAlias <!cast<VOP3_Pseudo>(old_name#"_e64"),
|
||||
!cast<Instruction>(real_name#"_e32_"#Arch),
|
||||
!cast<VOP3_Pseudo>(old_name#"_e64").Pfl.Asm32,
|
||||
real_name>;
|
||||
let WaveSizePredicate = isWave32 in {
|
||||
def : VOPCInstAlias <!cast<VOP3_Pseudo>(OpName#"_e64"),
|
||||
!cast<Instruction>(OpName#"_e32_"#Arch),
|
||||
"vcc_lo, "#!cast<VOP3_Pseudo>(OpName#"_e64").Pfl.Asm32>;
|
||||
def : VOPCInstAlias <!cast<VOP3_Pseudo>(old_name#"_e64"),
|
||||
!cast<Instruction>(real_name#"_e32_"#Arch),
|
||||
"vcc_lo, "#!cast<VOP3_Pseudo>(old_name#"_e64").Pfl.Asm32,
|
||||
real_name>;
|
||||
}
|
||||
let WaveSizePredicate = isWave64 in {
|
||||
def : VOPCInstAlias <!cast<VOP3_Pseudo>(OpName#"_e64"),
|
||||
!cast<Instruction>(OpName#"_e32_"#Arch),
|
||||
"vcc, "#!cast<VOP3_Pseudo>(OpName#"_e64").Pfl.Asm32>;
|
||||
def : VOPCInstAlias <!cast<VOP3_Pseudo>(old_name#"_e64"),
|
||||
!cast<Instruction>(real_name#"_e32_"#Arch),
|
||||
"vcc, "#!cast<VOP3_Pseudo>(old_name#"_e64").Pfl.Asm32,
|
||||
real_name>;
|
||||
}
|
||||
}
|
||||
|
||||
multiclass VOPCXInstAliases <string OpName, string Arch> {
|
||||
def : VOPCInstAlias <!cast<VOP3_Pseudo>(OpName#"_e64"),
|
||||
!cast<Instruction>(OpName#"_e32_"#Arch)>;
|
||||
multiclass VOPCXInstAliases <string old_name, string Arch, string real_name = old_name> {
|
||||
def : VOPCInstAlias <!cast<VOP3_Pseudo>(old_name#"_e64"),
|
||||
!cast<Instruction>(real_name#"_e32_"#Arch),
|
||||
!cast<VOP3_Pseudo>(old_name#"_e64").Pfl.Asm32,
|
||||
real_name>;
|
||||
}
|
||||
|
||||
|
||||
class getVOPCPat64 <SDPatternOperator cond, VOPProfile P> : LetDummies {
|
||||
list<dag> ret = !if(P.HasModifiers,
|
||||
[(set i1:$sdst,
|
||||
|
|
@ -244,6 +277,26 @@ multiclass VOPC_Pseudos <string opName,
|
|||
let isConvergent = DefExec;
|
||||
let isCompare = 1;
|
||||
}
|
||||
|
||||
let SubtargetPredicate = isGFX11Plus in {
|
||||
if P.HasExtDPP then
|
||||
def _e32_dpp : VOP_DPP_Pseudo<opName, P> {
|
||||
let Defs = !if(DefExec, [VCC, EXEC], [VCC]);
|
||||
let SchedRW = P.Schedule;
|
||||
let isConvergent = DefExec;
|
||||
let isCompare = 1;
|
||||
let VOPC = 1;
|
||||
let Constraints = "";
|
||||
}
|
||||
if P.HasExtVOP3DPP then
|
||||
def _e64_dpp : VOP3_DPP_Pseudo<opName, P> {
|
||||
let Defs = !if(DefExec, [EXEC], []);
|
||||
let SchedRW = P.Schedule;
|
||||
let isCompare = 1;
|
||||
let Constraints = !if(P.NumSrcArgs, P.TieRegDPP # " = $sdst", "");
|
||||
}
|
||||
} // end SubtargetPredicate = isGFX11Plus
|
||||
|
||||
}
|
||||
|
||||
let SubtargetPredicate = HasSdstCMPX in {
|
||||
|
|
@ -286,6 +339,25 @@ multiclass VOPCX_Pseudos <string opName,
|
|||
let isCompare = 1;
|
||||
let SubtargetPredicate = HasNoSdstCMPX;
|
||||
}
|
||||
|
||||
let SubtargetPredicate = isGFX11Plus in {
|
||||
if P.HasExtDPP then
|
||||
def _nosdst_e32_dpp : VOP_DPP_Pseudo<opName#"_nosdst", P_NoSDst> {
|
||||
let Defs = [EXEC];
|
||||
let SchedRW = P_NoSDst.Schedule;
|
||||
let isConvergent = 1;
|
||||
let isCompare = 1;
|
||||
let VOPC = 1;
|
||||
let Constraints = "";
|
||||
}
|
||||
if P.HasExtVOP3DPP then
|
||||
def _nosdst_e64_dpp : VOP3_DPP_Pseudo<opName#"_nosdst", P_NoSDst> {
|
||||
let Defs = [EXEC];
|
||||
let SchedRW = P_NoSDst.Schedule;
|
||||
let isCompare = 1;
|
||||
let Constraints = "";
|
||||
}
|
||||
} // end SubtargetPredicate = isGFX11Plus
|
||||
}
|
||||
} // End SubtargetPredicate = HasSdstCMPX
|
||||
|
||||
|
|
@ -637,8 +709,18 @@ defm V_CMPX_T_U64 : VOPCX_I64 <"v_cmpx_t_u64">;
|
|||
|
||||
class VOPC_Class_Profile<list<SchedReadWrite> sched, ValueType vt> :
|
||||
VOPC_Profile<sched, vt, i32> {
|
||||
let AsmDPP = "$src0_modifiers, $src1 $dpp_ctrl$row_mask$bank_mask$bound_ctrl";
|
||||
let AsmDPP16 = AsmDPP#"$fi";
|
||||
let InsDPP = (ins VGPR_32:$old, FPVRegInputMods:$src0_modifiers, VGPR_32:$src0, VGPR_32:$src1, dpp_ctrl:$dpp_ctrl, row_mask:$row_mask, bank_mask:$bank_mask, bound_ctrl:$bound_ctrl);
|
||||
let InsDPP16 = !con(InsDPP, (ins FI:$fi));
|
||||
// DPP8 forbids modifiers and can inherit from VOPC_Profile
|
||||
|
||||
let Ins64 = (ins Src0Mod:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
|
||||
dag InsPartVOP3DPP = (ins Src0Mod:$src0_modifiers, VGPRSrc_32:$src0, VGPRSrc_32:$src1);
|
||||
let InsVOP3Base = !con(InsPartVOP3DPP, !if(HasOpSel, (ins op_sel0:$op_sel),
|
||||
(ins)));
|
||||
let Asm64 = "$sdst, $src0_modifiers, $src1";
|
||||
let AsmVOP3DPPBase = Asm64;
|
||||
|
||||
let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0,
|
||||
Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1,
|
||||
|
|
@ -658,6 +740,7 @@ class VOPC_Class_NoSdst_Profile<list<SchedReadWrite> sched, ValueType vt> :
|
|||
Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1,
|
||||
src0_sel:$src0_sel, src1_sel:$src1_sel);
|
||||
let Asm64 = "$src0_modifiers, $src1";
|
||||
let AsmVOP3DPPBase = Asm64;
|
||||
let AsmSDWA9 = "$src0_modifiers, $src1_modifiers $src0_sel $src1_sel";
|
||||
let EmitDst = 0;
|
||||
}
|
||||
|
|
@ -695,6 +778,24 @@ multiclass VOPC_Class_Pseudos <string opName, VOPC_Profile p, bit DefExec,
|
|||
let SchedRW = p.Schedule;
|
||||
let isConvergent = DefExec;
|
||||
}
|
||||
|
||||
let SubtargetPredicate = isGFX11Plus in {
|
||||
if p.HasExtDPP then
|
||||
def _e32_dpp : VOP_DPP_Pseudo<opName, p> {
|
||||
let Defs = !if(DefExec, !if(DefVcc, [VCC, EXEC], [EXEC]),
|
||||
!if(DefVcc, [VCC], []));
|
||||
let SchedRW = p.Schedule;
|
||||
let isConvergent = DefExec;
|
||||
let VOPC = 1;
|
||||
let Constraints = "";
|
||||
}
|
||||
if p.HasExtVOP3DPP then
|
||||
def _e64_dpp : VOP3_DPP_Pseudo<opName, p> {
|
||||
let Defs = !if(DefExec, [EXEC], []);
|
||||
let SchedRW = p.Schedule;
|
||||
let Constraints = !if(p.NumSrcArgs, p.TieRegDPP # " = $sdst", "");
|
||||
}
|
||||
} // end SubtargetPredicate = isGFX11Plus
|
||||
}
|
||||
|
||||
let SubtargetPredicate = HasSdstCMPX in {
|
||||
|
|
@ -725,6 +826,23 @@ multiclass VOPCX_Class_Pseudos <string opName,
|
|||
let isConvergent = 1;
|
||||
let SubtargetPredicate = HasNoSdstCMPX;
|
||||
}
|
||||
|
||||
let SubtargetPredicate = isGFX11Plus in {
|
||||
if P.HasExtDPP then
|
||||
def _nosdst_e32_dpp : VOP_DPP_Pseudo<opName#"_nosdst", P_NoSDst> {
|
||||
let Defs = [EXEC];
|
||||
let SchedRW = P_NoSDst.Schedule;
|
||||
let isConvergent = 1;
|
||||
let VOPC = 1;
|
||||
let Constraints = "";
|
||||
}
|
||||
if P.HasExtVOP3DPP then
|
||||
def _nosdst_e64_dpp : VOP3_DPP_Pseudo<opName#"_nosdst", P_NoSDst> {
|
||||
let Defs = [EXEC];
|
||||
let SchedRW = P_NoSDst.Schedule;
|
||||
let Constraints = "";
|
||||
}
|
||||
} // end SubtargetPredicate = isGFX11Plus
|
||||
}
|
||||
} // End SubtargetPredicate = HasSdstCMPX
|
||||
|
||||
|
|
@ -882,15 +1000,673 @@ defm : FCMP_Pattern <COND_UGE, V_CMP_NLT_F16_e64, f16>;
|
|||
defm : FCMP_Pattern <COND_ULT, V_CMP_NGE_F16_e64, f16>;
|
||||
defm : FCMP_Pattern <COND_ULE, V_CMP_NGT_F16_e64, f16>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// DPP Encodings
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// VOPC32
|
||||
|
||||
class VOPC_DPPe_Common<bits<8> op> : Enc64 {
|
||||
bits<8> src1;
|
||||
let Inst{16-9} = src1;
|
||||
let Inst{24-17} = op;
|
||||
let Inst{31-25} = 0x3e;
|
||||
}
|
||||
|
||||
class VOPC_DPP_Base<bits<8> op, string OpName, VOPProfile P>
|
||||
: VOP_DPP_Base<OpName, P, P.InsDPP16, " " #P.AsmDPP16>,
|
||||
VOPC_DPPe_Common<op> {
|
||||
bits<2> src0_modifiers;
|
||||
bits<8> src0;
|
||||
bits<2> src1_modifiers;
|
||||
bits<9> dpp_ctrl;
|
||||
bits<1> bound_ctrl;
|
||||
bits<4> bank_mask;
|
||||
bits<4> row_mask;
|
||||
bit fi;
|
||||
|
||||
let Inst{8-0} = 0xfa;
|
||||
|
||||
let Inst{39-32} = !if (P.HasSrc0, src0{7-0}, 0);
|
||||
let Inst{48-40} = dpp_ctrl;
|
||||
let Inst{50} = fi;
|
||||
let Inst{51} = bound_ctrl;
|
||||
let Inst{52} = !if (P.HasSrc0Mods, src0_modifiers{0}, 0); // src0_neg
|
||||
let Inst{53} = !if (P.HasSrc0Mods, src0_modifiers{1}, 0); // src0_abs
|
||||
let Inst{54} = !if (P.HasSrc1Mods, src1_modifiers{0}, 0); // src1_neg
|
||||
let Inst{55} = !if (P.HasSrc1Mods, src1_modifiers{1}, 0); // src1_abs
|
||||
let Inst{59-56} = bank_mask;
|
||||
let Inst{63-60} = row_mask;
|
||||
|
||||
let AsmMatchConverter = "cvtDPP";
|
||||
let VOPC = 1;
|
||||
}
|
||||
|
||||
class VOPC_DPP8_Base<bits<8> op, string OpName, VOPProfile P>
|
||||
: VOP_DPP8_Base<OpName, P, P.InsDPP8, " " #P.AsmDPP8>,
|
||||
VOPC_DPPe_Common<op> {
|
||||
bits<8> src0;
|
||||
bits<24> dpp8;
|
||||
bits<9> fi;
|
||||
|
||||
let Inst{8-0} = fi;
|
||||
|
||||
let Inst{39-32} = !if (P.HasSrc0, src0{7-0}, 0);
|
||||
let Inst{63-40} = dpp8{23-0};
|
||||
|
||||
let AsmMatchConverter = "cvtDPP8";
|
||||
let VOPC = 1;
|
||||
}
|
||||
|
||||
class VOPC_DPP16<bits<8> op, VOP_DPP_Pseudo ps, string opName = ps.OpName>
|
||||
: VOPC_DPP_Base<op, opName, ps.Pfl> {
|
||||
let AssemblerPredicate = HasDPP16;
|
||||
let SubtargetPredicate = HasDPP16;
|
||||
let hasSideEffects = ps.hasSideEffects;
|
||||
let Defs = ps.Defs;
|
||||
let SchedRW = ps.SchedRW;
|
||||
let Uses = ps.Uses;
|
||||
let OtherPredicates = ps.OtherPredicates;
|
||||
let Constraints = ps.Constraints;
|
||||
let AsmMatchConverter = "cvtVOPCNoDstDPP";
|
||||
}
|
||||
|
||||
class VOPC_DPP16_SIMC<bits<8> op, VOP_DPP_Pseudo ps, int subtarget,
|
||||
string opName = ps.OpName>
|
||||
: VOPC_DPP16<op, ps, opName>, SIMCInstr<ps.PseudoInstr, subtarget>;
|
||||
|
||||
class VOPC_DPP8<bits<8> op, VOPC_Pseudo ps, string opName = ps.OpName>
|
||||
: VOPC_DPP8_Base<op, opName, ps.Pfl> {
|
||||
// Note ps is the non-dpp pseudo
|
||||
let hasSideEffects = ps.hasSideEffects;
|
||||
let Defs = ps.Defs;
|
||||
let SchedRW = ps.SchedRW;
|
||||
let Uses = ps.Uses;
|
||||
let OtherPredicates = ps.OtherPredicates;
|
||||
let Constraints = "";
|
||||
let AsmMatchConverter = "cvtVOPCNoDstDPP8";
|
||||
}
|
||||
|
||||
// VOPC64
|
||||
|
||||
class VOPC64_DPP_Base<bits<10> op, string OpName, VOPProfile P>
|
||||
: VOP3_DPP_Base<OpName, P, 1>, VOP3_DPPe_Common<op, P> {
|
||||
bits<8> src0;
|
||||
bits<9> dpp_ctrl;
|
||||
bits<1> bound_ctrl;
|
||||
bits<4> bank_mask;
|
||||
bits<4> row_mask;
|
||||
bit fi;
|
||||
|
||||
let Inst{40-32} = 0xfa;
|
||||
let Inst{71-64} = !if(P.HasSrc0, src0{7-0}, 0);
|
||||
let Inst{80-72} = dpp_ctrl;
|
||||
let Inst{82} = fi;
|
||||
let Inst{83} = bound_ctrl;
|
||||
// Inst{87-84} ignored by hw
|
||||
let Inst{91-88} = bank_mask;
|
||||
let Inst{95-92} = row_mask;
|
||||
|
||||
}
|
||||
|
||||
class VOPC64_DPP16<bits<10> op, VOP_DPP_Pseudo ps, string opName = ps.OpName>
|
||||
: VOPC64_DPP_Base<op, opName, ps.Pfl> {
|
||||
let AssemblerPredicate = HasDPP16;
|
||||
let SubtargetPredicate = HasDPP16;
|
||||
let hasSideEffects = ps.hasSideEffects;
|
||||
let Defs = ps.Defs;
|
||||
let SchedRW = ps.SchedRW;
|
||||
let Uses = ps.Uses;
|
||||
let OtherPredicates = ps.OtherPredicates;
|
||||
let Constraints = ps.Constraints;
|
||||
}
|
||||
|
||||
class VOPC64_DPP16_Dst<bits<10> op, VOP_DPP_Pseudo ps,
|
||||
string opName = ps.OpName>
|
||||
: VOPC64_DPP16<op, ps, opName> {
|
||||
bits<8> sdst;
|
||||
let Inst{7-0} = sdst;
|
||||
}
|
||||
|
||||
class VOPC64_DPP16_NoDst<bits<10> op, VOP_DPP_Pseudo ps,
|
||||
string opName = ps.OpName>
|
||||
: VOPC64_DPP16<op, ps, opName> {
|
||||
let Inst{7-0} = ? ;
|
||||
let AsmMatchConverter = "cvtVOPC64NoDstDPP";
|
||||
}
|
||||
|
||||
class VOPC64_DPP8_Base<bits<10> op, string OpName, VOPProfile P>
|
||||
: VOP3_DPP8_Base<OpName, P>, VOP3_DPPe_Common<op, P> {
|
||||
bits<8> src0;
|
||||
bits<24> dpp8;
|
||||
bits<9> fi;
|
||||
|
||||
let Inst{40-32} = fi;
|
||||
let Inst{71-64} = !if(P.HasSrc0, src0{7-0}, 0);
|
||||
let Inst{95-72} = dpp8{23-0};
|
||||
|
||||
}
|
||||
|
||||
class VOPC64_DPP8<bits<10> op, VOP_Pseudo ps, string opName = ps.OpName>
|
||||
: VOPC64_DPP8_Base<op, opName, ps.Pfl> {
|
||||
// Note ps is the non-dpp pseudo
|
||||
let hasSideEffects = ps.hasSideEffects;
|
||||
let Defs = ps.Defs;
|
||||
let SchedRW = ps.SchedRW;
|
||||
let Uses = ps.Uses;
|
||||
let OtherPredicates = ps.OtherPredicates;
|
||||
}
|
||||
|
||||
class VOPC64_DPP8_Dst<bits<10> op, VOP_Pseudo ps, string opName = ps.OpName>
|
||||
: VOPC64_DPP8<op, ps, opName> {
|
||||
bits<8> sdst;
|
||||
let Inst{7-0} = sdst;
|
||||
let Constraints = "$old = $sdst";
|
||||
}
|
||||
|
||||
class VOPC64_DPP8_NoDst<bits<10> op, VOP_Pseudo ps, string opName = ps.OpName>
|
||||
: VOPC64_DPP8<op, ps, opName> {
|
||||
let Inst{7-0} = ? ;
|
||||
let AsmMatchConverter = "cvtVOPC64NoDstDPP8";
|
||||
let Constraints = "";
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Target-specific instruction encodings.
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// GFX11.
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
let AssemblerPredicate = isGFX11Only in {
|
||||
multiclass VOPC_Real_gfx11<bits<9> op> {
|
||||
defvar ps32 = !cast<VOPC_Pseudo>(NAME#"_e32");
|
||||
defvar ps64 = !cast<VOP3_Pseudo>(NAME#"_e64");
|
||||
let DecoderNamespace = "GFX11" in {
|
||||
def _e32_gfx11 : VOPC_Real<ps32, SIEncodingFamily.GFX11>,
|
||||
VOPCe<op{7-0}>;
|
||||
def _e64_gfx11 : VOP3_Real<ps64, SIEncodingFamily.GFX11>,
|
||||
VOP3a_gfx11<{0, op}, ps64.Pfl> {
|
||||
// Encoding used for VOPC instructions encoded as VOP3 differs from
|
||||
// VOP3e by destination name (sdst) as VOPC doesn't have vector dst.
|
||||
bits<8> sdst;
|
||||
let Inst{7-0} = sdst;
|
||||
}
|
||||
} // End DecoderNamespace = "GFX11"
|
||||
|
||||
defm : VOPCInstAliases<NAME, "gfx11">;
|
||||
|
||||
foreach _ = BoolToList<ps32.Pfl.HasExtDPP>.ret in {
|
||||
defvar psDPP = !cast<VOP_DPP_Pseudo>(NAME #"_e32" #"_dpp");
|
||||
defvar AsmDPP = ps32.Pfl.AsmDPP16;
|
||||
let DecoderNamespace = "DPPGFX11" in {
|
||||
def _e32_dpp_gfx11 : VOPC_DPP16_SIMC<op{7-0}, psDPP,
|
||||
SIEncodingFamily.GFX11>;
|
||||
def _e32_dpp_w32_gfx11 : VOPC_DPP16<op{7-0}, psDPP> {
|
||||
let AsmString = psDPP.OpName # " vcc_lo, " # AsmDPP;
|
||||
let isAsmParserOnly = 1;
|
||||
let WaveSizePredicate = isWave32;
|
||||
}
|
||||
def _e32_dpp_w64_gfx11 : VOPC_DPP16<op{7-0}, psDPP> {
|
||||
let AsmString = psDPP.OpName # " vcc, " # AsmDPP;
|
||||
let isAsmParserOnly = 1;
|
||||
let WaveSizePredicate = isWave64;
|
||||
}
|
||||
}
|
||||
defvar AsmDPP8 = ps32.Pfl.AsmDPP8;
|
||||
let DecoderNamespace = "DPP8GFX11" in {
|
||||
def _e32_dpp8_gfx11 : VOPC_DPP8<op{7-0}, ps32>;
|
||||
def _e32_dpp8_w32_gfx11 : VOPC_DPP8<op{7-0}, ps32> {
|
||||
let AsmString = ps32.OpName # " vcc_lo, " # AsmDPP8;
|
||||
let isAsmParserOnly = 1;
|
||||
let WaveSizePredicate = isWave32;
|
||||
}
|
||||
def _e32_dpp8_w64_gfx11 : VOPC_DPP8<op{7-0}, ps32> {
|
||||
let AsmString = ps32.OpName # " vcc, " # AsmDPP8;
|
||||
let isAsmParserOnly = 1;
|
||||
let WaveSizePredicate = isWave64;
|
||||
}
|
||||
}
|
||||
}
|
||||
foreach _ = BoolToList<ps64.Pfl.HasExtVOP3DPP>.ret in {
|
||||
defvar psDPP = !cast<VOP_DPP_Pseudo>(NAME #"_e64" #"_dpp");
|
||||
defvar AsmDPP = ps64.Pfl.AsmVOP3DPP16;
|
||||
let DecoderNamespace = "DPPGFX11" in {
|
||||
def _e64_dpp_gfx11 : VOPC64_DPP16_Dst<{0, op}, psDPP>,
|
||||
SIMCInstr<psDPP.PseudoInstr, SIEncodingFamily.GFX11>;
|
||||
def _e64_dpp_w32_gfx11 : VOPC64_DPP16_Dst<{0, op}, psDPP> {
|
||||
let AsmString = psDPP.OpName # " vcc_lo, " # AsmDPP;
|
||||
let isAsmParserOnly = 1;
|
||||
let WaveSizePredicate = isWave32;
|
||||
}
|
||||
def _e64_dpp_w64_gfx11 : VOPC64_DPP16_Dst<{0, op}, psDPP> {
|
||||
let AsmString = psDPP.OpName # " vcc, " # AsmDPP;
|
||||
let isAsmParserOnly = 1;
|
||||
let WaveSizePredicate = isWave64;
|
||||
}
|
||||
}
|
||||
defvar AsmDPP8 = ps64.Pfl.AsmVOP3DPP8;
|
||||
let DecoderNamespace = "DPP8GFX11" in {
|
||||
def _e64_dpp8_gfx11 : VOPC64_DPP8_Dst<{0, op}, ps64>;
|
||||
def _e64_dpp8_w32_gfx11 : VOPC64_DPP8_Dst<{0, op}, ps64> {
|
||||
let AsmString = ps32.OpName # " vcc_lo, " # AsmDPP8;
|
||||
let isAsmParserOnly = 1;
|
||||
let WaveSizePredicate = isWave32;
|
||||
}
|
||||
def _e64_dpp8_w64_gfx11 : VOPC64_DPP8_Dst<{0, op}, ps64> {
|
||||
let AsmString = ps32.OpName # " vcc, " # AsmDPP8;
|
||||
let isAsmParserOnly = 1;
|
||||
let WaveSizePredicate = isWave64;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
multiclass VOPC_Real_with_name_gfx11<bits<9> op, string OpName,
|
||||
string asm_name> {
|
||||
defvar ps32 = !cast<VOPC_Pseudo>(OpName#"_e32");
|
||||
defvar ps64 = !cast<VOP3_Pseudo>(OpName#"_e64");
|
||||
let DecoderNamespace = "GFX11" in {
|
||||
def _e32_gfx11 :
|
||||
// 32 and 64 bit forms of the instruction have _e32 and _e64
|
||||
// respectively appended to their assembly mnemonic.
|
||||
// _e64 is printed as part of the VOPDstS64orS32 operand, whereas
|
||||
// the destination-less 32bit forms add it to the asmString here.
|
||||
VOPC_Real<ps32, SIEncodingFamily.GFX11, asm_name#"_e32">,
|
||||
VOPCe<op{7-0}>,
|
||||
MnemonicAlias<ps32.Mnemonic, asm_name>, Requires<[isGFX11Plus]>;
|
||||
def _e64_gfx11 :
|
||||
VOP3_Real<ps64, SIEncodingFamily.GFX11, asm_name>,
|
||||
VOP3a_gfx11<{0, op}, ps64.Pfl>,
|
||||
MnemonicAlias<ps64.Mnemonic, asm_name>, Requires<[isGFX11Plus]> {
|
||||
// Encoding used for VOPC instructions encoded as VOP3 differs from
|
||||
// VOP3e by destination name (sdst) as VOPC doesn't have vector dst.
|
||||
bits<8> sdst;
|
||||
let Inst{7-0} = sdst;
|
||||
}
|
||||
} // End DecoderNamespace = "GFX11"
|
||||
|
||||
defm : VOPCInstAliases<OpName, "gfx11", NAME>;
|
||||
|
||||
foreach _ = BoolToList<ps32.Pfl.HasExtDPP>.ret in {
|
||||
defvar psDPP = !cast<VOP_DPP_Pseudo>(OpName #"_e32" #"_dpp");
|
||||
defvar AsmDPP = ps32.Pfl.AsmDPP16;
|
||||
let DecoderNamespace = "DPPGFX11" in {
|
||||
def _e32_dpp_gfx11 : VOPC_DPP16_SIMC<op{7-0}, psDPP,
|
||||
SIEncodingFamily.GFX11, asm_name>;
|
||||
def _e32_dpp_w32_gfx11
|
||||
: VOPC_DPP16<op{7-0}, psDPP, asm_name> {
|
||||
let AsmString = asm_name # " vcc_lo, " # AsmDPP;
|
||||
let isAsmParserOnly = 1;
|
||||
let WaveSizePredicate = isWave32;
|
||||
}
|
||||
def _e32_dpp_w64_gfx11
|
||||
: VOPC_DPP16<op{7-0}, psDPP, asm_name> {
|
||||
let AsmString = asm_name # " vcc, " # AsmDPP;
|
||||
let isAsmParserOnly = 1;
|
||||
let WaveSizePredicate = isWave64;
|
||||
}
|
||||
}
|
||||
defvar AsmDPP8 = ps32.Pfl.AsmDPP8;
|
||||
let DecoderNamespace = "DPP8GFX11" in {
|
||||
def _e32_dpp8_gfx11 : VOPC_DPP8<op{7-0}, ps32, asm_name>;
|
||||
def _e32_dpp8_w32_gfx11
|
||||
: VOPC_DPP8<op{7-0}, ps32, asm_name> {
|
||||
let AsmString = asm_name # " vcc_lo, " # AsmDPP8;
|
||||
let isAsmParserOnly = 1;
|
||||
let WaveSizePredicate = isWave32;
|
||||
}
|
||||
def _e32_dpp8_w64_gfx11
|
||||
: VOPC_DPP8<op{7-0}, ps32, asm_name> {
|
||||
let AsmString = asm_name # " vcc, " # AsmDPP8;
|
||||
let isAsmParserOnly = 1;
|
||||
let WaveSizePredicate = isWave64;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
foreach _ = BoolToList<ps64.Pfl.HasExtVOP3DPP>.ret in {
|
||||
defvar psDPP = !cast<VOP_DPP_Pseudo>(OpName #"_e64" #"_dpp");
|
||||
defvar AsmDPP = ps64.Pfl.AsmVOP3DPP16;
|
||||
let DecoderNamespace = "DPPGFX11" in {
|
||||
def _e64_dpp_gfx11 : VOPC64_DPP16_Dst<{0, op}, psDPP, asm_name>,
|
||||
SIMCInstr<psDPP.PseudoInstr, SIEncodingFamily.GFX11>;
|
||||
def _e64_dpp_w32_gfx11
|
||||
: VOPC64_DPP16_Dst<{0, op}, psDPP, asm_name> {
|
||||
let AsmString = asm_name # " vcc_lo, " # AsmDPP;
|
||||
let isAsmParserOnly = 1;
|
||||
let WaveSizePredicate = isWave32;
|
||||
}
|
||||
def _e64_dpp_w64_gfx11
|
||||
: VOPC64_DPP16_Dst<{0, op}, psDPP, asm_name> {
|
||||
let AsmString = asm_name # " vcc, " # AsmDPP;
|
||||
let isAsmParserOnly = 1;
|
||||
let WaveSizePredicate = isWave64;
|
||||
}
|
||||
}
|
||||
defvar AsmDPP8 = ps64.Pfl.AsmVOP3DPP8;
|
||||
let DecoderNamespace = "DPP8GFX11" in {
|
||||
def _e64_dpp8_gfx11 : VOPC64_DPP8_Dst<{0, op}, ps64, asm_name>;
|
||||
def _e64_dpp8_w32_gfx11
|
||||
: VOPC64_DPP8_Dst<{0, op}, ps64, asm_name> {
|
||||
let AsmString = asm_name # " vcc_lo, " # AsmDPP8;
|
||||
let isAsmParserOnly = 1;
|
||||
let WaveSizePredicate = isWave32;
|
||||
}
|
||||
def _e64_dpp8_w64_gfx11
|
||||
: VOPC64_DPP8_Dst<{0, op}, ps64, asm_name> {
|
||||
let AsmString = asm_name # " vcc, " # AsmDPP8;
|
||||
let isAsmParserOnly = 1;
|
||||
let WaveSizePredicate = isWave64;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
multiclass VOPCX_Real_gfx11<bits<9> op> {
|
||||
defvar ps32 = !cast<VOPC_Pseudo>(NAME#"_nosdst_e32");
|
||||
defvar ps64 = !cast<VOP3_Pseudo>(NAME#"_nosdst_e64");
|
||||
let DecoderNamespace = "GFX11" in {
|
||||
def _e32_gfx11 :
|
||||
VOPC_Real<ps32, SIEncodingFamily.GFX11>,
|
||||
VOPCe<op{7-0}> {
|
||||
let AsmString = !subst("_nosdst", "", ps32.PseudoInstr)
|
||||
# " " # ps32.AsmOperands;
|
||||
}
|
||||
def _e64_gfx11 :
|
||||
VOP3_Real<ps64, SIEncodingFamily.GFX11>,
|
||||
VOP3a_gfx11<{0, op}, ps64.Pfl> {
|
||||
let Inst{7-0} = ?; // sdst
|
||||
let AsmString = !subst("_nosdst", "", ps64.Mnemonic)
|
||||
# "{_e64} " # ps64.AsmOperands;
|
||||
}
|
||||
} // End DecoderNamespace = "GFX11"
|
||||
|
||||
defm : VOPCXInstAliases<NAME, "gfx11">;
|
||||
|
||||
foreach _ = BoolToList<ps32.Pfl.HasExtDPP>.ret in {
|
||||
defvar psDPP = !cast<VOP_DPP_Pseudo>(NAME #"_nosdst_e32" #"_dpp");
|
||||
defvar AsmDPP = ps32.Pfl.AsmDPP16;
|
||||
let DecoderNamespace = "DPPGFX11" in {
|
||||
def _e32_dpp_gfx11
|
||||
: VOPC_DPP16_SIMC<op{7-0}, psDPP, SIEncodingFamily.GFX11> {
|
||||
let AsmString = !subst("_nosdst", "", psDPP.OpName) # " " # AsmDPP;
|
||||
}
|
||||
}
|
||||
defvar AsmDPP8 = ps32.Pfl.AsmDPP8;
|
||||
let DecoderNamespace = "DPP8GFX11" in {
|
||||
def _e32_dpp8_gfx11 : VOPC_DPP8<op{7-0}, ps32> {
|
||||
let AsmString = !subst("_nosdst", "", ps32.OpName) # " " # AsmDPP8;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
foreach _ = BoolToList<ps64.Pfl.HasExtVOP3DPP>.ret in {
|
||||
defvar psDPP = !cast<VOP_DPP_Pseudo>(NAME #"_nosdst_e64" #"_dpp");
|
||||
defvar AsmDPP = ps64.Pfl.AsmVOP3DPP16;
|
||||
let DecoderNamespace = "DPPGFX11" in {
|
||||
def _e64_dpp_gfx11
|
||||
: VOPC64_DPP16_NoDst<{0, op}, psDPP>,
|
||||
SIMCInstr<psDPP.PseudoInstr, SIEncodingFamily.GFX11> {
|
||||
let AsmString = !subst("_nosdst", "", psDPP.OpName)
|
||||
# "{_e64} " # AsmDPP;
|
||||
}
|
||||
}
|
||||
defvar AsmDPP8 = ps64.Pfl.AsmVOP3DPP8;
|
||||
let DecoderNamespace = "DPP8GFX11" in {
|
||||
def _e64_dpp8_gfx11 : VOPC64_DPP8_NoDst<{0, op}, ps64> {
|
||||
let AsmString = !subst("_nosdst", "", ps64.OpName)
|
||||
# "{_e64} " # AsmDPP8;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
multiclass VOPCX_Real_with_name_gfx11<bits<9> op, string OpName,
|
||||
string asm_name> {
|
||||
defvar ps32 = !cast<VOPC_Pseudo>(OpName#"_nosdst_e32");
|
||||
defvar ps64 = !cast<VOP3_Pseudo>(OpName#"_nosdst_e64");
|
||||
let DecoderNamespace = "GFX11" in {
|
||||
def _e32_gfx11
|
||||
: VOPC_Real<ps32, SIEncodingFamily.GFX11, asm_name>,
|
||||
MnemonicAlias<!subst("_nosdst", "", ps32.Mnemonic), asm_name>,
|
||||
Requires<[isGFX11Plus]>,
|
||||
VOPCe<op{7-0}> {
|
||||
let AsmString = asm_name # "{_e32} " # ps32.AsmOperands;
|
||||
}
|
||||
def _e64_gfx11
|
||||
: VOP3_Real<ps64, SIEncodingFamily.GFX11, asm_name>,
|
||||
MnemonicAlias<!subst("_nosdst", "", ps64.Mnemonic), asm_name>,
|
||||
Requires<[isGFX11Plus]>,
|
||||
VOP3a_gfx11<{0, op}, ps64.Pfl> {
|
||||
let Inst{7-0} = ? ; // sdst
|
||||
let AsmString = asm_name # "{_e64} " # ps64.AsmOperands;
|
||||
}
|
||||
} // End DecoderNamespace = "GFX11"
|
||||
|
||||
defm : VOPCXInstAliases<OpName, "gfx11", NAME>;
|
||||
|
||||
foreach _ = BoolToList<ps32.Pfl.HasExtDPP>.ret in {
|
||||
defvar psDPP = !cast<VOP_DPP_Pseudo>(OpName#"_nosdst_e32"#"_dpp");
|
||||
let DecoderNamespace = "DPPGFX11" in {
|
||||
def _e32_dpp_gfx11 : VOPC_DPP16_SIMC<op{7-0}, psDPP,
|
||||
SIEncodingFamily.GFX11, asm_name>;
|
||||
}
|
||||
let DecoderNamespace = "DPP8GFX11" in {
|
||||
def _e32_dpp8_gfx11 : VOPC_DPP8<op{7-0}, ps32, asm_name>;
|
||||
}
|
||||
}
|
||||
foreach _ = BoolToList<ps64.Pfl.HasExtVOP3DPP>.ret in {
|
||||
defvar psDPP = !cast<VOP_DPP_Pseudo>(OpName#"_nosdst_e64"#"_dpp");
|
||||
defvar AsmDPP = ps64.Pfl.AsmVOP3DPP16;
|
||||
let DecoderNamespace = "DPPGFX11" in {
|
||||
def _e64_dpp_gfx11
|
||||
: VOPC64_DPP16_NoDst<{0, op}, psDPP, asm_name>,
|
||||
SIMCInstr<psDPP.PseudoInstr, SIEncodingFamily.GFX11> {
|
||||
let AsmString = asm_name # "{_e64} " # AsmDPP;
|
||||
}
|
||||
}
|
||||
defvar AsmDPP8 = ps64.Pfl.AsmVOP3DPP8;
|
||||
let DecoderNamespace = "DPP8GFX11" in {
|
||||
def _e64_dpp8_gfx11 : VOPC64_DPP8_NoDst<{0, op}, ps64, asm_name> {
|
||||
let AsmString = asm_name # "{_e64} " # AsmDPP8;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
} // End AssemblerPredicate = isGFX11Only
|
||||
|
||||
defm V_CMP_F_F16 : VOPC_Real_gfx11<0x000>;
|
||||
defm V_CMP_LT_F16 : VOPC_Real_gfx11<0x001>;
|
||||
defm V_CMP_EQ_F16 : VOPC_Real_gfx11<0x002>;
|
||||
defm V_CMP_LE_F16 : VOPC_Real_gfx11<0x003>;
|
||||
defm V_CMP_GT_F16 : VOPC_Real_gfx11<0x004>;
|
||||
defm V_CMP_LG_F16 : VOPC_Real_gfx11<0x005>;
|
||||
defm V_CMP_GE_F16 : VOPC_Real_gfx11<0x006>;
|
||||
defm V_CMP_O_F16 : VOPC_Real_gfx11<0x007>;
|
||||
defm V_CMP_U_F16 : VOPC_Real_gfx11<0x008>;
|
||||
defm V_CMP_NGE_F16 : VOPC_Real_gfx11<0x009>;
|
||||
defm V_CMP_NLG_F16 : VOPC_Real_gfx11<0x00a>;
|
||||
defm V_CMP_NGT_F16 : VOPC_Real_gfx11<0x00b>;
|
||||
defm V_CMP_NLE_F16 : VOPC_Real_gfx11<0x00c>;
|
||||
defm V_CMP_NEQ_F16 : VOPC_Real_gfx11<0x00d>;
|
||||
defm V_CMP_NLT_F16 : VOPC_Real_gfx11<0x00e>;
|
||||
defm V_CMP_T_F16 : VOPC_Real_with_name_gfx11<0x00f, "V_CMP_TRU_F16", "v_cmp_t_f16">;
|
||||
defm V_CMP_F_F32 : VOPC_Real_gfx11<0x010>;
|
||||
defm V_CMP_LT_F32 : VOPC_Real_gfx11<0x011>;
|
||||
defm V_CMP_EQ_F32 : VOPC_Real_gfx11<0x012>;
|
||||
defm V_CMP_LE_F32 : VOPC_Real_gfx11<0x013>;
|
||||
defm V_CMP_GT_F32 : VOPC_Real_gfx11<0x014>;
|
||||
defm V_CMP_LG_F32 : VOPC_Real_gfx11<0x015>;
|
||||
defm V_CMP_GE_F32 : VOPC_Real_gfx11<0x016>;
|
||||
defm V_CMP_O_F32 : VOPC_Real_gfx11<0x017>;
|
||||
defm V_CMP_U_F32 : VOPC_Real_gfx11<0x018>;
|
||||
defm V_CMP_NGE_F32 : VOPC_Real_gfx11<0x019>;
|
||||
defm V_CMP_NLG_F32 : VOPC_Real_gfx11<0x01a>;
|
||||
defm V_CMP_NGT_F32 : VOPC_Real_gfx11<0x01b>;
|
||||
defm V_CMP_NLE_F32 : VOPC_Real_gfx11<0x01c>;
|
||||
defm V_CMP_NEQ_F32 : VOPC_Real_gfx11<0x01d>;
|
||||
defm V_CMP_NLT_F32 : VOPC_Real_gfx11<0x01e>;
|
||||
defm V_CMP_T_F32 : VOPC_Real_with_name_gfx11<0x01f, "V_CMP_TRU_F32", "v_cmp_t_f32">;
|
||||
defm V_CMP_T_F64 : VOPC_Real_with_name_gfx11<0x02f, "V_CMP_TRU_F64", "v_cmp_t_f64">;
|
||||
defm V_CMP_LT_I16 : VOPC_Real_gfx11<0x031>;
|
||||
defm V_CMP_EQ_I16 : VOPC_Real_gfx11<0x032>;
|
||||
defm V_CMP_LE_I16 : VOPC_Real_gfx11<0x033>;
|
||||
defm V_CMP_GT_I16 : VOPC_Real_gfx11<0x034>;
|
||||
defm V_CMP_NE_I16 : VOPC_Real_gfx11<0x035>;
|
||||
defm V_CMP_GE_I16 : VOPC_Real_gfx11<0x036>;
|
||||
defm V_CMP_LT_U16 : VOPC_Real_gfx11<0x039>;
|
||||
defm V_CMP_EQ_U16 : VOPC_Real_gfx11<0x03a>;
|
||||
defm V_CMP_LE_U16 : VOPC_Real_gfx11<0x03b>;
|
||||
defm V_CMP_GT_U16 : VOPC_Real_gfx11<0x03c>;
|
||||
defm V_CMP_NE_U16 : VOPC_Real_gfx11<0x03d>;
|
||||
defm V_CMP_GE_U16 : VOPC_Real_gfx11<0x03e>;
|
||||
defm V_CMP_F_I32 : VOPC_Real_gfx11<0x040>;
|
||||
defm V_CMP_LT_I32 : VOPC_Real_gfx11<0x041>;
|
||||
defm V_CMP_EQ_I32 : VOPC_Real_gfx11<0x042>;
|
||||
defm V_CMP_LE_I32 : VOPC_Real_gfx11<0x043>;
|
||||
defm V_CMP_GT_I32 : VOPC_Real_gfx11<0x044>;
|
||||
defm V_CMP_NE_I32 : VOPC_Real_gfx11<0x045>;
|
||||
defm V_CMP_GE_I32 : VOPC_Real_gfx11<0x046>;
|
||||
defm V_CMP_T_I32 : VOPC_Real_gfx11<0x047>;
|
||||
defm V_CMP_F_U32 : VOPC_Real_gfx11<0x048>;
|
||||
defm V_CMP_LT_U32 : VOPC_Real_gfx11<0x049>;
|
||||
defm V_CMP_EQ_U32 : VOPC_Real_gfx11<0x04a>;
|
||||
defm V_CMP_LE_U32 : VOPC_Real_gfx11<0x04b>;
|
||||
defm V_CMP_GT_U32 : VOPC_Real_gfx11<0x04c>;
|
||||
defm V_CMP_NE_U32 : VOPC_Real_gfx11<0x04d>;
|
||||
defm V_CMP_GE_U32 : VOPC_Real_gfx11<0x04e>;
|
||||
defm V_CMP_T_U32 : VOPC_Real_gfx11<0x04f>;
|
||||
|
||||
defm V_CMP_F_I64 : VOPC_Real_gfx11<0x050>;
|
||||
defm V_CMP_LT_I64 : VOPC_Real_gfx11<0x051>;
|
||||
defm V_CMP_EQ_I64 : VOPC_Real_gfx11<0x052>;
|
||||
defm V_CMP_LE_I64 : VOPC_Real_gfx11<0x053>;
|
||||
defm V_CMP_GT_I64 : VOPC_Real_gfx11<0x054>;
|
||||
defm V_CMP_NE_I64 : VOPC_Real_gfx11<0x055>;
|
||||
defm V_CMP_GE_I64 : VOPC_Real_gfx11<0x056>;
|
||||
defm V_CMP_T_I64 : VOPC_Real_gfx11<0x057>;
|
||||
defm V_CMP_F_U64 : VOPC_Real_gfx11<0x058>;
|
||||
defm V_CMP_LT_U64 : VOPC_Real_gfx11<0x059>;
|
||||
defm V_CMP_EQ_U64 : VOPC_Real_gfx11<0x05a>;
|
||||
defm V_CMP_LE_U64 : VOPC_Real_gfx11<0x05b>;
|
||||
defm V_CMP_GT_U64 : VOPC_Real_gfx11<0x05c>;
|
||||
defm V_CMP_NE_U64 : VOPC_Real_gfx11<0x05d>;
|
||||
defm V_CMP_GE_U64 : VOPC_Real_gfx11<0x05e>;
|
||||
defm V_CMP_T_U64 : VOPC_Real_gfx11<0x05f>;
|
||||
|
||||
defm V_CMP_CLASS_F16 : VOPC_Real_gfx11<0x07d>;
|
||||
defm V_CMP_CLASS_F32 : VOPC_Real_gfx11<0x07e>;
|
||||
defm V_CMP_CLASS_F64 : VOPC_Real_gfx11<0x07f>;
|
||||
|
||||
defm V_CMPX_F_F16 : VOPCX_Real_gfx11<0x080>;
|
||||
defm V_CMPX_LT_F16 : VOPCX_Real_gfx11<0x081>;
|
||||
defm V_CMPX_EQ_F16 : VOPCX_Real_gfx11<0x082>;
|
||||
defm V_CMPX_LE_F16 : VOPCX_Real_gfx11<0x083>;
|
||||
defm V_CMPX_GT_F16 : VOPCX_Real_gfx11<0x084>;
|
||||
defm V_CMPX_LG_F16 : VOPCX_Real_gfx11<0x085>;
|
||||
defm V_CMPX_GE_F16 : VOPCX_Real_gfx11<0x086>;
|
||||
defm V_CMPX_O_F16 : VOPCX_Real_gfx11<0x087>;
|
||||
defm V_CMPX_U_F16 : VOPCX_Real_gfx11<0x088>;
|
||||
defm V_CMPX_NGE_F16 : VOPCX_Real_gfx11<0x089>;
|
||||
defm V_CMPX_NLG_F16 : VOPCX_Real_gfx11<0x08a>;
|
||||
defm V_CMPX_NGT_F16 : VOPCX_Real_gfx11<0x08b>;
|
||||
defm V_CMPX_NLE_F16 : VOPCX_Real_gfx11<0x08c>;
|
||||
defm V_CMPX_NEQ_F16 : VOPCX_Real_gfx11<0x08d>;
|
||||
defm V_CMPX_NLT_F16 : VOPCX_Real_gfx11<0x08e>;
|
||||
defm V_CMPX_T_F16 : VOPCX_Real_with_name_gfx11<0x08f, "V_CMPX_TRU_F16", "v_cmpx_t_f16">;
|
||||
defm V_CMPX_F_F32 : VOPCX_Real_gfx11<0x090>;
|
||||
defm V_CMPX_LT_F32 : VOPCX_Real_gfx11<0x091>;
|
||||
defm V_CMPX_EQ_F32 : VOPCX_Real_gfx11<0x092>;
|
||||
defm V_CMPX_LE_F32 : VOPCX_Real_gfx11<0x093>;
|
||||
defm V_CMPX_GT_F32 : VOPCX_Real_gfx11<0x094>;
|
||||
defm V_CMPX_LG_F32 : VOPCX_Real_gfx11<0x095>;
|
||||
defm V_CMPX_GE_F32 : VOPCX_Real_gfx11<0x096>;
|
||||
defm V_CMPX_O_F32 : VOPCX_Real_gfx11<0x097>;
|
||||
defm V_CMPX_U_F32 : VOPCX_Real_gfx11<0x098>;
|
||||
defm V_CMPX_NGE_F32 : VOPCX_Real_gfx11<0x099>;
|
||||
defm V_CMPX_NLG_F32 : VOPCX_Real_gfx11<0x09a>;
|
||||
defm V_CMPX_NGT_F32 : VOPCX_Real_gfx11<0x09b>;
|
||||
defm V_CMPX_NLE_F32 : VOPCX_Real_gfx11<0x09c>;
|
||||
defm V_CMPX_NEQ_F32 : VOPCX_Real_gfx11<0x09d>;
|
||||
defm V_CMPX_NLT_F32 : VOPCX_Real_gfx11<0x09e>;
|
||||
defm V_CMPX_T_F32 : VOPCX_Real_with_name_gfx11<0x09f, "V_CMPX_TRU_F32", "v_cmpx_t_f32">;
|
||||
|
||||
defm V_CMPX_F_F64 : VOPCX_Real_gfx11<0x0a0>;
|
||||
defm V_CMPX_LT_F64 : VOPCX_Real_gfx11<0x0a1>;
|
||||
defm V_CMPX_EQ_F64 : VOPCX_Real_gfx11<0x0a2>;
|
||||
defm V_CMPX_LE_F64 : VOPCX_Real_gfx11<0x0a3>;
|
||||
defm V_CMPX_GT_F64 : VOPCX_Real_gfx11<0x0a4>;
|
||||
defm V_CMPX_LG_F64 : VOPCX_Real_gfx11<0x0a5>;
|
||||
defm V_CMPX_GE_F64 : VOPCX_Real_gfx11<0x0a6>;
|
||||
defm V_CMPX_O_F64 : VOPCX_Real_gfx11<0x0a7>;
|
||||
defm V_CMPX_U_F64 : VOPCX_Real_gfx11<0x0a8>;
|
||||
defm V_CMPX_NGE_F64 : VOPCX_Real_gfx11<0x0a9>;
|
||||
defm V_CMPX_NLG_F64 : VOPCX_Real_gfx11<0x0aa>;
|
||||
defm V_CMPX_NGT_F64 : VOPCX_Real_gfx11<0x0ab>;
|
||||
defm V_CMPX_NLE_F64 : VOPCX_Real_gfx11<0x0ac>;
|
||||
defm V_CMPX_NEQ_F64 : VOPCX_Real_gfx11<0x0ad>;
|
||||
defm V_CMPX_NLT_F64 : VOPCX_Real_gfx11<0x0ae>;
|
||||
defm V_CMPX_T_F64 : VOPCX_Real_with_name_gfx11<0x0af, "V_CMPX_TRU_F64", "v_cmpx_t_f64">;
|
||||
|
||||
defm V_CMPX_LT_I16 : VOPCX_Real_gfx11<0x0b1>;
|
||||
defm V_CMPX_EQ_I16 : VOPCX_Real_gfx11<0x0b2>;
|
||||
defm V_CMPX_LE_I16 : VOPCX_Real_gfx11<0x0b3>;
|
||||
defm V_CMPX_GT_I16 : VOPCX_Real_gfx11<0x0b4>;
|
||||
defm V_CMPX_NE_I16 : VOPCX_Real_gfx11<0x0b5>;
|
||||
defm V_CMPX_GE_I16 : VOPCX_Real_gfx11<0x0b6>;
|
||||
defm V_CMPX_LT_U16 : VOPCX_Real_gfx11<0x0b9>;
|
||||
defm V_CMPX_EQ_U16 : VOPCX_Real_gfx11<0x0ba>;
|
||||
defm V_CMPX_LE_U16 : VOPCX_Real_gfx11<0x0bb>;
|
||||
defm V_CMPX_GT_U16 : VOPCX_Real_gfx11<0x0bc>;
|
||||
defm V_CMPX_NE_U16 : VOPCX_Real_gfx11<0x0bd>;
|
||||
defm V_CMPX_GE_U16 : VOPCX_Real_gfx11<0x0be>;
|
||||
defm V_CMPX_F_I32 : VOPCX_Real_gfx11<0x0c0>;
|
||||
defm V_CMPX_LT_I32 : VOPCX_Real_gfx11<0x0c1>;
|
||||
defm V_CMPX_EQ_I32 : VOPCX_Real_gfx11<0x0c2>;
|
||||
defm V_CMPX_LE_I32 : VOPCX_Real_gfx11<0x0c3>;
|
||||
defm V_CMPX_GT_I32 : VOPCX_Real_gfx11<0x0c4>;
|
||||
defm V_CMPX_NE_I32 : VOPCX_Real_gfx11<0x0c5>;
|
||||
defm V_CMPX_GE_I32 : VOPCX_Real_gfx11<0x0c6>;
|
||||
defm V_CMPX_T_I32 : VOPCX_Real_gfx11<0x0c7>;
|
||||
defm V_CMPX_F_U32 : VOPCX_Real_gfx11<0x0c8>;
|
||||
defm V_CMPX_LT_U32 : VOPCX_Real_gfx11<0x0c9>;
|
||||
defm V_CMPX_EQ_U32 : VOPCX_Real_gfx11<0x0ca>;
|
||||
defm V_CMPX_LE_U32 : VOPCX_Real_gfx11<0x0cb>;
|
||||
defm V_CMPX_GT_U32 : VOPCX_Real_gfx11<0x0cc>;
|
||||
defm V_CMPX_NE_U32 : VOPCX_Real_gfx11<0x0cd>;
|
||||
defm V_CMPX_GE_U32 : VOPCX_Real_gfx11<0x0ce>;
|
||||
defm V_CMPX_T_U32 : VOPCX_Real_gfx11<0x0cf>;
|
||||
|
||||
defm V_CMPX_F_I64 : VOPCX_Real_gfx11<0x0d0>;
|
||||
defm V_CMPX_LT_I64 : VOPCX_Real_gfx11<0x0d1>;
|
||||
defm V_CMPX_EQ_I64 : VOPCX_Real_gfx11<0x0d2>;
|
||||
defm V_CMPX_LE_I64 : VOPCX_Real_gfx11<0x0d3>;
|
||||
defm V_CMPX_GT_I64 : VOPCX_Real_gfx11<0x0d4>;
|
||||
defm V_CMPX_NE_I64 : VOPCX_Real_gfx11<0x0d5>;
|
||||
defm V_CMPX_GE_I64 : VOPCX_Real_gfx11<0x0d6>;
|
||||
defm V_CMPX_T_I64 : VOPCX_Real_gfx11<0x0d7>;
|
||||
defm V_CMPX_F_U64 : VOPCX_Real_gfx11<0x0d8>;
|
||||
defm V_CMPX_LT_U64 : VOPCX_Real_gfx11<0x0d9>;
|
||||
defm V_CMPX_EQ_U64 : VOPCX_Real_gfx11<0x0da>;
|
||||
defm V_CMPX_LE_U64 : VOPCX_Real_gfx11<0x0db>;
|
||||
defm V_CMPX_GT_U64 : VOPCX_Real_gfx11<0x0dc>;
|
||||
defm V_CMPX_NE_U64 : VOPCX_Real_gfx11<0x0dd>;
|
||||
defm V_CMPX_GE_U64 : VOPCX_Real_gfx11<0x0de>;
|
||||
defm V_CMPX_T_U64 : VOPCX_Real_gfx11<0x0df>;
|
||||
defm V_CMPX_CLASS_F16 : VOPCX_Real_gfx11<0x0fd>;
|
||||
defm V_CMPX_CLASS_F32 : VOPCX_Real_gfx11<0x0fe>;
|
||||
defm V_CMPX_CLASS_F64 : VOPCX_Real_gfx11<0x0ff>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// GFX10.
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
let AssemblerPredicate = isGFX10Plus in {
|
||||
let AssemblerPredicate = isGFX10Only in {
|
||||
multiclass VOPC_Real_gfx10<bits<9> op> {
|
||||
let DecoderNamespace = "GFX10" in {
|
||||
def _e32_gfx10 :
|
||||
|
|
@ -942,7 +1718,7 @@ let AssemblerPredicate = isGFX10Plus in {
|
|||
|
||||
defm : VOPCXInstAliases<NAME, "gfx10">;
|
||||
}
|
||||
} // End AssemblerPredicate = isGFX10Plus
|
||||
} // End AssemblerPredicate = isGFX10Only
|
||||
|
||||
defm V_CMP_LT_I16 : VOPC_Real_gfx10<0x089>;
|
||||
defm V_CMP_EQ_I16 : VOPC_Real_gfx10<0x08a>;
|
||||
|
|
@ -1036,6 +1812,12 @@ multiclass VOPCX_Real_gfx6_gfx7<bits<9> op> :
|
|||
multiclass VOPCX_Real_gfx6_gfx7_gfx10 <bits<9> op> :
|
||||
VOPC_Real_gfx6_gfx7<op>, VOPCX_Real_gfx10<op>;
|
||||
|
||||
multiclass VOPC_Real_gfx6_gfx7_gfx10_gfx11<bits<9> op> :
|
||||
VOPC_Real_gfx6_gfx7_gfx10<op>, VOPC_Real_gfx11<op>;
|
||||
|
||||
multiclass VOPCX_Real_gfx6_gfx7_gfx10_gfx11<bits<9> op> :
|
||||
VOPCX_Real_gfx6_gfx7_gfx10<op>, VOPCX_Real_gfx11<op>;
|
||||
|
||||
defm V_CMP_F_F32 : VOPC_Real_gfx6_gfx7_gfx10<0x000>;
|
||||
defm V_CMP_LT_F32 : VOPC_Real_gfx6_gfx7_gfx10<0x001>;
|
||||
defm V_CMP_EQ_F32 : VOPC_Real_gfx6_gfx7_gfx10<0x002>;
|
||||
|
|
@ -1068,21 +1850,21 @@ defm V_CMPX_NLE_F32 : VOPCX_Real_gfx6_gfx7_gfx10<0x01c>;
|
|||
defm V_CMPX_NEQ_F32 : VOPCX_Real_gfx6_gfx7_gfx10<0x01d>;
|
||||
defm V_CMPX_NLT_F32 : VOPCX_Real_gfx6_gfx7_gfx10<0x01e>;
|
||||
defm V_CMPX_TRU_F32 : VOPCX_Real_gfx6_gfx7_gfx10<0x01f>;
|
||||
defm V_CMP_F_F64 : VOPC_Real_gfx6_gfx7_gfx10<0x020>;
|
||||
defm V_CMP_LT_F64 : VOPC_Real_gfx6_gfx7_gfx10<0x021>;
|
||||
defm V_CMP_EQ_F64 : VOPC_Real_gfx6_gfx7_gfx10<0x022>;
|
||||
defm V_CMP_LE_F64 : VOPC_Real_gfx6_gfx7_gfx10<0x023>;
|
||||
defm V_CMP_GT_F64 : VOPC_Real_gfx6_gfx7_gfx10<0x024>;
|
||||
defm V_CMP_LG_F64 : VOPC_Real_gfx6_gfx7_gfx10<0x025>;
|
||||
defm V_CMP_GE_F64 : VOPC_Real_gfx6_gfx7_gfx10<0x026>;
|
||||
defm V_CMP_O_F64 : VOPC_Real_gfx6_gfx7_gfx10<0x027>;
|
||||
defm V_CMP_U_F64 : VOPC_Real_gfx6_gfx7_gfx10<0x028>;
|
||||
defm V_CMP_NGE_F64 : VOPC_Real_gfx6_gfx7_gfx10<0x029>;
|
||||
defm V_CMP_NLG_F64 : VOPC_Real_gfx6_gfx7_gfx10<0x02a>;
|
||||
defm V_CMP_NGT_F64 : VOPC_Real_gfx6_gfx7_gfx10<0x02b>;
|
||||
defm V_CMP_NLE_F64 : VOPC_Real_gfx6_gfx7_gfx10<0x02c>;
|
||||
defm V_CMP_NEQ_F64 : VOPC_Real_gfx6_gfx7_gfx10<0x02d>;
|
||||
defm V_CMP_NLT_F64 : VOPC_Real_gfx6_gfx7_gfx10<0x02e>;
|
||||
defm V_CMP_F_F64 : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x020>;
|
||||
defm V_CMP_LT_F64 : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x021>;
|
||||
defm V_CMP_EQ_F64 : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x022>;
|
||||
defm V_CMP_LE_F64 : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x023>;
|
||||
defm V_CMP_GT_F64 : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x024>;
|
||||
defm V_CMP_LG_F64 : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x025>;
|
||||
defm V_CMP_GE_F64 : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x026>;
|
||||
defm V_CMP_O_F64 : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x027>;
|
||||
defm V_CMP_U_F64 : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x028>;
|
||||
defm V_CMP_NGE_F64 : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x029>;
|
||||
defm V_CMP_NLG_F64 : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x02a>;
|
||||
defm V_CMP_NGT_F64 : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x02b>;
|
||||
defm V_CMP_NLE_F64 : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x02c>;
|
||||
defm V_CMP_NEQ_F64 : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x02d>;
|
||||
defm V_CMP_NLT_F64 : VOPC_Real_gfx6_gfx7_gfx10_gfx11<0x02e>;
|
||||
defm V_CMP_TRU_F64 : VOPC_Real_gfx6_gfx7_gfx10<0x02f>;
|
||||
defm V_CMPX_F_F64 : VOPCX_Real_gfx6_gfx7_gfx10<0x030>;
|
||||
defm V_CMPX_LT_F64 : VOPCX_Real_gfx6_gfx7_gfx10<0x031>;
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,233 @@
|
|||
// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11,W32 %s
|
||||
// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11,W64 %s
|
||||
// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s
|
||||
// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s
|
||||
|
||||
// =========================================================
|
||||
// dpp8
|
||||
// =========================================================
|
||||
|
||||
// 32 bit
|
||||
|
||||
v_cmp_le_u16_dpp v1, v2 dpp8:[7,7,7,3,4,4,6,7] fi:1
|
||||
// GFX11: encoding: [0xea,0x04,0x76,0x7c,0x01,0xff,0x47,0xfa]
|
||||
|
||||
v_cmp_le_i16_dpp v1, v2 dpp8:[7,7,7,3,4,4,6,7]
|
||||
// GFX11: encoding: [0xe9,0x04,0x66,0x7c,0x01,0xff,0x47,0xfa]
|
||||
|
||||
// w32
|
||||
|
||||
v_cmp_le_i32_dpp vcc_lo, v1, v255 dpp8:[0,2,1,3,4,5,6,7]
|
||||
// W32: encoding: [0xe9,0xfe,0x87,0x7c,0x01,0x50,0xc6,0xfa]
|
||||
// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
|
||||
|
||||
v_cmp_tru_f32_dpp vcc_lo, v1, v2 dpp8:[0,2,1,3,4,5,6,7]
|
||||
// W32: encoding: [0xe9,0x04,0x3e,0x7c,0x01,0x50,0xc6,0xfa]
|
||||
// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
|
||||
|
||||
// check vcc/vcc_lo have been added
|
||||
v_cmp_lt_f32_dpp v1, v2 dpp8:[2,3,4,1,3,3,3,3]
|
||||
// W32: v_cmp_lt_f32 vcc_lo, v1, v2 dpp8:[2,3,4,1,3,3,3,3] ; encoding: [0xe9,0x04,0x22,0x7c,0x01,0x1a,0xb3,0x6d]
|
||||
// W64: v_cmp_lt_f32 vcc, v1, v2 dpp8:[2,3,4,1,3,3,3,3] ; encoding: [0xe9,0x04,0x22,0x7c,0x01,0x1a,0xb3,0x6d]
|
||||
|
||||
// w64
|
||||
|
||||
v_cmp_lt_u16_dpp vcc, v1, v2 dpp8:[7,6,5,3,4,2,1,0] fi:1
|
||||
// W64: encoding: [0xea,0x04,0x72,0x7c,0x01,0x77,0x47,0x05]
|
||||
// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
|
||||
|
||||
// cmp class
|
||||
|
||||
v_cmp_class_f16_dpp vcc, v1, v2 dpp8:[7,6,5,3,4,2,1,0] fi:1
|
||||
// W64: encoding: [0xea,0x04,0xfa,0x7c,0x01,0x77,0x47,0x05]
|
||||
// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
|
||||
|
||||
// cmpx
|
||||
|
||||
v_cmpx_f_i32_dpp v0, v2 dpp8:[7,6,5,3,4,2,1,0] fi:1
|
||||
// GFX11: encoding: [0xea,0x04,0x80,0x7d,0x00,0x77,0x47,0x05]
|
||||
|
||||
v_cmpx_t_f32_dpp v255, v2 dpp8:[7,6,5,3,4,2,1,0]
|
||||
// GFX11: encoding: [0xe9,0x04,0x3e,0x7d,0xff,0x77,0x47,0x05]
|
||||
|
||||
// cmpx class
|
||||
|
||||
v_cmpx_class_f16_dpp v12, v101 dpp8:[7,6,5,3,4,2,1,0]
|
||||
// GFX11: encoding: [0xe9,0xca,0xfa,0x7d,0x0c,0x77,0x47,0x05]
|
||||
|
||||
// =========================================================
|
||||
// 64 bit
|
||||
|
||||
v_cmp_lt_i16_e64_dpp s[50:51], v1, v22 dpp8:[7,6,5,3,4,2,1,0]
|
||||
// W64: encoding: [0x32,0x00,0x31,0xd4,0xe9,0x2c,0x02,0x00,0x01,0x77,0x47,0x05]
|
||||
// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
|
||||
|
||||
v_cmp_lt_i16_e64_dpp s10, v10, v2 dpp8:[7,6,5,3,4,2,1,0]
|
||||
// W32: encoding: [0x0a,0x00,0x31,0xd4,0xe9,0x04,0x02,0x00,0x0a,0x77,0x47,0x05]
|
||||
// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
|
||||
|
||||
// w32
|
||||
|
||||
v_cmp_gt_i32_e64_dpp s10, v1, v50 dpp8:[0,1,2,3,4,5,6,7] fi:1
|
||||
// W32: encoding: [0x0a,0x00,0x44,0xd4,0xea,0x64,0x02,0x00,0x01,0x88,0xc6,0xfa]
|
||||
// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
|
||||
|
||||
v_cmp_ngt_f32_e64_dpp s10, -v1, v2 dpp8:[0,1,2,3,4,5,6,7] fi:1
|
||||
// W32: encoding: [0x0a,0x00,0x1b,0xd4,0xea,0x04,0x02,0x20,0x01,0x88,0xc6,0xfa]
|
||||
// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
|
||||
|
||||
// w64
|
||||
|
||||
v_cmp_f_f32_e64_dpp s[10:11], v1, v2 dpp8:[0,1,2,3,4,5,6,7] fi:1
|
||||
// W64: encoding: [0x0a,0x00,0x10,0xd4,0xea,0x04,0x02,0x00,0x01,0x88,0xc6,0xfa]
|
||||
// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
|
||||
|
||||
v_cmp_nle_f32_e64_dpp s[10:11], v2, v201 dpp8:[0,1,6,3,4,5,6,7]
|
||||
// W64: encoding: [0x0a,0x00,0x1c,0xd4,0xe9,0x92,0x03,0x00,0x02,0x88,0xc7,0xfa]
|
||||
// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
|
||||
|
||||
v_cmp_lt_f16_e64_dpp s[10:11], v240, -v2 dpp8:[0,1,6,3,4,5,6,7]
|
||||
// W64: encoding: [0x0a,0x00,0x01,0xd4,0xe9,0x04,0x02,0x40,0xf0,0x88,0xc7,0xfa]
|
||||
// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
|
||||
|
||||
// cmp class
|
||||
|
||||
// w32
|
||||
|
||||
v_cmp_class_f32_e64_dpp s10, v10, v2 dpp8:[0,1,6,3,4,5,6,7]
|
||||
// W32: encoding: [0x0a,0x00,0x7e,0xd4,0xe9,0x04,0x02,0x00,0x0a,0x88,0xc7,0xfa]
|
||||
// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
|
||||
|
||||
// w64
|
||||
|
||||
v_cmp_class_f16_e64_dpp vcc, v1, v2 dpp8:[0,1,6,3,4,5,6,7]
|
||||
// W64: encoding: [0x6a,0x00,0x7d,0xd4,0xe9,0x04,0x02,0x00,0x01,0x88,0xc7,0xfa]
|
||||
// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
|
||||
|
||||
// cmpx
|
||||
|
||||
v_cmpx_eq_i16_e64_dpp v5, v25 dpp8:[0,1,6,3,4,5,6,7] fi:1
|
||||
// GFX11: encoding: [0x00,0x00,0xb2,0xd4,0xea,0x32,0x02,0x00,0x05,0x88,0xc7,0xfa]
|
||||
|
||||
v_cmpx_ge_i32_e64_dpp v0, v3 dpp8:[0,1,6,3,4,5,6,7] fi:1
|
||||
// GFX11: encoding: [0x00,0x00,0xc6,0xd4,0xea,0x06,0x02,0x00,0x00,0x88,0xc7,0xfa]
|
||||
|
||||
// cmpx class
|
||||
|
||||
v_cmpx_class_f32_e64_dpp v1, v20 dpp8:[0,1,6,3,4,5,6,7] fi:1
|
||||
// GFX11: encoding: [0x00,0x00,0xfe,0xd4,0xea,0x28,0x02,0x00,0x01,0x88,0xc7,0xfa]
|
||||
|
||||
// ================================================================
|
||||
// dpp
|
||||
// ================================================================
|
||||
|
||||
// 32 bit
|
||||
|
||||
v_cmp_gt_u16_dpp v1, v2 row_shl:0x7 row_mask:0x0 bank_mask:0x0 fi:1
|
||||
// GFX11: encoding: [0xfa,0x04,0x78,0x7c,0x01,0x07,0x05,0x00]
|
||||
|
||||
v_cmp_gt_i16_dpp v1, v2 quad_perm:[1,3,1,0] row_mask:0x7
|
||||
// GFX11: encoding: [0xfa,0x04,0x68,0x7c,0x01,0x1d,0x00,0x7f]
|
||||
|
||||
v_cmp_lt_f32 v1, -v2 quad_perm:[0,1,2,2]
|
||||
// GFX11: encoding: [0xfa,0x04,0x22,0x7c,0x01,0xa4,0x40,0xff]
|
||||
|
||||
// w32
|
||||
|
||||
v_cmp_gt_i32_dpp vcc_lo, v1, v255 row_mirror bank_mask:0x2 fi:1
|
||||
// W32: encoding: [0xfa,0xfe,0x89,0x7c,0x01,0x40,0x05,0xf2]
|
||||
// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
|
||||
|
||||
v_cmp_f_f32_dpp vcc_lo, v1, v2 row_shl:0x7 row_mask:0x0 bank_mask:0x0
|
||||
// W32: encoding: [0xfa,0x04,0x20,0x7c,0x01,0x07,0x01,0x00]
|
||||
// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
|
||||
|
||||
// w64
|
||||
|
||||
v_cmp_ge_u16_dpp vcc, v1, v2 row_share:0xa bound_ctrl:0
|
||||
// W64: encoding: [0xfa,0x04,0x7c,0x7c,0x01,0x5a,0x09,0xff]
|
||||
// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
|
||||
|
||||
// cmp class
|
||||
|
||||
v_cmp_class_f16_dpp vcc, v1, v2 row_half_mirror bound_ctrl:0
|
||||
// W64: encoding: [0xfa,0x04,0xfa,0x7c,0x01,0x41,0x09,0xff]
|
||||
// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
|
||||
|
||||
// cmpx
|
||||
|
||||
v_cmpx_t_i32_dpp v0, v2 row_shr:0xe row_mask:0x3 bank_mask:0xa bound_ctrl:0
|
||||
// GFX11: encoding: [0xfa,0x04,0x8e,0x7d,0x00,0x1e,0x09,0x3a]
|
||||
|
||||
v_cmpx_f_f32_dpp v255, v2 quad_perm:[2,3,0,0]
|
||||
// GFX11: encoding: [0xfa,0x04,0x20,0x7d,0xff,0x0e,0x00,0xff]
|
||||
|
||||
// cmpx class
|
||||
|
||||
v_cmpx_class_f16_dpp v12, v101 quad_perm:[2,3,0,0] fi:1
|
||||
// GFX11: encoding: [0xfa,0xca,0xfa,0x7d,0x0c,0x0e,0x04,0xff]
|
||||
|
||||
v_cmpx_class_f16_dpp abs(v12), v101 quad_perm:[2,3,0,0]
|
||||
// GFX11: encoding: [0xfa,0xca,0xfa,0x7d,0x0c,0x0e,0x20,0xff]
|
||||
|
||||
// =========================================================
|
||||
// 64 bit
|
||||
|
||||
v_cmp_ge_i16_e64_dpp s[50:51], v1, v22 quad_perm:[2,2,3,1]
|
||||
// W64: encoding: [0x32,0x00,0x36,0xd4,0xfa,0x2c,0x02,0x00,0x01,0x7a,0x00,0xff]
|
||||
// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
|
||||
|
||||
v_cmp_ge_i16_e64_dpp s10, v10, v2 quad_perm:[0,2,3,1] row_mask:0x0
|
||||
// W32: encoding: [0x0a,0x00,0x36,0xd4,0xfa,0x04,0x02,0x00,0x0a,0x78,0x00,0x0f]
|
||||
// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
|
||||
|
||||
// w32
|
||||
|
||||
v_cmp_le_i32_e64_dpp s10, v1, v50 quad_perm:[0,2,3,1] row_mask:0x0
|
||||
// W32: encoding: [0x0a,0x00,0x43,0xd4,0xfa,0x64,0x02,0x00,0x01,0x78,0x00,0x0f]
|
||||
// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
|
||||
|
||||
v_cmp_nle_f32_e64_dpp s10, -v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
|
||||
// W32: encoding: [0x0a,0x00,0x1c,0xd4,0xfa,0x04,0x02,0x20,0x01,0x1b,0x00,0x00]
|
||||
// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
|
||||
|
||||
// w64
|
||||
|
||||
v_cmp_t_f32_e64_dpp s[10:11], v1, v2 quad_perm:[3,2,1,0] bank_mask:0xe
|
||||
// W64: encoding: [0x0a,0x00,0x1f,0xd4,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xfe]
|
||||
// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
|
||||
|
||||
v_cmp_ngt_f32_e64_dpp s[10:11], v2, v201 row_ror:7 bank_mask:0x1 bound_ctrl:0
|
||||
// W64: encoding: [0x0a,0x00,0x1b,0xd4,0xfa,0x92,0x03,0x00,0x02,0x27,0x09,0xf1]
|
||||
// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
|
||||
|
||||
v_cmp_lt_f16_e64_dpp s[10:11], v240, -v2 row_xmask:0x6 row_mask:0x0 fi:1
|
||||
// W64: encoding: [0x0a,0x00,0x01,0xd4,0xfa,0x04,0x02,0x40,0xf0,0x66,0x05,0x0f]
|
||||
// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
|
||||
|
||||
// cmp class
|
||||
|
||||
// w32
|
||||
|
||||
v_cmp_class_f32_e64_dpp s10, v10, v2 quad_perm:[2,2,3,1] bound_ctrl:0 fi:1
|
||||
// W32: encoding: [0x0a,0x00,0x7e,0xd4,0xfa,0x04,0x02,0x00,0x0a,0x7a,0x0c,0xff]
|
||||
// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
|
||||
|
||||
// w64
|
||||
|
||||
v_cmp_class_f16_e64_dpp vcc, v1, v2 quad_perm:[1,2,3,1] bank_mask: 0x5 fi:1
|
||||
// W64: encoding: [0x6a,0x00,0x7d,0xd4,0xfa,0x04,0x02,0x00,0x01,0x79,0x04,0xf5]
|
||||
// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error
|
||||
|
||||
// cmpx
|
||||
|
||||
v_cmpx_eq_i16_e64_dpp v5, v25 quad_perm:[2,2,3,1] bound_ctrl:0 fi:1
|
||||
// GFX11: encoding: [0x00,0x00,0xb2,0xd4,0xfa,0x32,0x02,0x00,0x05,0x7a,0x0c,0xff]
|
||||
|
||||
v_cmpx_lt_i32_e64_dpp v0, v3 quad_perm:[3,2,1,0] bank_mask:0xe
|
||||
// GFX11: encoding: [0x00,0x00,0xc1,0xd4,0xfa,0x06,0x02,0x00,0x00,0x1b,0x00,0xfe]
|
||||
|
||||
// cmpx class
|
||||
|
||||
v_cmpx_class_f32_e64_dpp v1, v20 row_ror:7 bank_mask:0x1 bound_ctrl:0
|
||||
// GFX11: encoding: [0x00,0x00,0xfe,0xd4,0xfa,0x28,0x02,0x00,0x01,0x27,0x09,0xf1]
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue