forked from OSchip/llvm-project
Reland r308585
Builder clang-x86_64-linux-abi-test apparently failed due to a spurious error unrelated to the changes r308585 introduced. llvm-svn: 308612
This commit is contained in:
Stefan Maksimovic
parent
b6485252aa
commit
be0bc71e02
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@ -1124,10 +1124,7 @@ class ROUND_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.w.d", FGR64Opnd,
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FGR64Opnd, II_ROUND>;
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class SEL_S_MMR6_DESC : COP1_SEL_DESC_BASE<"sel.s", FGR32Opnd, II_SEL_S>;
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class SEL_D_MMR6_DESC : COP1_SEL_DESC_BASE<"sel.d", FGR64Opnd, II_SEL_D> {
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// We must insert a SUBREG_TO_REG around $fd_in
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bit usesCustomInserter = 1;
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}
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class SEL_D_MMR6_DESC : COP1_SEL_D_DESC_BASE<"sel.d", FGR64Opnd, II_SEL_D>;
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class SELEQZ_S_MMR6_DESC : SELEQNEZ_DESC_BASE<"seleqz.s", FGR32Opnd,
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II_SELCCZ_S>;
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@ -13,6 +13,24 @@
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include "Mips32r6InstrFormats.td"
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//===----------------------------------------------------------------------===//
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//
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// Mips profiles and nodes
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//
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//===----------------------------------------------------------------------===//
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def SDT_MipsFSelect : SDTypeProfile<1, 3, [SDTCisFP<1>,
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SDTCisSameAs<0,2>,
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SDTCisSameAs<2,3>]>;
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def MipsFSelect : SDNode<"MipsISD::FSELECT", SDT_MipsFSelect>;
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//===----------------------------------------------------------------------===//
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//
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// Mips Operands
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//
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//===----------------------------------------------------------------------===//
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// Notes about removals/changes from MIPS32r6:
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// Reencoded: jr -> jalr
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// Reencoded: jr.hb -> jalr.hb
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@ -578,11 +596,20 @@ class COP1_SEL_DESC_BASE<string instr_asm, RegisterOperand FGROpnd,
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InstrItinClass Itinerary = itin;
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}
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class SEL_D_DESC : COP1_SEL_DESC_BASE<"sel.d", FGR64Opnd, II_SEL_D>,
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MipsR6Arch<"sel.d"> {
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// We must insert a SUBREG_TO_REG around $fd_in
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bit usesCustomInserter = 1;
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class COP1_SEL_D_DESC_BASE<string instr_asm, RegisterOperand FGROpnd,
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InstrItinClass itin> {
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dag OutOperandList = (outs FGROpnd:$fd);
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dag InOperandList = (ins FGROpnd:$fd_in, FGROpnd:$fs, FGROpnd:$ft);
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string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
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list<dag> Pattern = [(set FGROpnd:$fd, (MipsFSelect FGROpnd:$fd_in,
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FGROpnd:$ft,
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FGROpnd:$fs))];
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string Constraints = "$fd_in = $fd";
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InstrItinClass Itinerary = itin;
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}
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class SEL_D_DESC : COP1_SEL_D_DESC_BASE<"sel.d", FGR64Opnd, II_SEL_D>,
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MipsR6Arch<"sel.d">;
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class SEL_S_DESC : COP1_SEL_DESC_BASE<"sel.s", FGR32Opnd, II_SEL_S>,
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MipsR6Arch<"sel.s">;
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@ -270,13 +270,13 @@ let usesCustomInserter = 1 in {
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ISA_MIPS1_NOT_4_32;
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class SelectFP_Pseudo_T<RegisterOperand RC> :
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PseudoSE<(outs RC:$dst), (ins GPR32Opnd:$cond, RC:$T, RC:$F),
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[(set RC:$dst, (MipsCMovFP_T RC:$T, GPR32Opnd:$cond, RC:$F))]>,
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PseudoSE<(outs RC:$dst), (ins FCCRegsOpnd:$cond, RC:$T, RC:$F),
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[(set RC:$dst, (MipsCMovFP_T RC:$T, FCCRegsOpnd:$cond, RC:$F))]>,
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ISA_MIPS1_NOT_4_32;
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class SelectFP_Pseudo_F<RegisterOperand RC> :
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PseudoSE<(outs RC:$dst), (ins GPR32Opnd:$cond, RC:$T, RC:$F),
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[(set RC:$dst, (MipsCMovFP_F RC:$T, GPR32Opnd:$cond, RC:$F))]>,
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PseudoSE<(outs RC:$dst), (ins FCCRegsOpnd:$cond, RC:$T, RC:$F),
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[(set RC:$dst, (MipsCMovFP_F RC:$T, FCCRegsOpnd:$cond, RC:$F))]>,
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ISA_MIPS1_NOT_4_32;
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}
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@ -166,6 +166,8 @@ const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
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case MipsISD::EH_RETURN: return "MipsISD::EH_RETURN";
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case MipsISD::FPBrcond: return "MipsISD::FPBrcond";
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case MipsISD::FPCmp: return "MipsISD::FPCmp";
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case MipsISD::FSELECT: return "MipsISD::FSELECT";
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case MipsISD::MTC1_D64: return "MipsISD::MTC1_D64";
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case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T";
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case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F";
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case MipsISD::TruncIntFP: return "MipsISD::TruncIntFP";
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@ -1398,9 +1400,6 @@ MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
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case Mips::DMOD_MM64R6:
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case Mips::DMODU_MM64R6:
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return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true, true);
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case Mips::SEL_D:
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case Mips::SEL_D_MMR6:
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return emitSEL_D(MI, BB);
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case Mips::PseudoSELECT_I:
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case Mips::PseudoSELECT_I64:
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@ -1960,32 +1959,6 @@ MachineBasicBlock *MipsTargetLowering::emitAtomicCmpSwapPartword(
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return exitMBB;
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}
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MachineBasicBlock *MipsTargetLowering::emitSEL_D(MachineInstr &MI,
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MachineBasicBlock *BB) const {
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MachineFunction *MF = BB->getParent();
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const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
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const TargetInstrInfo *TII = Subtarget.getInstrInfo();
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MachineRegisterInfo &RegInfo = MF->getRegInfo();
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DebugLoc DL = MI.getDebugLoc();
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MachineBasicBlock::iterator II(MI);
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unsigned Fc = MI.getOperand(1).getReg();
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const auto &FGR64RegClass = TRI->getRegClass(Mips::FGR64RegClassID);
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unsigned Fc2 = RegInfo.createVirtualRegister(FGR64RegClass);
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BuildMI(*BB, II, DL, TII->get(Mips::SUBREG_TO_REG), Fc2)
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.addImm(0)
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.addReg(Fc)
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.addImm(Mips::sub_lo);
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// We don't erase the original instruction, we just replace the condition
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// register with the 64-bit super-register.
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MI.getOperand(1).setReg(Fc2);
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return BB;
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}
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SDValue MipsTargetLowering::lowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
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// The first operand is the chain, the second is the condition, the third is
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// the block to branch to if the condition is true.
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@ -66,6 +66,12 @@ namespace llvm {
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// Floating Point Compare
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FPCmp,
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// Floating point select
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FSELECT,
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// Node used to generate an MTC1 i32 to f64 instruction
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MTC1_D64,
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// Floating Point Conditional Moves
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CMovFP_T,
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CMovFP_F,
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@ -39,6 +39,9 @@ def SDT_MipsExtractElementF64 : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
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SDTCisVT<1, f64>,
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SDTCisVT<2, i32>]>;
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def SDT_MipsMTC1_D64 : SDTypeProfile<1, 1, [SDTCisVT<0, f64>,
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SDTCisVT<1, i32>]>;
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def MipsFPCmp : SDNode<"MipsISD::FPCmp", SDT_MipsFPCmp, [SDNPOutGlue]>;
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def MipsCMovFP_T : SDNode<"MipsISD::CMovFP_T", SDT_MipsCMovFP, [SDNPInGlue]>;
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def MipsCMovFP_F : SDNode<"MipsISD::CMovFP_F", SDT_MipsCMovFP, [SDNPInGlue]>;
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@ -49,6 +52,8 @@ def MipsBuildPairF64 : SDNode<"MipsISD::BuildPairF64", SDT_MipsBuildPairF64>;
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def MipsExtractElementF64 : SDNode<"MipsISD::ExtractElementF64",
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SDT_MipsExtractElementF64>;
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def MipsMTC1_D64 : SDNode<"MipsISD::MTC1_D64", SDT_MipsMTC1_D64>;
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// Operand for printing out a condition code.
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let PrintMethod = "printFCCOperand", DecoderMethod = "DecodeCondCode" in
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def condcode : Operand<i32>;
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@ -820,6 +825,9 @@ def : MipsPat<(f32 (sint_to_fp GPR32Opnd:$src)),
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def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src),
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(TRUNC_W_S FGR32Opnd:$src)>;
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def : MipsPat<(MipsMTC1_D64 GPR32Opnd:$src),
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(MTC1_D64 GPR32Opnd:$src)>, FGR_64;
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def : MipsPat<(f64 (sint_to_fp GPR32Opnd:$src)),
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(PseudoCVT_D32_W GPR32Opnd:$src)>, FGR_32;
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def : MipsPat<(MipsTruncIntFP AFGR64Opnd:$src),
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@ -220,7 +220,7 @@ MipsSETargetLowering::MipsSETargetLowering(const MipsTargetMachine &TM,
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assert(Subtarget.isFP64bit() && "FR=1 is required for MIPS32r6");
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setOperationAction(ISD::SETCC, MVT::f64, Legal);
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setOperationAction(ISD::SELECT, MVT::f64, Legal);
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setOperationAction(ISD::SELECT, MVT::f64, Custom);
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setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
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setOperationAction(ISD::BRCOND, MVT::Other, Legal);
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@ -367,6 +367,22 @@ addMSAFloatType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
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}
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}
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SDValue MipsSETargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const {
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if(!Subtarget.hasMips32r6())
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return MipsTargetLowering::LowerOperation(Op, DAG);
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EVT ResTy = Op->getValueType(0);
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SDLoc DL(Op);
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// Although MTC1_D64 takes an i32 and writes an f64, the upper 32 bits of the
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// floating point register are undefined. Not really an issue as sel.d, which
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// is produced from an FSELECT node, only looks at bit 0.
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SDValue Tmp = DAG.getNode(MipsISD::MTC1_D64, DL, MVT::f64, Op->getOperand(0));
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return DAG.getNode(MipsISD::FSELECT, DL, ResTy, Tmp, Op->getOperand(1),
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Op->getOperand(2));
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}
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bool
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MipsSETargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
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unsigned,
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@ -414,6 +430,7 @@ SDValue MipsSETargetLowering::LowerOperation(SDValue Op,
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case ISD::EXTRACT_VECTOR_ELT: return lowerEXTRACT_VECTOR_ELT(Op, DAG);
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case ISD::BUILD_VECTOR: return lowerBUILD_VECTOR(Op, DAG);
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case ISD::VECTOR_SHUFFLE: return lowerVECTOR_SHUFFLE(Op, DAG);
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case ISD::SELECT: return lowerSELECT(Op, DAG);
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}
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return MipsTargetLowering::LowerOperation(Op, DAG);
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@ -76,6 +76,7 @@ namespace llvm {
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/// \brief Lower VECTOR_SHUFFLE into one of a number of instructions
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/// depending on the indices in the shuffle.
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SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
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MachineBasicBlock *emitBPOSGE32(MachineInstr &MI,
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MachineBasicBlock *BB) const;
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@ -1,32 +1,32 @@
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; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
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; RUN: llc < %s -march=mips -mcpu=mips2 -verify-machineinstrs | FileCheck %s \
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; RUN: -check-prefixes=ALL,M2,M2-M3
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; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
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; RUN: llc < %s -march=mips -mcpu=mips32 -verify-machineinstrs | FileCheck %s \
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; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R1
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; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
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; RUN: llc < %s -march=mips -mcpu=mips32r2 -verify-machineinstrs | FileCheck %s \
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; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R2-R5
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; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
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; RUN: llc < %s -march=mips -mcpu=mips32r3 -verify-machineinstrs | FileCheck %s \
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; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R2-R5
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; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
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; RUN: llc < %s -march=mips -mcpu=mips32r5 -verify-machineinstrs | FileCheck %s \
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; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R2-R5
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; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
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; RUN: llc < %s -march=mips -mcpu=mips32r6 -verify-machineinstrs | FileCheck %s \
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; RUN: -check-prefixes=ALL,SEL-32,32R6
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; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
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; RUN: llc < %s -march=mips64 -mcpu=mips3 -verify-machineinstrs | FileCheck %s \
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; RUN: -check-prefixes=ALL,M3,M2-M3
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; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
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; RUN: llc < %s -march=mips64 -mcpu=mips4 -verify-machineinstrs | FileCheck %s \
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; RUN: -check-prefixes=ALL,CMOV,CMOV-64
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; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
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; RUN: llc < %s -march=mips64 -mcpu=mips64 -verify-machineinstrs | FileCheck %s \
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; RUN: -check-prefixes=ALL,CMOV,CMOV-64
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; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
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; RUN: llc < %s -march=mips64 -mcpu=mips64r2 -verify-machineinstrs | FileCheck %s \
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; RUN: -check-prefixes=ALL,CMOV,CMOV-64
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; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
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; RUN: llc < %s -march=mips64 -mcpu=mips64r3 -verify-machineinstrs | FileCheck %s \
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; RUN: -check-prefixes=ALL,CMOV,CMOV-64
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; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
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; RUN: llc < %s -march=mips64 -mcpu=mips64r5 -verify-machineinstrs | FileCheck %s \
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; RUN: -check-prefixes=ALL,CMOV,CMOV-64
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; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
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; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -verify-machineinstrs | FileCheck %s \
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; RUN: -check-prefixes=ALL,SEL-64,64R6
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; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \
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; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -verify-machineinstrs | FileCheck %s \
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; RUN: -check-prefixes=ALL,MM32R3
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; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
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; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -verify-machineinstrs | FileCheck %s \
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; RUN: -check-prefixes=ALL,MM32R6,SEL-32
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define double @tst_select_i1_double(i1 signext %s, double %x, double %y) {
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@ -53,8 +53,8 @@ entry:
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; SEL-32: mtc1 $7, $[[F0:f[0-9]+]]
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; SEL-32: mthc1 $6, $[[F0]]
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; SEL-32: ldc1 $[[F1:f[0-9]+]], 16($sp)
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; SEL-32: mtc1 $4, $f0
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; SEL-32: ldc1 $[[F1:f[0-9]+]], 16($sp)
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; SEL-32: sel.d $f0, $[[F1]], $[[F0]]
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; M3: andi $[[T0:[0-9]+]], $4, 1
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@ -1,32 +1,32 @@
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; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
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; RUN: llc < %s -march=mips -mcpu=mips2 -verify-machineinstrs | FileCheck %s \
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; RUN: -check-prefixes=ALL,M2,M2-M3
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; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
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; RUN: llc < %s -march=mips -mcpu=mips32 -verify-machineinstrs | FileCheck %s \
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; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R1
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; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
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; RUN: llc < %s -march=mips -mcpu=mips32r2 -verify-machineinstrs | FileCheck %s \
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; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R2-R5
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; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
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; RUN: llc < %s -march=mips -mcpu=mips32r3 -verify-machineinstrs | FileCheck %s \
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; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R2-R5
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; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
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; RUN: llc < %s -march=mips -mcpu=mips32r5 -verify-machineinstrs | FileCheck %s \
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; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R2-R5
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; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
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; RUN: llc < %s -march=mips -mcpu=mips32r6 -verify-machineinstrs | FileCheck %s \
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; RUN: -check-prefixes=ALL,SEL-32,32R6
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; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
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; RUN: llc < %s -march=mips64 -mcpu=mips3 -verify-machineinstrs | FileCheck %s \
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; RUN: -check-prefixes=ALL,M3,M2-M3
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; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
|
||||
; RUN: llc < %s -march=mips64 -mcpu=mips4 -verify-machineinstrs | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,CMOV,CMOV-64
|
||||
; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
|
||||
; RUN: llc < %s -march=mips64 -mcpu=mips64 -verify-machineinstrs | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,CMOV,CMOV-64
|
||||
; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
|
||||
; RUN: llc < %s -march=mips64 -mcpu=mips64r2 -verify-machineinstrs | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,CMOV,CMOV-64
|
||||
; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
|
||||
; RUN: llc < %s -march=mips64 -mcpu=mips64r3 -verify-machineinstrs | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,CMOV,CMOV-64
|
||||
; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
|
||||
; RUN: llc < %s -march=mips64 -mcpu=mips64r5 -verify-machineinstrs | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,CMOV,CMOV-64
|
||||
; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
|
||||
; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -verify-machineinstrs | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,SEL-64,64R6
|
||||
; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \
|
||||
; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -verify-machineinstrs | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,MM32R3
|
||||
; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
|
||||
; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -verify-machineinstrs | FileCheck %s \
|
||||
; RUN: -check-prefixes=ALL,MM32R6,SEL-32
|
||||
|
||||
define float @tst_select_i1_float(i1 signext %s, float %x, float %y) {
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
; RUN: llc < %s -march=mipsel -mcpu=mips32 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,32
|
||||
; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,32R2
|
||||
; RUN: llc < %s -march=mipsel -mcpu=mips32r6 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,32R6
|
||||
; RUN: llc < %s -march=mips64el -mcpu=mips64 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,64
|
||||
; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,64R2
|
||||
; RUN: llc < %s -march=mips64el -mcpu=mips64r6 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,64R6
|
||||
; RUN: llc < %s -march=mipsel -mcpu=mips32 -relocation-model=pic -verify-machineinstrs | FileCheck %s -check-prefixes=ALL,32
|
||||
; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -relocation-model=pic -verify-machineinstrs | FileCheck %s -check-prefixes=ALL,32R2
|
||||
; RUN: llc < %s -march=mipsel -mcpu=mips32r6 -relocation-model=pic -verify-machineinstrs | FileCheck %s -check-prefixes=ALL,32R6
|
||||
; RUN: llc < %s -march=mips64el -mcpu=mips64 -relocation-model=pic -verify-machineinstrs | FileCheck %s -check-prefixes=ALL,64
|
||||
; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -relocation-model=pic -verify-machineinstrs | FileCheck %s -check-prefixes=ALL,64R2
|
||||
; RUN: llc < %s -march=mips64el -mcpu=mips64r6 -relocation-model=pic -verify-machineinstrs | FileCheck %s -check-prefixes=ALL,64R6
|
||||
|
||||
@d2 = external global double
|
||||
@d3 = external global double
|
||||
|
|
|
|||
Loading…
Reference in New Issue