maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

[Power9]Legalize and emit code for quad-precision convert from double-precision 

Legalize and emit code for quad-precision floating point operation xscvdpqp
and add option to guard the quad precision operation support.

Differential Revision: https://reviews.llvm.org/D44746

llvm-svn: 328558
This commit is contained in:
Lei Huang 2018-03-26 17:46:25 +00:00
parent 7341691502
commit be0afb0870
3 changed files with 42 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -111,6 +111,9 @@ cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
static cl::opt<bool> DisableSCO("disable-ppc-sco",
cl::desc("disable sibling call optimization on ppc"), cl::Hidden);
static cl::opt<bool> EnableQuadPrecision("enable-ppc-quad-precision",
cl::desc("enable quad precision float support on ppc"), cl::Hidden);
STATISTIC(NumTailCalls, "Number of tail calls");
STATISTIC(NumSiblingCalls, "Number of sibling calls");
@ -787,11 +790,15 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
setOperationAction(ISD::SRL, MVT::v1i128, Legal);
setOperationAction(ISD::SRA, MVT::v1i128, Expand);
addRegisterClass(MVT::f128, &PPC::VRRCRegClass);
setOperationAction(ISD::FADD, MVT::f128, Legal);
setOperationAction(ISD::FSUB, MVT::f128, Legal);
setOperationAction(ISD::FDIV, MVT::f128, Legal);
setOperationAction(ISD::FMUL, MVT::f128, Legal);
if (EnableQuadPrecision) {
addRegisterClass(MVT::f128, &PPC::VRRCRegClass);
setOperationAction(ISD::FADD, MVT::f128, Legal);
setOperationAction(ISD::FSUB, MVT::f128, Legal);
setOperationAction(ISD::FDIV, MVT::f128, Legal);
setOperationAction(ISD::FMUL, MVT::f128, Legal);
setOperationAction(ISD::FP_EXTEND, MVT::f128, Legal);
setLoadExtAction(ISD::EXTLOAD, MVT::f128, MVT::f64, Expand);
}
}

1
llvm/lib/Target/PowerPC/PPCInstrVSX.td
View File

@ -2470,6 +2470,7 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in {
// Convert DP -> QP
def XSCVDPQP : X_VT5_XO5_VB5_TyVB<63, 22, 836, "xscvdpqp", vfrc, []>;
def : Pat<(f128 (fpextend f64:$src)), (f128 (XSCVDPQP $src))>;
// Round & Convert QP -> DP (dword[1] is set to zero)
def XSCVQPDP : X_VT5_XO5_VB5 <63, 20, 836, "xscvqpdp" , []>;

30
llvm/test/CodeGen/PowerPC/f128-arith.ll
View File

@ -1,4 +1,5 @@
; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s
; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
; RUN: -enable-ppc-quad-precision < %s | FileCheck %s
; Function Attrs: norecurse nounwind
define void @qpAdd(fp128* nocapture readonly %a, fp128* nocapture %res) {
@ -147,3 +148,30 @@ entry:
; CHECK: stxv
; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @dpConv2qp(double* nocapture readonly %a, fp128* nocapture %res) {
entry:
%0 = load double, double* %a, align 8
%conv = fpext double %0 to fp128
store fp128 %conv, fp128* %res, align 16
ret void
; CHECK-LABEL: dpConv2qp
; CHECK-NOT: bl __extenddftf2
; CHECK: lxsd
; CHECK: xscvdpqp
; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @dpConv2qp_02(double %a, fp128* nocapture %res) {
entry:
%conv = fpext double %a to fp128
store fp128 %conv, fp128* %res, align 16
ret void
; CHECK-LABEL: dpConv2qp_02
; CHECK-NOT: bl __extenddftf2
; CHECK: xxlor
; CHECK: xscvdpqp
; CHECK: blr
}