forked from OSchip/llvm-project
[AMDGPU] hazard recognizer for fp atomic to s_denorm_mode
This requires 3 wait states unless there is a wait or VALU in between. Differential Revision: https://reviews.llvm.org/D63619 llvm-svn: 364074
This commit is contained in:
Stanislav Mekhanoshin
parent
dbcdad51ff
commit
bdf7f81b89
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@ -691,34 +691,53 @@ class MUBUF_AtomicRet_Pseudo<string opName, int addrKind,
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multiclass MUBUF_Pseudo_Atomics_NO_RTN <string opName,
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RegisterClass vdataClass,
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ValueType vdataType,
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SDPatternOperator atomic> {
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SDPatternOperator atomic,
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bit isFP = getIsFP<vdataType>.ret> {
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let FPAtomic = isFP in
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def _OFFSET : MUBUF_AtomicNoRet_Pseudo <opName, BUFAddrKind.Offset, vdataClass>,
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MUBUFAddr64Table <0, NAME>;
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let FPAtomic = isFP in
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def _ADDR64 : MUBUF_AtomicNoRet_Pseudo <opName, BUFAddrKind.Addr64, vdataClass>,
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MUBUFAddr64Table <1, NAME>;
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let FPAtomic = isFP in
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def _OFFEN : MUBUF_AtomicNoRet_Pseudo <opName, BUFAddrKind.OffEn, vdataClass>;
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let FPAtomic = isFP in
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def _IDXEN : MUBUF_AtomicNoRet_Pseudo <opName, BUFAddrKind.IdxEn, vdataClass>;
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let FPAtomic = isFP in
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def _BOTHEN : MUBUF_AtomicNoRet_Pseudo <opName, BUFAddrKind.BothEn, vdataClass>;
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}
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multiclass MUBUF_Pseudo_Atomics_RTN <string opName,
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RegisterClass vdataClass,
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ValueType vdataType,
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SDPatternOperator atomic> {
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SDPatternOperator atomic,
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bit isFP = getIsFP<vdataType>.ret> {
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let FPAtomic = isFP in
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def _OFFSET_RTN : MUBUF_AtomicRet_Pseudo <opName, BUFAddrKind.Offset, vdataClass,
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[(set vdataType:$vdata,
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(atomic (MUBUFOffsetAtomic v4i32:$srsrc, i32:$soffset, i16:$offset, i1:$slc),
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vdataType:$vdata_in))]>,
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MUBUFAddr64Table <0, NAME # "_RTN">;
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let FPAtomic = isFP in
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def _ADDR64_RTN : MUBUF_AtomicRet_Pseudo <opName, BUFAddrKind.Addr64, vdataClass,
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[(set vdataType:$vdata,
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(atomic (MUBUFAddr64Atomic v4i32:$srsrc, i64:$vaddr, i32:$soffset, i16:$offset, i1:$slc),
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vdataType:$vdata_in))]>,
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MUBUFAddr64Table <1, NAME # "_RTN">;
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let FPAtomic = isFP in
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def _OFFEN_RTN : MUBUF_AtomicRet_Pseudo <opName, BUFAddrKind.OffEn, vdataClass>;
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let FPAtomic = isFP in
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def _IDXEN_RTN : MUBUF_AtomicRet_Pseudo <opName, BUFAddrKind.IdxEn, vdataClass>;
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let FPAtomic = isFP in
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def _BOTHEN_RTN : MUBUF_AtomicRet_Pseudo <opName, BUFAddrKind.BothEn, vdataClass>;
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}
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@ -273,7 +273,8 @@ multiclass FLAT_Atomic_Pseudo<
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ValueType vt,
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SDPatternOperator atomic = null_frag,
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ValueType data_vt = vt,
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RegisterClass data_rc = vdst_rc> {
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RegisterClass data_rc = vdst_rc,
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bit isFP = getIsFP<data_vt>.ret> {
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def "" : FLAT_AtomicNoRet_Pseudo <opName,
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(outs),
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(ins VReg_64:$vaddr, data_rc:$vdata, offset_u12:$offset, SLC:$slc),
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@ -281,6 +282,7 @@ multiclass FLAT_Atomic_Pseudo<
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GlobalSaddrTable<0, opName>,
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AtomicNoRet <opName, 0> {
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let PseudoInstr = NAME;
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let FPAtomic = isFP;
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}
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def _RTN : FLAT_AtomicRet_Pseudo <opName,
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@ -290,7 +292,9 @@ multiclass FLAT_Atomic_Pseudo<
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[(set vt:$vdst,
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(atomic (FLATAtomic i64:$vaddr, i16:$offset, i1:$slc), data_vt:$vdata))]>,
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GlobalSaddrTable<0, opName#"_rtn">,
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AtomicNoRet <opName, 1>;
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AtomicNoRet <opName, 1>{
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let FPAtomic = isFP;
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}
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}
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multiclass FLAT_Global_Atomic_Pseudo_NO_RTN<
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@ -299,7 +303,8 @@ multiclass FLAT_Global_Atomic_Pseudo_NO_RTN<
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ValueType vt,
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SDPatternOperator atomic = null_frag,
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ValueType data_vt = vt,
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RegisterClass data_rc = vdst_rc> {
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RegisterClass data_rc = vdst_rc,
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bit isFP = getIsFP<data_vt>.ret> {
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def "" : FLAT_AtomicNoRet_Pseudo <opName,
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(outs),
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@ -309,6 +314,7 @@ multiclass FLAT_Global_Atomic_Pseudo_NO_RTN<
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AtomicNoRet <opName, 0> {
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let has_saddr = 1;
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let PseudoInstr = NAME;
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let FPAtomic = isFP;
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}
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def _SADDR : FLAT_AtomicNoRet_Pseudo <opName,
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@ -320,6 +326,7 @@ multiclass FLAT_Global_Atomic_Pseudo_NO_RTN<
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let has_saddr = 1;
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let enabled_saddr = 1;
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let PseudoInstr = NAME#"_SADDR";
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let FPAtomic = isFP;
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}
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}
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@ -329,7 +336,8 @@ multiclass FLAT_Global_Atomic_Pseudo_RTN<
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ValueType vt,
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SDPatternOperator atomic = null_frag,
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ValueType data_vt = vt,
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RegisterClass data_rc = vdst_rc> {
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RegisterClass data_rc = vdst_rc,
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bit isFP = getIsFP<data_vt>.ret> {
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def _RTN : FLAT_AtomicRet_Pseudo <opName,
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(outs vdst_rc:$vdst),
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@ -340,6 +348,7 @@ multiclass FLAT_Global_Atomic_Pseudo_RTN<
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GlobalSaddrTable<0, opName#"_rtn">,
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AtomicNoRet <opName, 1> {
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let has_saddr = 1;
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let FPAtomic = isFP;
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}
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def _SADDR_RTN : FLAT_AtomicRet_Pseudo <opName,
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@ -351,6 +360,7 @@ multiclass FLAT_Global_Atomic_Pseudo_RTN<
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let has_saddr = 1;
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let enabled_saddr = 1;
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let PseudoInstr = NAME#"_SADDR_RTN";
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let FPAtomic = isFP;
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}
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}
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@ -145,6 +145,9 @@ GCNHazardRecognizer::getHazardType(SUnit *SU, int Stalls) {
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if (ST.hasNSAtoVMEMBug() && checkNSAtoVMEMHazard(MI) > 0)
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return NoopHazard;
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if (checkFPAtomicToDenormModeHazard(MI) > 0)
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return NoopHazard;
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if (ST.hasNoDataDepHazard())
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return NoHazard;
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@ -247,6 +250,8 @@ unsigned GCNHazardRecognizer::PreEmitNoopsCommon(MachineInstr *MI) {
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if (ST.hasNSAtoVMEMBug())
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WaitStates = std::max(WaitStates, checkNSAtoVMEMHazard(MI));
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WaitStates = std::max(WaitStates, checkFPAtomicToDenormModeHazard(MI));
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if (ST.hasNoDataDepHazard())
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return WaitStates;
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@ -1138,3 +1143,39 @@ int GCNHazardRecognizer::checkNSAtoVMEMHazard(MachineInstr *MI) {
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return NSAtoVMEMWaitStates - getWaitStatesSince(IsHazardFn, 1);
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}
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int GCNHazardRecognizer::checkFPAtomicToDenormModeHazard(MachineInstr *MI) {
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int FPAtomicToDenormModeWaitStates = 3;
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if (MI->getOpcode() != AMDGPU::S_DENORM_MODE)
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return 0;
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auto IsHazardFn = [] (MachineInstr *I) {
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if (!SIInstrInfo::isVMEM(*I) && !SIInstrInfo::isFLAT(*I))
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return false;
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return SIInstrInfo::isFPAtomic(*I);
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};
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auto IsExpiredFn = [] (MachineInstr *MI, int WaitStates) {
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if (WaitStates >= 3 || SIInstrInfo::isVALU(*MI))
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return true;
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switch (MI->getOpcode()) {
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case AMDGPU::S_WAITCNT:
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case AMDGPU::S_WAITCNT_VSCNT:
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case AMDGPU::S_WAITCNT_VMCNT:
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case AMDGPU::S_WAITCNT_EXPCNT:
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case AMDGPU::S_WAITCNT_LGKMCNT:
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case AMDGPU::S_WAITCNT_IDLE:
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return true;
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default:
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break;
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}
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return false;
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};
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return FPAtomicToDenormModeWaitStates -
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::getWaitStatesSince(IsHazardFn, MI, IsExpiredFn);
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}
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@ -84,6 +84,7 @@ private:
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int checkAnyInstHazards(MachineInstr *MI);
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int checkReadM0Hazards(MachineInstr *SMovRel);
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int checkNSAtoVMEMHazard(MachineInstr *MI);
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int checkFPAtomicToDenormModeHazard(MachineInstr *MI);
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void fixHazards(MachineInstr *MI);
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bool fixVcmpxPermlaneHazards(MachineInstr *MI);
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bool fixVMEMtoScalarWriteHazards(MachineInstr *MI);
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@ -716,9 +716,11 @@ defm IMAGE_ATOMIC_OR : MIMG_Atomic <mimg<0x19>, "image_atomic_or">;
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defm IMAGE_ATOMIC_XOR : MIMG_Atomic <mimg<0x1a>, "image_atomic_xor">;
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defm IMAGE_ATOMIC_INC : MIMG_Atomic <mimg<0x1b>, "image_atomic_inc">;
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defm IMAGE_ATOMIC_DEC : MIMG_Atomic <mimg<0x1c>, "image_atomic_dec">;
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//let FPAtomic = 1 in {
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//def IMAGE_ATOMIC_FCMPSWAP : MIMG_NoPattern_ <"image_atomic_fcmpswap", 0x0000001d, 1>; -- not on VI
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//def IMAGE_ATOMIC_FMIN : MIMG_NoPattern_ <"image_atomic_fmin", 0x0000001e>; -- not on VI
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//def IMAGE_ATOMIC_FMAX : MIMG_NoPattern_ <"image_atomic_fmax", 0x0000001f>; -- not on VI
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//} // End let FPAtomic = 1
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defm IMAGE_SAMPLE : MIMG_Sampler_WQM <0x00000020, AMDGPUSample>;
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defm IMAGE_SAMPLE_CL : MIMG_Sampler_WQM <0x00000021, AMDGPUSample_cl>;
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defm IMAGE_SAMPLE_D : MIMG_Sampler <0x00000022, AMDGPUSample_d>;
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@ -93,7 +93,10 @@ enum : uint64_t {
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IsNonFlatSeg = UINT64_C(1) << 51,
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// Uses floating point double precision rounding mode
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FPDPRounding = UINT64_C(1) << 52
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FPDPRounding = UINT64_C(1) << 52,
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// Instruction is FP atomic.
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FPAtomic = UINT64_C(1) << 53
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};
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// v_cmp_class_* etc. use a 10-bit mask for what operation is checked.
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@ -118,6 +118,9 @@ class InstSI <dag outs, dag ins, string asm = "",
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// rounding mode flags
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field bit FPDPRounding = 0;
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// Instruction is FP atomic.
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field bit FPAtomic = 0;
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// These need to be kept in sync with the enum in SIInstrFlags.
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let TSFlags{0} = SALU;
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let TSFlags{1} = VALU;
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@ -179,6 +182,8 @@ class InstSI <dag outs, dag ins, string asm = "",
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let TSFlags{52} = FPDPRounding;
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let TSFlags{53} = FPAtomic;
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let SchedRW = [Write32Bit];
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field bits<1> DisableSIDecoder = 0;
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@ -631,6 +631,14 @@ public:
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return get(Opcode).TSFlags & SIInstrFlags::FPDPRounding;
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}
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static bool isFPAtomic(const MachineInstr &MI) {
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return MI.getDesc().TSFlags & SIInstrFlags::FPAtomic;
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}
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bool isFPAtomic(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::FPAtomic;
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}
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bool isVGPRCopy(const MachineInstr &MI) const {
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assert(MI.isCopy());
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unsigned Dest = MI.getOperand(0).getReg();
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@ -1243,6 +1243,17 @@ class getVALUDstForVT<ValueType VT> {
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VOPDstS64orS32)))); // else VT == i1
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}
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// Returns true if VT is floating point.
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class getIsFP<ValueType VT> {
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bit ret = !if(!eq(VT.Value, f16.Value), 1,
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!if(!eq(VT.Value, v2f16.Value), 1,
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!if(!eq(VT.Value, f32.Value), 1,
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!if(!eq(VT.Value, v2f32.Value), 1,
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!if(!eq(VT.Value, f64.Value), 1,
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!if(!eq(VT.Value, v2f64.Value), 1,
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0))))));
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}
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// Returns the register class to use for the destination of VOP[12C]
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// instructions with SDWA extension
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class getSDWADstForVT<ValueType VT> {
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@ -1254,11 +1265,7 @@ class getSDWADstForVT<ValueType VT> {
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// Returns the register class to use for source 0 of VOP[12C]
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// instructions for the given VT.
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class getVOPSrc0ForVT<ValueType VT> {
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bit isFP = !if(!eq(VT.Value, f16.Value), 1,
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!if(!eq(VT.Value, v2f16.Value), 1,
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!if(!eq(VT.Value, f32.Value), 1,
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!if(!eq(VT.Value, f64.Value), 1,
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0))));
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bit isFP = getIsFP<VT>.ret;
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RegisterOperand ret =
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!if(isFP,
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@ -1292,9 +1299,7 @@ class getVregSrcForVT<ValueType VT> {
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}
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class getSDWASrcForVT <ValueType VT> {
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bit isFP = !if(!eq(VT.Value, f16.Value), 1,
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!if(!eq(VT.Value, f32.Value), 1,
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0));
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bit isFP = getIsFP<VT>.ret;
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RegisterOperand retFlt = !if(!eq(VT.Size, 16), SDWASrc_f16, SDWASrc_f32);
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RegisterOperand retInt = !if(!eq(VT.Size, 16), SDWASrc_i16, SDWASrc_i32);
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RegisterOperand ret = !if(isFP, retFlt, retInt);
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@ -1303,11 +1308,7 @@ class getSDWASrcForVT <ValueType VT> {
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// Returns the register class to use for sources of VOP3 instructions for the
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// given VT.
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class getVOP3SrcForVT<ValueType VT> {
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bit isFP = !if(!eq(VT.Value, f16.Value), 1,
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!if(!eq(VT.Value, v2f16.Value), 1,
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!if(!eq(VT.Value, f32.Value), 1,
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!if(!eq(VT.Value, f64.Value), 1,
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0))));
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bit isFP = getIsFP<VT>.ret;
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RegisterOperand ret =
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!if(!eq(VT.Size, 128),
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VSrc_128,
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@ -1351,10 +1352,7 @@ class isModifierType<ValueType SrcVT> {
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// Return type of input modifiers operand for specified input operand
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class getSrcMod <ValueType VT, bit EnableF32SrcMods> {
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bit isFP = !if(!eq(VT.Value, f16.Value), 1,
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!if(!eq(VT.Value, f32.Value), 1,
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!if(!eq(VT.Value, f64.Value), 1,
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0)));
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bit isFP = getIsFP<VT>.ret;
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bit isPacked = isPackedType<VT>.ret;
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Operand ret = !if(!eq(VT.Size, 64),
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!if(isFP, FP64InputMods, Int64InputMods),
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@ -1373,10 +1371,7 @@ class getOpSelMod <ValueType VT> {
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// Return type of input modifiers operand specified input operand for DPP
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class getSrcModExt <ValueType VT> {
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bit isFP = !if(!eq(VT.Value, f16.Value), 1,
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!if(!eq(VT.Value, f32.Value), 1,
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!if(!eq(VT.Value, f64.Value), 1,
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0)));
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bit isFP = getIsFP<VT>.ret;
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Operand ret = !if(isFP, FPVRegInputMods, IntVRegInputMods);
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}
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@ -0,0 +1,447 @@
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# RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs -run-pass post-RA-hazard-rec -o - %s | FileCheck -check-prefix=GCN %s
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# GCN-LABEL: name: flat_atomic_fcmpswap_to_s_denorm_mode
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# GCN: FLAT_ATOMIC_FCMPSWAP
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# GCN-NEXT: S_NOP 0
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# GCN-NEXT: S_NOP 0
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# GCN-NEXT: S_NOP 0
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# GCN-NEXT: S_DENORM_MODE
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---
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name: flat_atomic_fcmpswap_to_s_denorm_mode
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body: |
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bb.0:
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FLAT_ATOMIC_FCMPSWAP undef %0:vreg_64, undef %1:vreg_64, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
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S_DENORM_MODE 0
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...
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# GCN-LABEL: name: flat_atomic_fcmpswap_x2_to_s_denorm_mode
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# GCN: FLAT_ATOMIC_FCMPSWAP_X2
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# GCN-NEXT: S_NOP 0
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# GCN-NEXT: S_NOP 0
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# GCN-NEXT: S_NOP 0
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# GCN-NEXT: S_DENORM_MODE
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---
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name: flat_atomic_fcmpswap_x2_to_s_denorm_mode
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body: |
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bb.0:
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FLAT_ATOMIC_FCMPSWAP_X2 undef %0:vreg_64, undef %1:vreg_128, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
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S_DENORM_MODE 0
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...
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# GCN-LABEL: name: flat_atomic_fmax_to_s_denorm_mode
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# GCN: FLAT_ATOMIC_FMAX
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# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_DENORM_MODE
|
||||
---
|
||||
name: flat_atomic_fmax_to_s_denorm_mode
|
||||
body: |
|
||||
bb.0:
|
||||
FLAT_ATOMIC_FMAX undef %0:vreg_64, undef %1:vgpr_32, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
|
||||
S_DENORM_MODE 0
|
||||
...
|
||||
|
||||
# GCN-LABEL: name: flat_atomic_fmax_x2_to_s_denorm_mode
|
||||
# GCN: FLAT_ATOMIC_FMAX_X2
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_DENORM_MODE
|
||||
---
|
||||
name: flat_atomic_fmax_x2_to_s_denorm_mode
|
||||
body: |
|
||||
bb.0:
|
||||
FLAT_ATOMIC_FMAX_X2 undef %0:vreg_64, undef %1:vreg_64, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
|
||||
S_DENORM_MODE 0
|
||||
...
|
||||
|
||||
# GCN-LABEL: name: flat_atomic_fmin_to_s_denorm_mode
|
||||
# GCN: FLAT_ATOMIC_FMIN
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_DENORM_MODE
|
||||
---
|
||||
name: flat_atomic_fmin_to_s_denorm_mode
|
||||
body: |
|
||||
bb.0:
|
||||
FLAT_ATOMIC_FMIN undef %0:vreg_64, undef %1:vgpr_32, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
|
||||
S_DENORM_MODE 0
|
||||
...
|
||||
|
||||
# GCN-LABEL: name: flat_atomic_fmin_x2_to_s_denorm_mode
|
||||
# GCN: FLAT_ATOMIC_FMIN_X2
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_DENORM_MODE
|
||||
---
|
||||
name: flat_atomic_fmin_x2_to_s_denorm_mode
|
||||
body: |
|
||||
bb.0:
|
||||
FLAT_ATOMIC_FMIN_X2 undef %0:vreg_64, undef %1:vreg_64, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
|
||||
S_DENORM_MODE 0
|
||||
...
|
||||
|
||||
# GCN-LABEL: name: flat_atomic_fcmpswap_x2_rtn_to_s_denorm_mode
|
||||
# GCN: FLAT_ATOMIC_FCMPSWAP_X2_RTN
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_DENORM_MODE
|
||||
---
|
||||
name: flat_atomic_fcmpswap_x2_rtn_to_s_denorm_mode
|
||||
body: |
|
||||
bb.0:
|
||||
%2:vreg_64 = FLAT_ATOMIC_FCMPSWAP_X2_RTN undef %0:vreg_64, undef %1:vreg_128, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
|
||||
S_DENORM_MODE 0
|
||||
...
|
||||
|
||||
# GCN-LABEL: name: flat_atomic_fmax_rtn_to_s_denorm_mode
|
||||
# GCN: FLAT_ATOMIC_FMAX_RTN
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_DENORM_MODE
|
||||
---
|
||||
name: flat_atomic_fmax_rtn_to_s_denorm_mode
|
||||
body: |
|
||||
bb.0:
|
||||
%2:vgpr_32 = FLAT_ATOMIC_FMAX_RTN undef %0:vreg_64, undef %1:vgpr_32, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
|
||||
S_DENORM_MODE 0
|
||||
...
|
||||
|
||||
# GCN-LABEL: name: flat_atomic_fmax_x2_rtn_to_s_denorm_mode
|
||||
# GCN: FLAT_ATOMIC_FMAX_X2_RTN
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_DENORM_MODE
|
||||
---
|
||||
name: flat_atomic_fmax_x2_rtn_to_s_denorm_mode
|
||||
body: |
|
||||
bb.0:
|
||||
%2:vreg_64 = FLAT_ATOMIC_FMAX_X2_RTN undef %0:vreg_64, undef %1:vreg_64, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
|
||||
S_DENORM_MODE 0
|
||||
...
|
||||
|
||||
# GCN-LABEL: name: flat_atomic_fmin_rtn_to_s_denorm_mode
|
||||
# GCN: FLAT_ATOMIC_FMIN_RTN
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_DENORM_MODE
|
||||
---
|
||||
name: flat_atomic_fmin_rtn_to_s_denorm_mode
|
||||
body: |
|
||||
bb.0:
|
||||
%2:vgpr_32 = FLAT_ATOMIC_FMIN_RTN undef %0:vreg_64, undef %1:vgpr_32, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
|
||||
S_DENORM_MODE 0
|
||||
...
|
||||
|
||||
# GCN-LABEL: name: flat_atomic_fmin_x2_rtn_to_s_denorm_mode
|
||||
# GCN: FLAT_ATOMIC_FMIN_X2_RTN
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_DENORM_MODE
|
||||
---
|
||||
name: flat_atomic_fmin_x2_rtn_to_s_denorm_mode
|
||||
body: |
|
||||
bb.0:
|
||||
%2:vreg_64 = FLAT_ATOMIC_FMIN_X2_RTN undef %0:vreg_64, undef %1:vreg_64, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
|
||||
S_DENORM_MODE 0
|
||||
...
|
||||
|
||||
# GCN-LABEL: name: flat_atomic_fcmpswap_rtn_to_s_denorm_mode
|
||||
# GCN: FLAT_ATOMIC_FCMPSWAP_RTN
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_DENORM_MODE
|
||||
---
|
||||
name: flat_atomic_fcmpswap_rtn_to_s_denorm_mode
|
||||
body: |
|
||||
bb.0:
|
||||
%2:vgpr_32 = FLAT_ATOMIC_FCMPSWAP_RTN undef %0:vreg_64, undef %1:vreg_64, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
|
||||
S_DENORM_MODE 0
|
||||
...
|
||||
|
||||
# GCN-LABEL: name: global_atomic_fcmpswap_to_s_denorm_mode
|
||||
# GCN: GLOBAL_ATOMIC_FCMPSWAP
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_DENORM_MODE
|
||||
---
|
||||
name: global_atomic_fcmpswap_to_s_denorm_mode
|
||||
body: |
|
||||
bb.0:
|
||||
GLOBAL_ATOMIC_FCMPSWAP undef %0:vreg_64, undef %1:vgpr_32, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
|
||||
S_DENORM_MODE 0
|
||||
...
|
||||
|
||||
# GCN-LABEL: name: global_atomic_fcmpswap_x2_to_s_denorm_mode
|
||||
# GCN: GLOBAL_ATOMIC_FCMPSWAP_X2
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_DENORM_MODE
|
||||
---
|
||||
name: global_atomic_fcmpswap_x2_to_s_denorm_mode
|
||||
body: |
|
||||
bb.0:
|
||||
GLOBAL_ATOMIC_FCMPSWAP_X2 undef %0:vreg_64, undef %1:vreg_64, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
|
||||
S_DENORM_MODE 0
|
||||
...
|
||||
|
||||
# GCN-LABEL: name: global_atomic_fmax_to_s_denorm_mode
|
||||
# GCN: GLOBAL_ATOMIC_FMAX
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_DENORM_MODE
|
||||
---
|
||||
name: global_atomic_fmax_to_s_denorm_mode
|
||||
body: |
|
||||
bb.0:
|
||||
GLOBAL_ATOMIC_FMAX undef %0:vreg_64, undef %1:vgpr_32, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
|
||||
S_DENORM_MODE 0
|
||||
...
|
||||
|
||||
# GCN-LABEL: name: global_atomic_fmax_x2_to_s_denorm_mode
|
||||
# GCN: GLOBAL_ATOMIC_FMAX_X2
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_DENORM_MODE
|
||||
---
|
||||
name: global_atomic_fmax_x2_to_s_denorm_mode
|
||||
body: |
|
||||
bb.0:
|
||||
GLOBAL_ATOMIC_FMAX_X2 undef %0:vreg_64, undef %1:vreg_64, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
|
||||
S_DENORM_MODE 0
|
||||
...
|
||||
|
||||
# GCN-LABEL: name: global_atomic_fmin_to_s_denorm_mode
|
||||
# GCN: GLOBAL_ATOMIC_FMIN
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_DENORM_MODE
|
||||
---
|
||||
name: global_atomic_fmin_to_s_denorm_mode
|
||||
body: |
|
||||
bb.0:
|
||||
GLOBAL_ATOMIC_FMIN undef %0:vreg_64, undef %1:vgpr_32, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
|
||||
S_DENORM_MODE 0
|
||||
...
|
||||
|
||||
# GCN-LABEL: name: global_atomic_fmin_x2_to_s_denorm_mode
|
||||
# GCN: GLOBAL_ATOMIC_FMIN_X2
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_DENORM_MODE
|
||||
---
|
||||
name: global_atomic_fmin_x2_to_s_denorm_mode
|
||||
body: |
|
||||
bb.0:
|
||||
GLOBAL_ATOMIC_FMIN_X2 undef %0:vreg_64, undef %1:vreg_64, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
|
||||
S_DENORM_MODE 0
|
||||
...
|
||||
|
||||
# GCN-LABEL: name: global_atomic_fcmpswap_rtn_to_s_denorm_mode
|
||||
# GCN: GLOBAL_ATOMIC_FCMPSWAP_RTN
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_DENORM_MODE
|
||||
---
|
||||
name: global_atomic_fcmpswap_rtn_to_s_denorm_mode
|
||||
body: |
|
||||
bb.0:
|
||||
%2:vgpr_32 = GLOBAL_ATOMIC_FCMPSWAP_RTN undef %0:vreg_64, undef %1:vgpr_32, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
|
||||
S_DENORM_MODE 0
|
||||
...
|
||||
|
||||
# GCN-LABEL: name: global_atomic_fcmpswap_x2_rtn_to_s_denorm_mode
|
||||
# GCN: GLOBAL_ATOMIC_FCMPSWAP_X2_RTN
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_DENORM_MODE
|
||||
---
|
||||
name: global_atomic_fcmpswap_x2_rtn_to_s_denorm_mode
|
||||
body: |
|
||||
bb.0:
|
||||
%2:vreg_64 = GLOBAL_ATOMIC_FCMPSWAP_X2_RTN undef %0:vreg_64, undef %1:vreg_64, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
|
||||
S_DENORM_MODE 0
|
||||
...
|
||||
|
||||
# GCN-LABEL: name: global_atomic_fmax_rtn_to_s_denorm_mode
|
||||
# GCN: GLOBAL_ATOMIC_FMAX_RTN
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_DENORM_MODE
|
||||
---
|
||||
name: global_atomic_fmax_rtn_to_s_denorm_mode
|
||||
body: |
|
||||
bb.0:
|
||||
%2:vgpr_32 = GLOBAL_ATOMIC_FMAX_RTN undef %0:vreg_64, undef %1:vgpr_32, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
|
||||
S_DENORM_MODE 0
|
||||
...
|
||||
|
||||
# GCN-LABEL: name: global_atomic_fmax_x2_rtn_to_s_denorm_mode
|
||||
# GCN: GLOBAL_ATOMIC_FMAX_X2_RTN
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_DENORM_MODE
|
||||
---
|
||||
name: global_atomic_fmax_x2_rtn_to_s_denorm_mode
|
||||
body: |
|
||||
bb.0:
|
||||
%2:vreg_64 = GLOBAL_ATOMIC_FMAX_X2_RTN undef %0:vreg_64, undef %1:vreg_64, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
|
||||
S_DENORM_MODE 0
|
||||
...
|
||||
|
||||
# GCN-LABEL: name: global_atomic_fmin_rtn_to_s_denorm_mode
|
||||
# GCN: GLOBAL_ATOMIC_FMIN_RTN
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_DENORM_MODE
|
||||
---
|
||||
name: global_atomic_fmin_rtn_to_s_denorm_mode
|
||||
body: |
|
||||
bb.0:
|
||||
%2:vgpr_32 = GLOBAL_ATOMIC_FMIN_RTN undef %0:vreg_64, undef %1:vgpr_32, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
|
||||
S_DENORM_MODE 0
|
||||
...
|
||||
|
||||
# GCN-LABEL: name: global_atomic_fmin_x2_rtn_to_s_denorm_mode
|
||||
# GCN: GLOBAL_ATOMIC_FMIN_X2_RTN
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_DENORM_MODE
|
||||
---
|
||||
name: global_atomic_fmin_x2_rtn_to_s_denorm_mode
|
||||
body: |
|
||||
bb.0:
|
||||
%2:vreg_64 = GLOBAL_ATOMIC_FMIN_X2_RTN undef %0:vreg_64, undef %1:vreg_64, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
|
||||
S_DENORM_MODE 0
|
||||
...
|
||||
|
||||
# GCN-LABEL: name: global_atomic_fcmpswap_saddr_to_s_denorm_mode
|
||||
# GCN: GLOBAL_ATOMIC_FCMPSWAP_SADDR
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_DENORM_MODE
|
||||
---
|
||||
name: global_atomic_fcmpswap_saddr_to_s_denorm_mode
|
||||
body: |
|
||||
bb.0:
|
||||
GLOBAL_ATOMIC_FCMPSWAP_SADDR undef %0:vreg_64, undef %1:vgpr_32, undef %3:sgpr_64, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
|
||||
S_DENORM_MODE 0
|
||||
...
|
||||
|
||||
# GCN-LABEL: name: global_atomic_fcmpswap_x2_saddr_rtn_to_s_denorm_mode
|
||||
# GCN: GLOBAL_ATOMIC_FCMPSWAP_X2_SADDR_RTN
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_DENORM_MODE
|
||||
---
|
||||
name: global_atomic_fcmpswap_x2_saddr_rtn_to_s_denorm_mode
|
||||
body: |
|
||||
bb.0:
|
||||
%2:vreg_64 = GLOBAL_ATOMIC_FCMPSWAP_X2_SADDR_RTN undef %0:vreg_64, undef %1:vreg_64, undef %3:sgpr_64, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
|
||||
S_DENORM_MODE 0
|
||||
...
|
||||
|
||||
# GCN-LABEL: name: global_atomic_fmax_saddr_rtn_to_s_denorm_mode
|
||||
# GCN: GLOBAL_ATOMIC_FMAX_SADDR_RTN
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_DENORM_MODE
|
||||
---
|
||||
name: global_atomic_fmax_saddr_rtn_to_s_denorm_mode
|
||||
body: |
|
||||
bb.0:
|
||||
%2:vgpr_32 = GLOBAL_ATOMIC_FMAX_SADDR_RTN undef %0:vreg_64, undef %1:vgpr_32, undef %3:sgpr_64, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
|
||||
S_DENORM_MODE 0
|
||||
...
|
||||
|
||||
# GCN-LABEL: name: global_atomic_fmax_x2_saddr_rtn_to_s_denorm_mode
|
||||
# GCN: GLOBAL_ATOMIC_FMAX_X2_SADDR_RTN
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_DENORM_MODE
|
||||
---
|
||||
name: global_atomic_fmax_x2_saddr_rtn_to_s_denorm_mode
|
||||
body: |
|
||||
bb.0:
|
||||
%2:vreg_64 = GLOBAL_ATOMIC_FMAX_X2_SADDR_RTN undef %0:vreg_64, undef %1:vreg_64, undef %3:sgpr_64, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
|
||||
S_DENORM_MODE 0
|
||||
...
|
||||
|
||||
# GCN-LABEL: name: global_atomic_fmin_saddr_rtn_to_s_denorm_mode
|
||||
# GCN: GLOBAL_ATOMIC_FMIN_SADDR_RTN
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_DENORM_MODE
|
||||
---
|
||||
name: global_atomic_fmin_saddr_rtn_to_s_denorm_mode
|
||||
body: |
|
||||
bb.0:
|
||||
%2:vgpr_32 = GLOBAL_ATOMIC_FMIN_SADDR_RTN undef %0:vreg_64, undef %1:vgpr_32, undef %3:sgpr_64, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
|
||||
S_DENORM_MODE 0
|
||||
...
|
||||
|
||||
# GCN-LABEL: name: global_atomic_fmin_x2_saddr_rtn_to_s_denorm_mode
|
||||
# GCN: GLOBAL_ATOMIC_FMIN_X2_SADDR_RTN
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_NOP 0
|
||||
# GCN-NEXT: S_DENORM_MODE
|
||||
---
|
||||
name: global_atomic_fmin_x2_saddr_rtn_to_s_denorm_mode
|
||||
body: |
|
||||
bb.0:
|
||||
%2:vreg_64 = GLOBAL_ATOMIC_FMIN_X2_SADDR_RTN undef %0:vreg_64, undef %1:vreg_64, undef %3:sgpr_64, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
|
||||
S_DENORM_MODE 0
|
||||
...
|
||||
|
||||
# GCN-LABEL: name: flat_fp_atomic_to_s_denorm_mode_waitcnt
|
||||
# GCN: FLAT_ATOMIC_FMIN
|
||||
# GCN-NEXT: S_WAITCNT
|
||||
# GCN-NEXT: S_DENORM_MODE
|
||||
---
|
||||
name: flat_fp_atomic_to_s_denorm_mode_waitcnt
|
||||
body: |
|
||||
bb.0:
|
||||
FLAT_ATOMIC_FMIN undef %0:vreg_64, undef %1:vgpr_32, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
|
||||
S_WAITCNT 0
|
||||
S_DENORM_MODE 0
|
||||
...
|
||||
|
||||
# GCN-LABEL: name: flat_fp_atomic_to_s_denorm_mode_valu
|
||||
# GCN: FLAT_ATOMIC_FMIN
|
||||
# GCN-NEXT: V_ADD_F32_e32
|
||||
# GCN-NEXT: S_DENORM_MODE
|
||||
---
|
||||
name: flat_fp_atomic_to_s_denorm_mode_valu
|
||||
body: |
|
||||
bb.0:
|
||||
FLAT_ATOMIC_FMIN undef %0:vreg_64, undef %1:vgpr_32, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
|
||||
%2:vgpr_32 = V_ADD_F32_e32 undef %1:vgpr_32, undef %1:vgpr_32, implicit $exec
|
||||
S_DENORM_MODE 0
|
||||
...
|
||||
Loading…
Reference in New Issue