forked from OSchip/llvm-project
parent
2495bca543
commit
bdf39a46a3
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@ -478,7 +478,7 @@ NVPTXAsmPrinter::getVirtualRegisterName(unsigned vr, bool isVec,
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<< getNVPTXRegClassStr(RC) << mapped_vr << "_1"
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<< "}";
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else
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assert(0 && "Unsupported vector size");
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llvm_unreachable("Unsupported vector size");
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}
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void
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@ -519,7 +519,7 @@ void NVPTXAsmPrinter::printVecModifiedImmediate(const MachineOperand &MO,
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O << "_" << vecelem[Imm%2];
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}
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else
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assert(0 && "Unknown Modifier on immediate operand");
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llvm_unreachable("Unknown Modifier on immediate operand");
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}
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void NVPTXAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
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@ -539,7 +539,7 @@ void NVPTXAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
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if (strcmp(Modifier, "vecfull") == 0)
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emitVirtualRegister(MO.getReg(), true, O);
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else
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assert(0 &&
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llvm_unreachable(
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"Don't know how to handle the modifier on virtual register.");
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}
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}
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@ -551,7 +551,7 @@ void NVPTXAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
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else if (strstr(Modifier, "vec") == Modifier)
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printVecModifiedImmediate(MO, Modifier, O);
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else
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assert(0 && "Don't know how to handle modifier on immediate operand");
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llvm_unreachable("Don't know how to handle modifier on immediate operand");
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return;
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case MachineOperand::MO_FPImmediate:
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@ -584,7 +584,7 @@ void NVPTXAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
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return;
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default:
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assert(0 && " Operand type not supported.");
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llvm_unreachable("Operand type not supported.");
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}
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}
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@ -1257,7 +1257,7 @@ void NVPTXAsmPrinter::emitPTXAddressSpace(unsigned int AddressSpace,
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O << "shared" ;
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break;
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default:
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assert(0 && "unexpected address space");
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llvm_unreachable("unexpected address space");
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}
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}
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@ -1748,8 +1748,7 @@ void NVPTXAsmPrinter::bufferLEByte(Constant *CPV, int Bytes,
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ptr = (unsigned char*)&int32;
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aggBuffer->addBytes(ptr, 4, Bytes);
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break;
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}
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else if (ConstantExpr *Cexpr = dyn_cast<ConstantExpr>(CPV)) {
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} else if (ConstantExpr *Cexpr = dyn_cast<ConstantExpr>(CPV)) {
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if (ConstantInt *constInt =
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dyn_cast<ConstantInt>(ConstantFoldConstantExpression(
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Cexpr, TD))) {
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@ -1765,15 +1764,14 @@ void NVPTXAsmPrinter::bufferLEByte(Constant *CPV, int Bytes,
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break;
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}
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}
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assert(0 && "unsupported integer const type");
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llvm_unreachable("unsupported integer const type");
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} else if (ETy == Type::getInt64Ty(CPV->getContext()) ) {
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if (ConstantInt *constInt = dyn_cast<ConstantInt>(CPV)) {
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long long int64 =(long long)(constInt->getZExtValue());
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ptr = (unsigned char*)&int64;
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aggBuffer->addBytes(ptr, 8, Bytes);
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break;
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}
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else if (ConstantExpr *Cexpr = dyn_cast<ConstantExpr>(CPV)) {
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} else if (ConstantExpr *Cexpr = dyn_cast<ConstantExpr>(CPV)) {
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if (ConstantInt *constInt = dyn_cast<ConstantInt>(
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ConstantFoldConstantExpression(Cexpr, TD))) {
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long long int64 =(long long)(constInt->getZExtValue());
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@ -1789,8 +1787,7 @@ void NVPTXAsmPrinter::bufferLEByte(Constant *CPV, int Bytes,
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}
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}
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llvm_unreachable("unsupported integer const type");
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}
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else
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} else
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llvm_unreachable("unsupported integer const type");
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break;
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}
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@ -1887,7 +1884,7 @@ void NVPTXAsmPrinter::bufferAggregateConstant(Constant *CPV,
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}
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return;
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}
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assert(0 && "unsupported constant type in printAggregateConstant()");
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llvm_unreachable("unsupported constant type in printAggregateConstant()");
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}
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// buildTypeNameMap - Run through symbol table looking for type names.
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@ -148,8 +148,7 @@ class LLVM_LIBRARY_VISIBILITY NVPTXAsmPrinter : public AsmPrinter {
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O << ", ";
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O << (unsigned int)buffer[i];
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}
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}
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else {
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} else {
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// print out in 4-bytes or 8-bytes
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unsigned int pos = 0;
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unsigned int nSym = 0;
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@ -169,16 +168,14 @@ class LLVM_LIBRARY_VISIBILITY NVPTXAsmPrinter : public AsmPrinter {
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else if (ConstantExpr *Cexpr =
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dyn_cast<ConstantExpr>(v)) {
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O << *nvptx::LowerConstant(Cexpr, AP);
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}
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else
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assert(0 && "symbol type unknown");
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} else
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llvm_unreachable("symbol type unknown");
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nSym++;
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if (nSym >= numSymbols)
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nextSymbolPos = size+1;
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else
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nextSymbolPos = symbolPosInBuffer[nSym];
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}
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else
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} else
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if (nBytes == 4)
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O << *(unsigned int*)(buffer+pos);
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else
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@ -106,7 +106,7 @@ void NVPTXInstrInfo::copyPhysReg (MachineBasicBlock &MBB,
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BuildMI(MBB, I, DL, get(NVPTX::V2f64Mov), DestReg)
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.addReg(SrcReg, getKillRegState(KillSrc));
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else {
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assert(0 && "Don't know how to copy a register");
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llvm_unreachable("Don't know how to copy a register");
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}
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}
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@ -196,8 +196,7 @@ std::string getNVPTXElemClassName(TargetRegisterClass const *RC) {
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return getNVPTXRegClassName(&NVPTX::Int32RegsRegClass);
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if (RC->getID() == NVPTX::V4I8RegsRegClassID)
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return getNVPTXRegClassName(&NVPTX::Int8RegsRegClass);
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assert(0 && "Not a vector register class");
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return "Unsupported";
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llvm_unreachable("Not a vector register class");
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}
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const TargetRegisterClass *getNVPTXElemClass(TargetRegisterClass const *RC) {
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@ -221,8 +220,7 @@ const TargetRegisterClass *getNVPTXElemClass(TargetRegisterClass const *RC) {
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return (&NVPTX::Int32RegsRegClass);
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if (RC->getID() == NVPTX::V4I8RegsRegClassID)
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return (&NVPTX::Int8RegsRegClass);
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assert(0 && "Not a vector register class");
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return 0;
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llvm_unreachable("Not a vector register class");
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}
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int getNVPTXVectorSize(TargetRegisterClass const *RC) {
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@ -246,8 +244,7 @@ int getNVPTXVectorSize(TargetRegisterClass const *RC) {
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return 4;
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if (RC->getID() == NVPTX::V4I8RegsRegClassID)
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return 4;
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assert(0 && "Not a vector register class");
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return -1;
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llvm_unreachable("Not a vector register class");
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}
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}
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@ -731,9 +731,7 @@ unsigned VectorElementize::getScalarVersion(unsigned opcode) {
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if (opcode == NVPTX::IMPLICIT_DEF)
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return opcode;
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switch(opcode) {
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default:
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assert(0 && "Scalar version not set, fix NVPTXVector.td");
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return 0;
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default: llvm_unreachable("Scalar version not set, fix NVPTXVector.td");
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case TargetOpcode::COPY: return TargetOpcode::COPY;
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case NVPTX::AddCCCV2I32: return NVPTX::ADDCCCi32rr;
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case NVPTX::AddCCCV4I32: return NVPTX::ADDCCCi32rr;
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