forked from OSchip/llvm-project
[AArch64] Add support for NEON scalar shift immediate instructions.
llvm-svn: 193791
This commit is contained in:
Chad Rosier
parent
20e1f20d69
commit
bdca387884
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@ -106,6 +106,7 @@ class Inst <string n, string p, string t, Op o> {
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string Types = t;
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Op Operand = o;
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bit isShift = 0;
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bit isScalarShift = 0;
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bit isVCVT_N = 0;
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bit isA64 = 0;
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@ -784,6 +785,41 @@ def SCALAR_QRSHL: SInst<"vqrshl", "sss", "ScSsSiSlSUcSUsSUiSUl">;
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// Scalar Shift Rouding Left
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def SCALAR_RSHL: SInst<"vrshl", "sss", "SlSUl">;
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////////////////////////////////////////////////////////////////////////////////
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// Scalar Shift (Immediate)
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let isScalarShift = 1 in {
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// Signed/Unsigned Shift Right (Immediate)
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def SCALAR_SSHR_N: SInst<"vshr_n", "ssi", "SlSUl">;
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// Signed/Unsigned Rounding Shift Right (Immediate)
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def SCALAR_SRSHR_N: SInst<"vrshr_n", "ssi", "SlSUl">;
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// Signed/Unsigned Shift Right and Accumulate (Immediate)
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def SCALAR_SSRA_N: SInst<"vsra_n", "sssi", "SlSUl">;
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// Signed/Unsigned Rounding Shift Right and Accumulate (Immediate)
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def SCALAR_SRSRA_N: SInst<"vrsra_n", "sssi", "SlSUl">;
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// Shift Left (Immediate)
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def SCALAR_SHL_N: SInst<"vshl_n", "ssi", "SlSUl">;
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// Signed/Unsigned Saturating Shift Left (Immediate)
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def SCALAR_SQSHL_N: SInst<"vqshl_n", "ssi", "ScSsSiSlSUcSUsSUiSUl">;
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// Signed Saturating Shift Left Unsigned (Immediate)
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def SCALAR_SQSHLU_N: SInst<"vqshlu_n", "ssi", "ScSsSiSl">;
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// Shift Right And Insert (Immediate)
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def SCALAR_SRI_N: SInst<"vsri_n", "ssi", "SlSUl">;
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// Shift Left And Insert (Immediate)
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def SCALAR_SLI_N: SInst<"vsli_n", "ssi", "SlSUl">;
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// Signed/Unsigned Saturating Shift Right Narrow (Immediate)
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def SCALAR_SQSHRN_N: SInst<"vqshrn_n", "zsi", "SsSiSlSUsSUiSUl">;
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// Signed/Unsigned Saturating Rounded Shift Right Narrow (Immediate)
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def SCALAR_SQRSHRN_N: SInst<"vqrshrn_n", "zsi", "SsSiSlSUsSUiSUl">;
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// Signed Saturating Shift Right Unsigned Narrow (Immediate)
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def SCALAR_SQSHRUN_N: SInst<"vqshrun_n", "zsi", "SsSiSl">;
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// Signed Saturating Rounded Shift Right Unsigned Narrow (Immediate)
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def SCALAR_SQRSHRUN_N: SInst<"vqrshrun_n", "zsi", "SsSiSl">;
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}
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////////////////////////////////////////////////////////////////////////////////
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// Scalar Reduce Pairwise Addition (Scalar and Floating Point)
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def SCALAR_ADDP : SInst<"vpadd", "sd", "SfSHlSHd">;
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@ -2227,6 +2227,110 @@ static Value *EmitAArch64ScalarBuiltinExpr(CodeGenFunction &CGF,
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case AArch64::BI__builtin_neon_vqmovnd_u64:
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Int = Intrinsic::arm_neon_vqmovnu;
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s = "vqmovn"; OverloadNarrowInt = true; break;
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// Scalar Signed Shift Right (Immediate)
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case AArch64::BI__builtin_neon_vshrd_n_s64:
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Int = Intrinsic::aarch64_neon_vshrds_n;
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s = "vsshr"; OverloadInt = false; break;
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// Scalar Unsigned Shift Right (Immediate)
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case AArch64::BI__builtin_neon_vshrd_n_u64:
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Int = Intrinsic::aarch64_neon_vshrdu_n;
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s = "vushr"; OverloadInt = false; break;
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// Scalar Signed Rounding Shift Right (Immediate)
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case AArch64::BI__builtin_neon_vrshrd_n_s64:
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Int = Intrinsic::aarch64_neon_vrshrds_n;
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s = "vsrshr"; OverloadInt = false; break;
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// Scalar Unsigned Rounding Shift Right (Immediate)
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case AArch64::BI__builtin_neon_vrshrd_n_u64:
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Int = Intrinsic::aarch64_neon_vrshrdu_n;
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s = "vurshr"; OverloadInt = false; break;
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// Scalar Signed Shift Right and Accumulate (Immediate)
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case AArch64::BI__builtin_neon_vsrad_n_s64:
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Int = Intrinsic::aarch64_neon_vsrads_n;
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s = "vssra"; OverloadInt = false; break;
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// Scalar Unsigned Shift Right and Accumulate (Immediate)
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case AArch64::BI__builtin_neon_vsrad_n_u64:
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Int = Intrinsic::aarch64_neon_vsradu_n;
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s = "vusra"; OverloadInt = false; break;
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// Scalar Signed Rounding Shift Right and Accumulate (Immediate)
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case AArch64::BI__builtin_neon_vrsrad_n_s64:
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Int = Intrinsic::aarch64_neon_vrsrads_n;
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s = "vsrsra"; OverloadInt = false; break;
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// Scalar Unsigned Rounding Shift Right and Accumulate (Immediate)
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case AArch64::BI__builtin_neon_vrsrad_n_u64:
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Int = Intrinsic::aarch64_neon_vrsradu_n;
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s = "vursra"; OverloadInt = false; break;
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// Scalar Signed/Unsigned Shift Left (Immediate)
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case AArch64::BI__builtin_neon_vshld_n_s64:
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case AArch64::BI__builtin_neon_vshld_n_u64:
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Int = Intrinsic::aarch64_neon_vshld_n;
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s = "vshl"; OverloadInt = false; break;
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// Signed Saturating Shift Left (Immediate)
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case AArch64::BI__builtin_neon_vqshlb_n_s8:
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case AArch64::BI__builtin_neon_vqshlh_n_s16:
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case AArch64::BI__builtin_neon_vqshls_n_s32:
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case AArch64::BI__builtin_neon_vqshld_n_s64:
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Int = Intrinsic::aarch64_neon_vqshls_n;
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s = "vsqshl"; OverloadInt = true; break;
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// Unsigned Saturating Shift Left (Immediate)
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case AArch64::BI__builtin_neon_vqshlb_n_u8:
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case AArch64::BI__builtin_neon_vqshlh_n_u16:
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case AArch64::BI__builtin_neon_vqshls_n_u32:
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case AArch64::BI__builtin_neon_vqshld_n_u64:
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Int = Intrinsic::aarch64_neon_vqshlu_n;
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s = "vuqshl"; OverloadInt = true; break;
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// Signed Saturating Shift Left Unsigned (Immediate)
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case AArch64::BI__builtin_neon_vqshlub_n_s8:
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case AArch64::BI__builtin_neon_vqshluh_n_s16:
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case AArch64::BI__builtin_neon_vqshlus_n_s32:
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case AArch64::BI__builtin_neon_vqshlud_n_s64:
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Int = Intrinsic::aarch64_neon_vqshlus_n;
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s = "vsqshlu"; OverloadInt = true; break;
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// Shift Right And Insert (Immediate)
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case AArch64::BI__builtin_neon_vsrid_n_s64:
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case AArch64::BI__builtin_neon_vsrid_n_u64:
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Int = Intrinsic::aarch64_neon_vsrid_n;
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s = "vsri"; OverloadInt = false; break;
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// Shift Left And Insert (Immediate)
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case AArch64::BI__builtin_neon_vslid_n_s64:
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case AArch64::BI__builtin_neon_vslid_n_u64:
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Int = Intrinsic::aarch64_neon_vslid_n;
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s = "vsli"; OverloadInt = false; break;
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// Signed Saturating Shift Right Narrow (Immediate)
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case AArch64::BI__builtin_neon_vqshrnh_n_s16:
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case AArch64::BI__builtin_neon_vqshrns_n_s32:
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case AArch64::BI__builtin_neon_vqshrnd_n_s64:
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Int = Intrinsic::aarch64_neon_vsqshrn;
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s = "vsqshrn"; OverloadInt = true; break;
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// Unsigned Saturating Shift Right Narrow (Immediate)
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case AArch64::BI__builtin_neon_vqshrnh_n_u16:
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case AArch64::BI__builtin_neon_vqshrns_n_u32:
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case AArch64::BI__builtin_neon_vqshrnd_n_u64:
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Int = Intrinsic::aarch64_neon_vuqshrn;
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s = "vuqshrn"; OverloadInt = true; break;
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// Signed Saturating Rounded Shift Right Narrow (Immediate)
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case AArch64::BI__builtin_neon_vqrshrnh_n_s16:
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case AArch64::BI__builtin_neon_vqrshrns_n_s32:
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case AArch64::BI__builtin_neon_vqrshrnd_n_s64:
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Int = Intrinsic::aarch64_neon_vsqrshrn;
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s = "vsqrshrn"; OverloadInt = true; break;
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// Unsigned Saturating Rounded Shift Right Narrow (Immediate)
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case AArch64::BI__builtin_neon_vqrshrnh_n_u16:
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case AArch64::BI__builtin_neon_vqrshrns_n_u32:
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case AArch64::BI__builtin_neon_vqrshrnd_n_u64:
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Int = Intrinsic::aarch64_neon_vuqrshrn;
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s = "vuqrshrn"; OverloadInt = true; break;
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// Signed Saturating Shift Right Unsigned Narrow (Immediate)
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case AArch64::BI__builtin_neon_vqshrunh_n_s16:
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case AArch64::BI__builtin_neon_vqshruns_n_s32:
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case AArch64::BI__builtin_neon_vqshrund_n_s64:
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Int = Intrinsic::aarch64_neon_vsqshrun;
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s = "vsqshrun"; OverloadInt = true; break;
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// Signed Saturating Rounded Shift Right Unsigned Narrow (Immediate)
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case AArch64::BI__builtin_neon_vqrshrunh_n_s16:
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case AArch64::BI__builtin_neon_vqrshruns_n_s32:
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case AArch64::BI__builtin_neon_vqrshrund_n_s64:
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Int = Intrinsic::aarch64_neon_vsqrshrun;
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s = "vsqrshrun"; OverloadInt = true; break;
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}
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if (!Int)
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@ -2254,8 +2358,7 @@ static Value *EmitAArch64ScalarBuiltinExpr(CodeGenFunction &CGF,
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assert(E->getNumArgs() == 1);
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} else if (OverloadInt) {
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// Determine the type of this overloaded AArch64 intrinsic
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const Expr *Arg = E->getArg(E->getNumArgs()-1);
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llvm::Type *Ty = CGF.ConvertType(Arg->getType());
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llvm::Type *Ty = CGF.ConvertType(E->getCallReturnType());
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llvm::VectorType *VTy = llvm::VectorType::get(Ty, 1);
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assert(VTy);
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@ -7484,3 +7484,266 @@ uint64_t test_vcaltd_f64(float64_t a, float64_t b) {
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return (uint64_t)vcaltd_f64(a, b);
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}
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int64_t test_vshrd_n_s64(int64_t a) {
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// CHECK-LABEL: test_vshrd_n_s64
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// CHECK: sshr {{d[0-9]+}}, {{d[0-9]+}}, #1
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return (int64_t)vshrd_n_s64(a, 1);
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}
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uint64_t test_vshrd_n_u64(uint64_t a) {
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// CHECK-LABEL: test_vshrd_n_u64
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// CHECK: ushr {{d[0-9]+}}, {{d[0-9]+}}, #64
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return (uint64_t)vshrd_n_u64(a, 64);
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}
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int64_t test_vrshrd_n_s64(int64_t a) {
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// CHECK-LABEL: test_vrshrd_n_s64
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// CHECK: srshr {{d[0-9]+}}, {{d[0-9]+}}, #63
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return (int64_t)vrshrd_n_s64(a, 63);
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}
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uint64_t test_vrshrd_n_u64(uint64_t a) {
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// CHECK-LABEL: test_vrshrd_n_u64
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// CHECK: urshr {{d[0-9]+}}, {{d[0-9]+}}, #63
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return (uint64_t)vrshrd_n_u64(a, 63);
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}
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int64_t test_vsrad_n_s64(int64_t a, int64_t b) {
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// CHECK-LABEL: test_vsrad_n_s64
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// CHECK: ssra {{d[0-9]+}}, {{d[0-9]+}}, #63
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return (int64_t)vsrad_n_s64(a, b, 63);
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}
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uint64_t test_vsrad_n_u64(uint64_t a, uint64_t b) {
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// CHECK-LABEL: test_vsrad_n_u64
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// CHECK: usra {{d[0-9]+}}, {{d[0-9]+}}, #63
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return (uint64_t)vsrad_n_u64(a, b, 63);
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}
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int64_t test_vrsrad_n_s64(int64_t a, int64_t b) {
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// CHECK-LABEL: test_vrsrad_n_s64
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// CHECK: srsra {{d[0-9]+}}, {{d[0-9]+}}, #63
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return (int64_t)vrsrad_n_s64(a, b, 63);
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}
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uint64_t test_vrsrad_n_u64(uint64_t a, uint64_t b) {
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// CHECK-LABEL: test_vrsrad_n_u64
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// CHECK: ursra {{d[0-9]+}}, {{d[0-9]+}}, #63
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return (uint64_t)vrsrad_n_u64(a, b, 63);
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}
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int64_t test_vshld_n_s64(int64_t a) {
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// CHECK-LABEL: test_vshld_n_s64
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// CHECK: shl {{d[0-9]+}}, {{d[0-9]+}}, #0
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return (int64_t)vshld_n_s64(a, 0);
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}
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uint64_t test_vshld_n_u64(uint64_t a) {
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// CHECK-LABEL: test_vshld_n_u64
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// CHECK: shl {{d[0-9]+}}, {{d[0-9]+}}, #63
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return (uint64_t)vshld_n_u64(a, 63);
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}
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int8_t test_vqshlb_n_s8(int8_t a) {
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// CHECK-LABEL: test_vqshlb_n_s8
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// CHECK: sqshl {{b[0-9]+}}, {{b[0-9]+}}, #7
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return (int8_t)vqshlb_n_s8(a, 7);
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}
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int16_t test_vqshlh_n_s16(int16_t a) {
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// CHECK-LABEL: test_vqshlh_n_s16
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// CHECK: sqshl {{h[0-9]+}}, {{h[0-9]+}}, #15
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return (int16_t)vqshlh_n_s16(a, 15);
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}
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int32_t test_vqshls_n_s32(int32_t a) {
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// CHECK-LABEL: test_vqshls_n_s32
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// CHECK: sqshl {{s[0-9]+}}, {{s[0-9]+}}, #31
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return (int32_t)vqshls_n_s32(a, 31);
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}
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int64_t test_vqshld_n_s64(int64_t a) {
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// CHECK-LABEL: test_vqshld_n_s64
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// CHECK: sqshl {{d[0-9]+}}, {{d[0-9]+}}, #63
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return (int64_t)vqshld_n_s64(a, 63);
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}
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uint8_t test_vqshlb_n_u8(uint8_t a) {
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// CHECK-LABEL: test_vqshlb_n_u8
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// CHECK: uqshl {{b[0-9]+}}, {{b[0-9]+}}, #7
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return (uint8_t)vqshlb_n_u8(a, 7);
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}
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uint16_t test_vqshlh_n_u16(uint16_t a) {
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// CHECK-LABEL: test_vqshlh_n_u16
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// CHECK: uqshl {{h[0-9]+}}, {{h[0-9]+}}, #15
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return (uint16_t)vqshlh_n_u16(a, 15);
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}
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uint32_t test_vqshls_n_u32(uint32_t a) {
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// CHECK-LABEL: test_vqshls_n_u32
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// CHECK: uqshl {{s[0-9]+}}, {{s[0-9]+}}, #31
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return (uint32_t)vqshls_n_u32(a, 31);
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}
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uint64_t test_vqshld_n_u64(uint64_t a) {
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// CHECK-LABEL: test_vqshld_n_u64
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// CHECK: uqshl {{d[0-9]+}}, {{d[0-9]+}}, #63
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return (uint64_t)vqshld_n_u64(a, 63);
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}
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int8_t test_vqshlub_n_s8(int8_t a) {
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// CHECK-LABEL: test_vqshlub_n_s8
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// CHECK: sqshlu {{b[0-9]+}}, {{b[0-9]+}}, #7
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return (int8_t)vqshlub_n_s8(a, 7);
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}
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int16_t test_vqshluh_n_s16(int16_t a) {
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// CHECK-LABEL: test_vqshluh_n_s16
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// CHECK: sqshlu {{h[0-9]+}}, {{h[0-9]+}}, #15
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return (int16_t)vqshluh_n_s16(a, 15);
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}
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int32_t test_vqshlus_n_s32(int32_t a) {
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// CHECK-LABEL: test_vqshlus_n_s32
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// CHECK: sqshlu {{s[0-9]+}}, {{s[0-9]+}}, #31
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return (int32_t)vqshlus_n_s32(a, 31);
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}
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int64_t test_vqshlud_n_s64(int64_t a) {
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// CHECK-LABEL: test_vqshlud_n_s64
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// CHECK: sqshlu {{d[0-9]+}}, {{d[0-9]+}}, #63
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return (int64_t)vqshlud_n_s64(a, 63);
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}
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int64_t test_vsrid_n_s64(int64_t a) {
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// CHECK-LABEL: test_vsrid_n_s64
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// CHECK: sri {{d[0-9]+}}, {{d[0-9]+}}, #63
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return (int64_t)vsrid_n_s64(a, 63);
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}
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uint64_t test_vsrid_n_u64(uint64_t a) {
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// CHECK-LABEL: test_vsrid_n_u64
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// CHECK: sri {{d[0-9]+}}, {{d[0-9]+}}, #63
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return (uint64_t)vsrid_n_u64(a, 63);
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}
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int64_t test_vslid_n_s64(int64_t a) {
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// CHECK-LABEL: test_vslid_n_s64
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// CHECK: sli {{d[0-9]+}}, {{d[0-9]+}}, #63
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return (int64_t)vslid_n_s64(a, 63);
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}
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||||
uint64_t test_vslid_n_u64(uint64_t a) {
|
||||
// CHECK-LABEL: test_vslid_n_u64
|
||||
// CHECK: sli {{d[0-9]+}}, {{d[0-9]+}}, #63
|
||||
return (uint64_t)vslid_n_u64(a, 63);
|
||||
}
|
||||
|
||||
int8_t test_vqshrnh_n_s16(int16_t a) {
|
||||
// CHECK-LABEL: test_vqshrnh_n_s16
|
||||
// CHECK: sqshrn {{b[0-9]+}}, {{h[0-9]+}}, #15
|
||||
return (int8_t)vqshrnh_n_s16(a, 15);
|
||||
}
|
||||
|
||||
int16_t test_vqshrns_n_s32(int32_t a) {
|
||||
// CHECK-LABEL: test_vqshrns_n_s32
|
||||
// CHECK: sqshrn {{h[0-9]+}}, {{s[0-9]+}}, #31
|
||||
return (int16_t)vqshrns_n_s32(a, 31);
|
||||
}
|
||||
|
||||
int32_t test_vqshrnd_n_s64(int64_t a) {
|
||||
// CHECK-LABEL: test_vqshrnd_n_s64
|
||||
// CHECK: sqshrn {{s[0-9]+}}, {{d[0-9]+}}, #63
|
||||
return (int32_t)vqshrnd_n_s64(a, 63);
|
||||
}
|
||||
|
||||
uint8_t test_vqshrnh_n_u16(uint16_t a) {
|
||||
// CHECK-LABEL: test_vqshrnh_n_u16
|
||||
// CHECK: uqshrn {{b[0-9]+}}, {{h[0-9]+}}, #15
|
||||
return (uint8_t)vqshrnh_n_u16(a, 15);
|
||||
}
|
||||
|
||||
uint16_t test_vqshrns_n_u32(uint32_t a) {
|
||||
// CHECK-LABEL: test_vqshrns_n_u32
|
||||
// CHECK: uqshrn {{h[0-9]+}}, {{s[0-9]+}}, #31
|
||||
return (uint16_t)vqshrns_n_u32(a, 31);
|
||||
}
|
||||
|
||||
uint32_t test_vqshrnd_n_u64(uint64_t a) {
|
||||
// CHECK-LABEL: test_vqshrnd_n_u64
|
||||
// CHECK: uqshrn {{s[0-9]+}}, {{d[0-9]+}}, #63
|
||||
return (uint32_t)vqshrnd_n_u64(a, 63);
|
||||
}
|
||||
|
||||
int8_t test_vqrshrnh_n_s16(int16_t a) {
|
||||
// CHECK-LABEL: test_vqrshrnh_n_s16
|
||||
// CHECK: sqrshrn {{b[0-9]+}}, {{h[0-9]+}}, #15
|
||||
return (int8_t)vqrshrnh_n_s16(a, 15);
|
||||
}
|
||||
|
||||
int16_t test_vqrshrns_n_s32(int32_t a) {
|
||||
// CHECK-LABEL: test_vqrshrns_n_s32
|
||||
// CHECK: sqrshrn {{h[0-9]+}}, {{s[0-9]+}}, #31
|
||||
return (int16_t)vqrshrns_n_s32(a, 31);
|
||||
}
|
||||
|
||||
int32_t test_vqrshrnd_n_s64(int64_t a) {
|
||||
// CHECK-LABEL: test_vqrshrnd_n_s64
|
||||
// CHECK: sqrshrn {{s[0-9]+}}, {{d[0-9]+}}, #63
|
||||
return (int32_t)vqrshrnd_n_s64(a, 63);
|
||||
}
|
||||
|
||||
uint8_t test_vqrshrnh_n_u16(uint16_t a) {
|
||||
// CHECK-LABEL: test_vqrshrnh_n_u16
|
||||
// CHECK: uqrshrn {{b[0-9]+}}, {{h[0-9]+}}, #15
|
||||
return (uint8_t)vqrshrnh_n_u16(a, 15);
|
||||
}
|
||||
|
||||
uint16_t test_vqrshrns_n_u32(uint32_t a) {
|
||||
// CHECK-LABEL: test_vqrshrns_n_u32
|
||||
// CHECK: uqrshrn {{h[0-9]+}}, {{s[0-9]+}}, #31
|
||||
return (uint16_t)vqrshrns_n_u32(a, 31);
|
||||
}
|
||||
|
||||
uint32_t test_vqrshrnd_n_u64(uint64_t a) {
|
||||
// CHECK-LABEL: test_vqrshrnd_n_u64
|
||||
// CHECK: uqrshrn {{s[0-9]+}}, {{d[0-9]+}}, #63
|
||||
return (uint32_t)vqrshrnd_n_u64(a, 63);
|
||||
}
|
||||
|
||||
int8_t test_vqshrunh_n_s16(int16_t a) {
|
||||
// CHECK-LABEL: test_vqshrunh_n_s16
|
||||
// CHECK: sqshrun {{b[0-9]+}}, {{h[0-9]+}}, #15
|
||||
return (int8_t)vqshrunh_n_s16(a, 15);
|
||||
}
|
||||
|
||||
int16_t test_vqshruns_n_s32(int32_t a) {
|
||||
// CHECK-LABEL: test_vqshruns_n_s32
|
||||
// CHECK: sqshrun {{h[0-9]+}}, {{s[0-9]+}}, #31
|
||||
return (int16_t)vqshruns_n_s32(a, 31);
|
||||
}
|
||||
|
||||
int32_t test_vqshrund_n_s64(int64_t a) {
|
||||
// CHECK-LABEL: test_vqshrund_n_s64
|
||||
// CHECK: sqshrun {{s[0-9]+}}, {{d[0-9]+}}, #63
|
||||
return (int32_t)vqshrund_n_s64(a, 63);
|
||||
}
|
||||
|
||||
int8_t test_vqrshrunh_n_s16(int16_t a) {
|
||||
// CHECK-LABEL: test_vqrshrunh_n_s16
|
||||
// CHECK: sqrshrun {{b[0-9]+}}, {{h[0-9]+}}, #15
|
||||
return (int8_t)vqrshrunh_n_s16(a, 15);
|
||||
}
|
||||
|
||||
int16_t test_vqrshruns_n_s32(int32_t a) {
|
||||
// CHECK-LABEL: test_vqrshruns_n_s32
|
||||
// CHECK: sqrshrun {{h[0-9]+}}, {{s[0-9]+}}, #31
|
||||
return (int16_t)vqrshruns_n_s32(a, 31);
|
||||
}
|
||||
|
||||
int32_t test_vqrshrund_n_s64(int64_t a) {
|
||||
// CHECK-LABEL: test_vqrshrund_n_s64
|
||||
// CHECK: sqrshrun {{s[0-9]+}}, {{d[0-9]+}}, #63
|
||||
return (int32_t)vqrshrund_n_s64(a, 63);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -2383,6 +2383,29 @@ static unsigned RangeFromType(const char mod, StringRef typestr) {
|
|||
}
|
||||
}
|
||||
|
||||
static unsigned RangeScalarShiftImm(const char mod, StringRef typestr) {
|
||||
// base type to get the type string for.
|
||||
bool dummy = false;
|
||||
char type = ClassifyType(typestr, dummy, dummy, dummy);
|
||||
type = ModType(mod, type, dummy, dummy, dummy, dummy, dummy, dummy);
|
||||
|
||||
switch (type) {
|
||||
case 'c':
|
||||
return 7;
|
||||
case 'h':
|
||||
case 's':
|
||||
return 15;
|
||||
case 'f':
|
||||
case 'i':
|
||||
return 31;
|
||||
case 'd':
|
||||
case 'l':
|
||||
return 63;
|
||||
default:
|
||||
PrintFatalError("unhandled type!");
|
||||
}
|
||||
}
|
||||
|
||||
/// Generate the ARM and AArch64 intrinsic range checking code for
|
||||
/// shift/lane immediates, checking for unique declarations.
|
||||
void
|
||||
|
|
@ -2456,6 +2479,14 @@ NeonEmitter::genIntrinsicRangeCheckCode(raw_ostream &OS,
|
|||
else
|
||||
PrintFatalError(R->getLoc(),
|
||||
"Fixed point convert name should contains \"32\" or \"64\"");
|
||||
|
||||
} else if (R->getValueAsBit("isScalarShift")) {
|
||||
// Right shifts have an 'r' in the name, left shifts do not.
|
||||
if (name.find('r') != std::string::npos)
|
||||
rangestr = "l = 1; ";
|
||||
|
||||
rangestr += "u = " +
|
||||
utostr(RangeScalarShiftImm(Proto[immPos - 1], TypeVec[ti]));
|
||||
} else if (!ProtoHasScalar(Proto)) {
|
||||
// Builtins which are overloaded by type will need to have their upper
|
||||
// bound computed at Sema time based on the type constant.
|
||||
|
|
|
|||
Loading…
Reference in New Issue