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[Hexagon] Adding frame index + add load/store patterns. 

llvm-svn: 231850
This commit is contained in:
Colin LeMahieu 2015-03-10 21:24:13 +00:00
parent e912e3e3f9
commit bdc6c83d24
2 changed files with 20 additions and 5 deletions
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23
llvm/lib/Target/Hexagon/HexagonInstrInfo.td
View File

@ -1772,6 +1772,8 @@ def L2_loadalignb_io: T_loadalign_io <"memb_fifo", 0b0100, s11_0Ext>;
multiclass Loadx_pat<PatFrag Load, ValueType VT, PatLeaf ImmPred, multiclass Loadx_pat<PatFrag Load, ValueType VT, PatLeaf ImmPred,
InstHexagon MI> { InstHexagon MI> {
def: Pat<(VT (Load AddrFI:$fi)), (VT (MI AddrFI:$fi, 0))>; def: Pat<(VT (Load AddrFI:$fi)), (VT (MI AddrFI:$fi, 0))>;
def: Pat<(VT (Load (add (i32 AddrFI:$fi), ImmPred:$Off))),
(VT (MI AddrFI:$fi, imm:$Off))>;
def: Pat<(VT (Load (add (i32 IntRegs:$Rs), ImmPred:$Off))), def: Pat<(VT (Load (add (i32 IntRegs:$Rs), ImmPred:$Off))),
(VT (MI IntRegs:$Rs, imm:$Off))>; (VT (MI IntRegs:$Rs, imm:$Off))>;
def: Pat<(VT (Load (i32 IntRegs:$Rs))), (VT (MI IntRegs:$Rs, 0))>; def: Pat<(VT (Load (i32 IntRegs:$Rs))), (VT (MI IntRegs:$Rs, 0))>;
@ -3544,7 +3546,8 @@ let addrMode = BaseImmOffset, InputType = "imm" in {
} }
// Patterns for generating stores, where the address takes different forms: // Patterns for generating stores, where the address takes different forms:
// - frameindex,, // - frameindex,
// - frameindex + offset,
// - base + offset, // - base + offset,
// - simple (base address without offset). // - simple (base address without offset).
// These would usually be used together (via Storex_pat defined below), but // These would usually be used together (via Storex_pat defined below), but
@ -3552,6 +3555,10 @@ let addrMode = BaseImmOffset, InputType = "imm" in {
// AddedComplexity) to the individual patterns. // AddedComplexity) to the individual patterns.
class Storex_fi_pat<PatFrag Store, PatFrag Value, InstHexagon MI> class Storex_fi_pat<PatFrag Store, PatFrag Value, InstHexagon MI>
: Pat<(Store Value:$Rs, AddrFI:$fi), (MI AddrFI:$fi, 0, Value:$Rs)>; : Pat<(Store Value:$Rs, AddrFI:$fi), (MI AddrFI:$fi, 0, Value:$Rs)>;
class Storex_fi_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred,
InstHexagon MI>
: Pat<(Store Value:$Rs, (add (i32 AddrFI:$fi), ImmPred:$Off)),
(MI AddrFI:$fi, imm:$Off, Value:$Rs)>;
class Storex_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred, class Storex_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred,
InstHexagon MI> InstHexagon MI>
: Pat<(Store Value:$Rt, (add (i32 IntRegs:$Rs), ImmPred:$Off)), : Pat<(Store Value:$Rt, (add (i32 IntRegs:$Rs), ImmPred:$Off)),
@ -3567,6 +3574,10 @@ class Storexm_fi_pat<PatFrag Store, PatFrag Value, PatFrag ValueMod,
InstHexagon MI> InstHexagon MI>
: Pat<(Store Value:$Rs, AddrFI:$fi), : Pat<(Store Value:$Rs, AddrFI:$fi),
(MI AddrFI:$fi, 0, (ValueMod Value:$Rs))>; (MI AddrFI:$fi, 0, (ValueMod Value:$Rs))>;
class Storexm_fi_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred,
PatFrag ValueMod, InstHexagon MI>
: Pat<(Store Value:$Rs, (add (i32 AddrFI:$fi), ImmPred:$Off)),
(MI AddrFI:$fi, imm:$Off, (ValueMod Value:$Rs))>;
class Storexm_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred, class Storexm_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred,
PatFrag ValueMod, InstHexagon MI> PatFrag ValueMod, InstHexagon MI>
: Pat<(Store Value:$Rt, (add (i32 IntRegs:$Rs), ImmPred:$Off)), : Pat<(Store Value:$Rt, (add (i32 IntRegs:$Rs), ImmPred:$Off)),
@ -3578,14 +3589,16 @@ class Storexm_simple_pat<PatFrag Store, PatFrag Value, PatFrag ValueMod,
multiclass Storex_pat<PatFrag Store, PatFrag Value, PatLeaf ImmPred, multiclass Storex_pat<PatFrag Store, PatFrag Value, PatLeaf ImmPred,
InstHexagon MI> { InstHexagon MI> {
def: Storex_fi_pat <Store, Value, MI>; def: Storex_fi_pat <Store, Value, MI>;
def: Storex_add_pat <Store, Value, ImmPred, MI>; def: Storex_fi_add_pat <Store, Value, ImmPred, MI>;
def: Storex_add_pat <Store, Value, ImmPred, MI>;
} }
multiclass Storexm_pat<PatFrag Store, PatFrag Value, PatLeaf ImmPred, multiclass Storexm_pat<PatFrag Store, PatFrag Value, PatLeaf ImmPred,
PatFrag ValueMod, InstHexagon MI> { PatFrag ValueMod, InstHexagon MI> {
def: Storexm_fi_pat <Store, Value, ValueMod, MI>; def: Storexm_fi_pat <Store, Value, ValueMod, MI>;
def: Storexm_add_pat <Store, Value, ImmPred, ValueMod, MI>; def: Storexm_fi_add_pat <Store, Value, ImmPred, ValueMod, MI>;
def: Storexm_add_pat <Store, Value, ImmPred, ValueMod, MI>;
} }
// Regular stores in the DAG have two operands: value and address. // Regular stores in the DAG have two operands: value and address.

2
llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td
View File

@ -367,6 +367,8 @@ multiclass Loadxm_pat<PatFrag Load, ValueType VT, PatFrag ValueMod,
PatLeaf ImmPred, InstHexagon MI> { PatLeaf ImmPred, InstHexagon MI> {
def: Pat<(VT (Load AddrFI:$fi)), def: Pat<(VT (Load AddrFI:$fi)),
(VT (ValueMod (MI AddrFI:$fi, 0)))>; (VT (ValueMod (MI AddrFI:$fi, 0)))>;
def: Pat<(VT (Load (add AddrFI:$fi, ImmPred:$Off))),
(VT (ValueMod (MI AddrFI:$fi, imm:$Off)))>;
def: Pat<(VT (Load (add IntRegs:$Rs, ImmPred:$Off))), def: Pat<(VT (Load (add IntRegs:$Rs, ImmPred:$Off))),
(VT (ValueMod (MI IntRegs:$Rs, imm:$Off)))>; (VT (ValueMod (MI IntRegs:$Rs, imm:$Off)))>;
def: Pat<(VT (Load (i32 IntRegs:$Rs))), def: Pat<(VT (Load (i32 IntRegs:$Rs))),