forked from OSchip/llvm-project
Fix ARM FastISel tests, as a first step to enabling ARM FastISel
ARM FastISel is currently only enabled for iOS non-Thumb1, and I'm working on enabling it for other targets. As a first step I've fixed some of the tests. Changes to ARM FastISel tests: - Different triples don't generate the same relocations (especially movw/movt versus constant pool loads). Use a regex to allow either. - Mangling is different. Use a regex to allow either. - The reserved registers are sometimes different, so registers get allocated in a different order. Capture the names only where this occurs. - Add -verify-machineinstrs to some tests where it works. It doesn't work everywhere it should yet. - Add -fast-isel-abort to many tests that didn't have it before. - Split out the VarArg test from fast-isel-call.ll into its own test. This simplifies test setup because of --check-prefix. Patch by JF Bastien llvm-svn: 181801
This commit is contained in:
Derek Schuff
parent
ef3d1a24ed
commit
bd7c6e5015
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@ -26,8 +26,8 @@ entry:
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; THUMB: t2
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%addr = alloca i32*, align 4
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store i32* getelementptr inbounds ([3 x [3 x %struct.A]]* @A, i32 0, i32 2, i32 2, i32 3, i32 1, i32 2, i32 2), i32** %addr, align 4
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; ARM: movw r1, #1148
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; ARM: add r0, r0, r1
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; ARM: movw [[R:r[0-9]+]], #1148
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; ARM: add r0, r{{[0-9]+}}, [[R]]
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; THUMB: addw r0, r0, #1148
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%0 = load i32** %addr, align 4
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ret i32* %0
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@ -7,8 +7,8 @@ entry:
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; ARM: t1:
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%x = add i32 %a, %b
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br i1 1, label %if.then, label %if.else
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; THUMB-NOT: b LBB0_1
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; ARM-NOT: b LBB0_1
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; THUMB-NOT: b {{\.?}}LBB0_1
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; ARM-NOT: b {{\.?}}LBB0_1
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if.then: ; preds = %entry
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call void @foo1()
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@ -16,8 +16,8 @@ if.then: ; preds = %entry
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if.else: ; preds = %entry
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br i1 0, label %if.then2, label %if.else3
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; THUMB: b LBB0_4
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; ARM: b LBB0_4
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; THUMB: b {{\.?}}LBB0_4
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; ARM: b {{\.?}}LBB0_4
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if.then2: ; preds = %if.else
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call void @foo2()
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@ -26,8 +26,8 @@ if.then2: ; preds = %if.else
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if.else3: ; preds = %if.else
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%y = sub i32 %a, %b
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br i1 1, label %if.then5, label %if.end
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; THUMB-NOT: b LBB0_5
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; ARM-NOT: b LBB0_5
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; THUMB-NOT: b {{\.?}}LBB0_5
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; ARM-NOT: b {{\.?}}LBB0_5
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if.then5: ; preds = %if.else3
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call void @foo1()
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@ -1,5 +1,5 @@
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; RUN: llc < %s -O0 -verify-machineinstrs -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
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; RUN: llc < %s -O0 -verify-machineinstrs -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
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; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
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; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
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; Fast-isel can't handle non-double multi-reg retvals.
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; This test just check to make sure we don't hit the assert in FinishCall.
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@ -2,8 +2,12 @@
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; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
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; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -arm-long-calls | FileCheck %s --check-prefix=ARM-LONG
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; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -arm-long-calls | FileCheck %s --check-prefix=THUMB-LONG
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; RUN: llc < %s -O0 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -mattr=-vfp2 | FileCheck %s --check-prefix=ARM-NOVFP
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; RUN: llc < %s -O0 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -mattr=-vfp2 | FileCheck %s --check-prefix=THUMB-NOVFP
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; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -mattr=-vfp2 | FileCheck %s --check-prefix=ARM-NOVFP
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; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -mattr=-vfp2 | FileCheck %s --check-prefix=THUMB-NOVFP
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; Note that some of these tests assume that relocations are either
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; movw/movt or constant pool loads. Different platforms will select
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; different approaches.
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define i32 @t0(i1 zeroext %a) nounwind {
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%1 = zext i1 %a to i32
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@ -88,53 +92,53 @@ declare zeroext i1 @t9();
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define i32 @t10(i32 %argc, i8** nocapture %argv) {
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entry:
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; ARM: @t10
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; ARM: movw r0, #0
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; ARM: movw r1, #248
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; ARM: movw r2, #187
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; ARM: movw r3, #28
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; ARM: movw r9, #40
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; ARM: movw r12, #186
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; ARM: uxtb r0, r0
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; ARM: uxtb r1, r1
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; ARM: uxtb r2, r2
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; ARM: uxtb r3, r3
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; ARM: uxtb r9, r9
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; ARM: str r9, [sp]
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; ARM: uxtb r9, r12
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; ARM: str r9, [sp, #4]
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; ARM: bl _bar
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; ARM: movw [[R0:l?r[0-9]*]], #0
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; ARM: movw [[R1:l?r[0-9]*]], #248
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; ARM: movw [[R2:l?r[0-9]*]], #187
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; ARM: movw [[R3:l?r[0-9]*]], #28
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; ARM: movw [[R4:l?r[0-9]*]], #40
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; ARM: movw [[R5:l?r[0-9]*]], #186
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; ARM: uxtb [[R0]], [[R0]]
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; ARM: uxtb [[R1]], [[R1]]
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; ARM: uxtb [[R2]], [[R2]]
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; ARM: uxtb [[R3]], [[R3]]
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; ARM: uxtb [[R4]], [[R4]]
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; ARM: str [[R4]], [sp]
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; ARM: uxtb [[R4]], [[R5]]
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; ARM: str [[R4]], [sp, #4]
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; ARM: bl {{_?}}bar
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; ARM-LONG: @t10
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; ARM-LONG: movw lr, :lower16:L_bar$non_lazy_ptr
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; ARM-LONG: movt lr, :upper16:L_bar$non_lazy_ptr
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; ARM-LONG: ldr lr, [lr]
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; ARM-LONG: blx lr
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; ARM-LONG: {{(movw)|(ldr)}} [[R:l?r[0-9]*]], {{(:lower16:L_bar\$non_lazy_ptr)|(.LCPI)}}
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; ARM-LONG: {{(movt [[R]], :upper16:L_bar\$non_lazy_ptr)?}}
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; ARM-LONG: ldr [[R]], {{\[}}[[R]]{{\]}}
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; ARM-LONG: blx [[R]]
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; THUMB: @t10
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; THUMB: movs r0, #0
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; THUMB: movt r0, #0
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; THUMB: movs r1, #248
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; THUMB: movt r1, #0
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; THUMB: movs r2, #187
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; THUMB: movt r2, #0
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; THUMB: movs r3, #28
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; THUMB: movt r3, #0
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; THUMB: movw r9, #40
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; THUMB: movt r9, #0
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; THUMB: movw r12, #186
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; THUMB: movt r12, #0
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; THUMB: uxtb r0, r0
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; THUMB: uxtb r1, r1
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; THUMB: uxtb r2, r2
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; THUMB: uxtb r3, r3
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; THUMB: uxtb.w r9, r9
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; THUMB: str.w r9, [sp]
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; THUMB: uxtb.w r9, r12
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; THUMB: str.w r9, [sp, #4]
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; THUMB: bl _bar
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; THUMB: movs [[R0:l?r[0-9]*]], #0
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; THUMB: movt [[R0]], #0
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; THUMB: movs [[R1:l?r[0-9]*]], #248
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; THUMB: movt [[R1]], #0
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; THUMB: movs [[R2:l?r[0-9]*]], #187
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; THUMB: movt [[R2]], #0
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; THUMB: movs [[R3:l?r[0-9]*]], #28
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; THUMB: movt [[R3]], #0
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; THUMB: movw [[R4:l?r[0-9]*]], #40
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; THUMB: movt [[R4]], #0
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; THUMB: movw [[R5:l?r[0-9]*]], #186
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; THUMB: movt [[R5]], #0
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; THUMB: uxtb [[R0]], [[R0]]
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; THUMB: uxtb [[R1]], [[R1]]
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; THUMB: uxtb [[R2]], [[R2]]
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; THUMB: uxtb [[R3]], [[R3]]
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; THUMB: uxtb.w [[R4]], [[R4]]
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; THUMB: str.w [[R4]], [sp]
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; THUMB: uxtb.w [[R4]], [[R5]]
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; THUMB: str.w [[R4]], [sp, #4]
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; THUMB: bl {{_?}}bar
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; THUMB-LONG: @t10
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; THUMB-LONG: movw lr, :lower16:L_bar$non_lazy_ptr
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; THUMB-LONG: movt lr, :upper16:L_bar$non_lazy_ptr
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; THUMB-LONG: ldr.w lr, [lr]
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; THUMB-LONG: blx lr
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; THUMB-LONG: {{(movw)|(ldr.n)}} [[R:l?r[0-9]*]], {{(:lower16:L_bar\$non_lazy_ptr)|(.LCPI)}}
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; THUMB-LONG: {{(movt [[R]], :upper16:L_bar\$non_lazy_ptr)?}}
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; THUMB-LONG: ldr{{(.w)?}} [[R]], {{\[}}[[R]]{{\]}}
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; THUMB-LONG: blx [[R]]
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%call = call i32 @bar(i8 zeroext 0, i8 zeroext -8, i8 zeroext -69, i8 zeroext 28, i8 zeroext 40, i8 zeroext -70)
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ret i32 0
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}
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@ -147,12 +151,12 @@ define i32 @bar0(i32 %i) nounwind {
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define void @foo3() uwtable {
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; ARM: movw r0, #0
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; ARM: movw r1, :lower16:_bar0
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; ARM: movt r1, :upper16:_bar0
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; ARM: {{(movw r1, :lower16:_?bar0)|(ldr r1, .LCPI)}}
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; ARM: {{(movt r1, :upper16:_?bar0)|(ldr r1, \[r1\])}}
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; ARM: blx r1
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; THUMB: movs r0, #0
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; THUMB: movw r1, :lower16:_bar0
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; THUMB: movt r1, :upper16:_bar0
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; THUMB: {{(movw r1, :lower16:_?bar0)|(ldr.n r1, .LCPI)}}
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; THUMB: {{(movt r1, :upper16:_?bar0)|(ldr r1, \[r1\])}}
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; THUMB: blx r1
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%fptr = alloca i32 (i32)*, align 8
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store i32 (i32)* @bar0, i32 (i32)** %fptr, align 8
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@ -164,66 +168,23 @@ define void @foo3() uwtable {
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define i32 @LibCall(i32 %a, i32 %b) {
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entry:
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; ARM: LibCall
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; ARM: bl ___udivsi3
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; ARM: bl {{___udivsi3|__aeabi_uidiv}}
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; ARM-LONG: LibCall
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; ARM-LONG: movw r2, :lower16:L___udivsi3$non_lazy_ptr
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; ARM-LONG: movt r2, :upper16:L___udivsi3$non_lazy_ptr
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; ARM-LONG: {{(movw r2, :lower16:L___udivsi3\$non_lazy_ptr)|(ldr r2, .LCPI)}}
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; ARM-LONG: {{(movt r2, :upper16:L___udivsi3\$non_lazy_ptr)?}}
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; ARM-LONG: ldr r2, [r2]
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; ARM-LONG: blx r2
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; THUMB: LibCall
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; THUMB: bl ___udivsi3
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; THUMB: bl {{___udivsi3|__aeabi_uidiv}}
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; THUMB-LONG: LibCall
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; THUMB-LONG: movw r2, :lower16:L___udivsi3$non_lazy_ptr
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; THUMB-LONG: movt r2, :upper16:L___udivsi3$non_lazy_ptr
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; THUMB-LONG: {{(movw r2, :lower16:L___udivsi3\$non_lazy_ptr)|(ldr.n r2, .LCPI)}}
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; THUMB-LONG: {{(movt r2, :upper16:L___udivsi3\$non_lazy_ptr)?}}
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; THUMB-LONG: ldr r2, [r2]
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; THUMB-LONG: blx r2
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%tmp1 = udiv i32 %a, %b ; <i32> [#uses=1]
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ret i32 %tmp1
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}
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define i32 @VarArg() nounwind {
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entry:
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%i = alloca i32, align 4
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%j = alloca i32, align 4
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%k = alloca i32, align 4
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%m = alloca i32, align 4
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%n = alloca i32, align 4
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%tmp = alloca i32, align 4
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%0 = load i32* %i, align 4
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%1 = load i32* %j, align 4
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%2 = load i32* %k, align 4
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%3 = load i32* %m, align 4
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%4 = load i32* %n, align 4
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; ARM: VarArg
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; ARM: mov r7, sp
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; ARM: movw r0, #5
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; ARM: ldr r1, [r7, #-4]
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; ARM: ldr r2, [r7, #-8]
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; ARM: ldr r3, [r7, #-12]
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; ARM: ldr r9, [sp, #16]
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; ARM: ldr r12, [sp, #12]
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; ARM: str r9, [sp]
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; ARM: str r12, [sp, #4]
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; ARM: bl _CallVariadic
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; THUMB: mov r7, sp
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; THUMB: movs r0, #5
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; THUMB: movt r0, #0
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; THUMB: ldr r1, [sp, #28]
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; THUMB: ldr r2, [sp, #24]
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; THUMB: ldr r3, [sp, #20]
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; THUMB: ldr.w r9, [sp, #16]
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; THUMB: ldr.w r12, [sp, #12]
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; THUMB: str.w r9, [sp]
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; THUMB: str.w r12, [sp, #4]
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; THUMB: bl _CallVariadic
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%call = call i32 (i32, ...)* @CallVariadic(i32 5, i32 %0, i32 %1, i32 %2, i32 %3, i32 %4)
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store i32 %call, i32* %tmp, align 4
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%5 = load i32* %tmp, align 4
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ret i32 %5
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}
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declare i32 @CallVariadic(i32, ...)
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; Test fastcc
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define fastcc void @fast_callee(float %i) ssp {
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@ -1,4 +1,4 @@
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; RUN: llc < %s -O0 -verify-machineinstrs -mtriple=thumbv7-apple-darwin
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; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=thumbv7-apple-darwin
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%union.anon = type { <16 x i32> }
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@ -1,4 +1,4 @@
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; RUN: llc < %s -O0 -verify-machineinstrs -mtriple=thumbv7-apple-darwin
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; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=thumbv7-apple-darwin
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; rdar://9515076
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; (Make sure this doesn't crash.)
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@ -1,4 +1,4 @@
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; RUN: llc < %s -O0 -verify-machineinstrs -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
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; RUN: llc < %s -O0 -fast-isel-abort -verify-machineinstrs -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
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; Target-specific selector can't properly handle the double because it isn't
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; being passed via a register, so the materialized arguments become dead code.
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@ -3,33 +3,37 @@
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; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -arm-long-calls | FileCheck %s --check-prefix=ARM-LONG
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; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -arm-long-calls | FileCheck %s --check-prefix=THUMB-LONG
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; Note that some of these tests assume that relocations are either
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; movw/movt or constant pool loads. Different platforms will select
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; different approaches.
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@message1 = global [60 x i8] c"The LLVM Compiler Infrastructure\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00", align 1
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@temp = common global [60 x i8] zeroinitializer, align 1
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define void @t1() nounwind ssp {
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; ARM: t1
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; ARM: movw r0, :lower16:_message1
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; ARM: movt r0, :upper16:_message1
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; ARM: {{(movw r0, :lower16:_?message1)|(ldr r0, .LCPI)}}
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; ARM: {{(movt r0, :upper16:_?message1)|(ldr r0, \[r0\])}}
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; ARM: add r0, r0, #5
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; ARM: movw r1, #64
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; ARM: movw r2, #10
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; ARM: uxtb r1, r1
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; ARM: bl _memset
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; ARM: bl {{_?}}memset
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; ARM-LONG: t1
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; ARM-LONG: movw r3, :lower16:L_memset$non_lazy_ptr
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; ARM-LONG: movt r3, :upper16:L_memset$non_lazy_ptr
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; ARM-LONG: ldr r3, [r3]
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; ARM-LONG: blx r3
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; THUMB: t1
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; THUMB: movw r0, :lower16:_message1
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; THUMB: movt r0, :upper16:_message1
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; THUMB: {{(movw r0, :lower16:_?message1)|(ldr.n r0, .LCPI)}}
|
||||
; THUMB: {{(movt r0, :upper16:_?message1)|(ldr r0, \[r0\])}}
|
||||
; THUMB: adds r0, #5
|
||||
; THUMB: movs r1, #64
|
||||
; THUMB: movt r1, #0
|
||||
; THUMB: movs r2, #10
|
||||
; THUMB: movt r2, #0
|
||||
; THUMB: uxtb r1, r1
|
||||
; THUMB: bl _memset
|
||||
; THUMB: bl {{_?}}memset
|
||||
; THUMB-LONG: t1
|
||||
; THUMB-LONG: movw r3, :lower16:L_memset$non_lazy_ptr
|
||||
; THUMB-LONG: movt r3, :upper16:L_memset$non_lazy_ptr
|
||||
|
|
@ -43,31 +47,33 @@ declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i32, i1) nounwind
|
|||
|
||||
define void @t2() nounwind ssp {
|
||||
; ARM: t2
|
||||
; ARM: movw r0, :lower16:L_temp$non_lazy_ptr
|
||||
; ARM: movt r0, :upper16:L_temp$non_lazy_ptr
|
||||
; ARM: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr r0, .LCPI)}}
|
||||
; ARM: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}}
|
||||
; ARM: ldr r0, [r0]
|
||||
; ARM: add r1, r0, #4
|
||||
; ARM: add r0, r0, #16
|
||||
; ARM: movw r2, #17
|
||||
; ARM: str r0, [sp] @ 4-byte Spill
|
||||
; ARM: str r0, [sp[[SLOT:[, #0-9]*]]] @ 4-byte Spill
|
||||
; ARM: mov r0, r1
|
||||
; ARM: ldr r1, [sp] @ 4-byte Reload
|
||||
; ARM: bl _memcpy
|
||||
; ARM: ldr r1, [sp[[SLOT]]] @ 4-byte Reload
|
||||
; ARM: bl {{_?}}memcpy
|
||||
; ARM-LONG: t2
|
||||
; ARM-LONG: movw r3, :lower16:L_memcpy$non_lazy_ptr
|
||||
; ARM-LONG: movt r3, :upper16:L_memcpy$non_lazy_ptr
|
||||
; ARM-LONG: ldr r3, [r3]
|
||||
; ARM-LONG: blx r3
|
||||
; THUMB: t2
|
||||
; THUMB: movw r0, :lower16:L_temp$non_lazy_ptr
|
||||
; THUMB: movt r0, :upper16:L_temp$non_lazy_ptr
|
||||
; THUMB: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr.n r0, .LCPI)}}
|
||||
; THUMB: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}}
|
||||
; THUMB: ldr r0, [r0]
|
||||
; THUMB: adds r1, r0, #4
|
||||
; THUMB: adds r0, #16
|
||||
; THUMB: movs r2, #17
|
||||
; THUMB: movt r2, #0
|
||||
; THUMB: str r0, [sp[[SLOT:[, #0-9]*]]] @ 4-byte Spill
|
||||
; THUMB: mov r0, r1
|
||||
; THUMB: bl _memcpy
|
||||
; THUMB: ldr r1, [sp[[SLOT]]] @ 4-byte Reload
|
||||
; THUMB: bl {{_?}}memcpy
|
||||
; THUMB-LONG: t2
|
||||
; THUMB-LONG: movw r3, :lower16:L_memcpy$non_lazy_ptr
|
||||
; THUMB-LONG: movt r3, :upper16:L_memcpy$non_lazy_ptr
|
||||
|
|
@ -81,29 +87,31 @@ declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32,
|
|||
|
||||
define void @t3() nounwind ssp {
|
||||
; ARM: t3
|
||||
; ARM: movw r0, :lower16:L_temp$non_lazy_ptr
|
||||
; ARM: movt r0, :upper16:L_temp$non_lazy_ptr
|
||||
; ARM: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr r0, .LCPI)}}
|
||||
; ARM: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}}
|
||||
; ARM: ldr r0, [r0]
|
||||
; ARM: add r1, r0, #4
|
||||
; ARM: add r0, r0, #16
|
||||
; ARM: movw r2, #10
|
||||
; ARM: mov r0, r1
|
||||
; ARM: bl _memmove
|
||||
; ARM: bl {{_?}}memmove
|
||||
; ARM-LONG: t3
|
||||
; ARM-LONG: movw r3, :lower16:L_memmove$non_lazy_ptr
|
||||
; ARM-LONG: movt r3, :upper16:L_memmove$non_lazy_ptr
|
||||
; ARM-LONG: ldr r3, [r3]
|
||||
; ARM-LONG: blx r3
|
||||
; THUMB: t3
|
||||
; THUMB: movw r0, :lower16:L_temp$non_lazy_ptr
|
||||
; THUMB: movt r0, :upper16:L_temp$non_lazy_ptr
|
||||
; THUMB: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr.n r0, .LCPI)}}
|
||||
; THUMB: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}}
|
||||
; THUMB: ldr r0, [r0]
|
||||
; THUMB: adds r1, r0, #4
|
||||
; THUMB: adds r0, #16
|
||||
; THUMB: movs r2, #10
|
||||
; THUMB: movt r2, #0
|
||||
; THUMB: str r0, [sp[[SLOT:[, #0-9]*]]] @ 4-byte Spill
|
||||
; THUMB: mov r0, r1
|
||||
; THUMB: bl _memmove
|
||||
; THUMB: ldr r1, [sp[[SLOT]]] @ 4-byte Reload
|
||||
; THUMB: bl {{_?}}memmove
|
||||
; THUMB-LONG: t3
|
||||
; THUMB-LONG: movw r3, :lower16:L_memmove$non_lazy_ptr
|
||||
; THUMB-LONG: movt r3, :upper16:L_memmove$non_lazy_ptr
|
||||
|
|
@ -115,8 +123,8 @@ define void @t3() nounwind ssp {
|
|||
|
||||
define void @t4() nounwind ssp {
|
||||
; ARM: t4
|
||||
; ARM: movw r0, :lower16:L_temp$non_lazy_ptr
|
||||
; ARM: movt r0, :upper16:L_temp$non_lazy_ptr
|
||||
; ARM: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr r0, .LCPI)}}
|
||||
; ARM: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}}
|
||||
; ARM: ldr r0, [r0]
|
||||
; ARM: ldr r1, [r0, #16]
|
||||
; ARM: str r1, [r0, #4]
|
||||
|
|
@ -126,8 +134,8 @@ define void @t4() nounwind ssp {
|
|||
; ARM: strh r1, [r0, #12]
|
||||
; ARM: bx lr
|
||||
; THUMB: t4
|
||||
; THUMB: movw r0, :lower16:L_temp$non_lazy_ptr
|
||||
; THUMB: movt r0, :upper16:L_temp$non_lazy_ptr
|
||||
; THUMB: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr.n r0, .LCPI)}}
|
||||
; THUMB: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}}
|
||||
; THUMB: ldr r0, [r0]
|
||||
; THUMB: ldr r1, [r0, #16]
|
||||
; THUMB: str r1, [r0, #4]
|
||||
|
|
@ -144,8 +152,8 @@ declare void @llvm.memmove.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32,
|
|||
|
||||
define void @t5() nounwind ssp {
|
||||
; ARM: t5
|
||||
; ARM: movw r0, :lower16:L_temp$non_lazy_ptr
|
||||
; ARM: movt r0, :upper16:L_temp$non_lazy_ptr
|
||||
; ARM: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr r0, .LCPI)}}
|
||||
; ARM: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}}
|
||||
; ARM: ldr r0, [r0]
|
||||
; ARM: ldrh r1, [r0, #16]
|
||||
; ARM: strh r1, [r0, #4]
|
||||
|
|
@ -159,8 +167,8 @@ define void @t5() nounwind ssp {
|
|||
; ARM: strh r1, [r0, #12]
|
||||
; ARM: bx lr
|
||||
; THUMB: t5
|
||||
; THUMB: movw r0, :lower16:L_temp$non_lazy_ptr
|
||||
; THUMB: movt r0, :upper16:L_temp$non_lazy_ptr
|
||||
; THUMB: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr.n r0, .LCPI)}}
|
||||
; THUMB: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}}
|
||||
; THUMB: ldr r0, [r0]
|
||||
; THUMB: ldrh r1, [r0, #16]
|
||||
; THUMB: strh r1, [r0, #4]
|
||||
|
|
@ -179,8 +187,8 @@ define void @t5() nounwind ssp {
|
|||
|
||||
define void @t6() nounwind ssp {
|
||||
; ARM: t6
|
||||
; ARM: movw r0, :lower16:L_temp$non_lazy_ptr
|
||||
; ARM: movt r0, :upper16:L_temp$non_lazy_ptr
|
||||
; ARM: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr r0, .LCPI)}}
|
||||
; ARM: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}}
|
||||
; ARM: ldr r0, [r0]
|
||||
; ARM: ldrb r1, [r0, #16]
|
||||
; ARM: strb r1, [r0, #4]
|
||||
|
|
@ -204,8 +212,8 @@ define void @t6() nounwind ssp {
|
|||
; ARM: strb r1, [r0, #13]
|
||||
; ARM: bx lr
|
||||
; THUMB: t6
|
||||
; THUMB: movw r0, :lower16:L_temp$non_lazy_ptr
|
||||
; THUMB: movt r0, :upper16:L_temp$non_lazy_ptr
|
||||
; THUMB: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr.n r0, .LCPI)}}
|
||||
; THUMB: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}}
|
||||
; THUMB: ldr r0, [r0]
|
||||
; THUMB: ldrb r1, [r0, #16]
|
||||
; THUMB: strb r1, [r0, #4]
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=ARM
|
||||
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=ARM
|
||||
|
||||
define i32 @t1(i32* nocapture %ptr) nounwind readonly {
|
||||
entry:
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
|
||||
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
|
||||
; rdar://10418009
|
||||
|
||||
define zeroext i16 @t1(i16* nocapture %a) nounwind uwtable readonly ssp {
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
|
||||
; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
|
||||
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
|
||||
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
|
||||
; rdar://10412592
|
||||
|
||||
; Note: The Thumb code is being generated by the target-independent selector.
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
|
||||
; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=pic -mtriple=arm-apple-ios | FileCheck %s --check-prefix=ARM
|
||||
; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARMv7
|
||||
; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=pic -mtriple=thumbv7-none-linux-gnueabi | FileCheck %s --check-prefix=THUMB-ELF
|
||||
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
|
||||
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=pic -mtriple=arm-apple-ios | FileCheck %s --check-prefix=ARM
|
||||
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARMv7
|
||||
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=pic -mtriple=thumbv7-none-linux-gnueabi | FileCheck %s --check-prefix=THUMB-ELF
|
||||
; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=pic -mtriple=armv7-none-linux-gnueabi | FileCheck %s --check-prefix=ARMv7-ELF
|
||||
|
||||
@g = global i32 0, align 4
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
; RUN: llc -O0 -verify-machineinstrs -optimize-regalloc -regalloc=basic < %s
|
||||
; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort -optimize-regalloc -regalloc=basic < %s
|
||||
; This isn't exactly a useful set of command-line options, but check that it
|
||||
; doesn't crash. (It was crashing because a register was getting redefined.)
|
||||
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
|
||||
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
|
||||
; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
|
||||
|
||||
define i32 @t1(i1 %c) nounwind readnone {
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
; RUN: llc < %s -mtriple=thumbv7-apple-darwin -O0 -verify-machineinstrs -relocation-model=static -arm-long-calls | FileCheck -check-prefix=LONG %s
|
||||
; RUN: llc < %s -mtriple=thumbv7-apple-darwin -O0 -verify-machineinstrs -relocation-model=static | FileCheck -check-prefix=NORM %s
|
||||
; RUN: llc < %s -mtriple=thumbv7-apple-darwin -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=static -arm-long-calls | FileCheck -check-prefix=LONG %s
|
||||
; RUN: llc < %s -mtriple=thumbv7-apple-darwin -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=static | FileCheck -check-prefix=NORM %s
|
||||
|
||||
define void @myadd(float* %sum, float* %addend) nounwind {
|
||||
entry:
|
||||
|
|
@ -24,7 +24,7 @@ entry:
|
|||
store float 0.000000e+00, float* %ztot, align 4
|
||||
store float 1.000000e+00, float* %z, align 4
|
||||
; CHECK-LONG: blx r
|
||||
; CHECK-NORM: bl _myadd
|
||||
; CHECK-NORM: bl {{_?}}myadd
|
||||
call void @myadd(float* %ztot, float* %z)
|
||||
ret i32 0
|
||||
}
|
||||
|
|
|
|||
|
|
@ -144,15 +144,19 @@ define void @test4() {
|
|||
store i32 %b, i32* @test4g
|
||||
ret void
|
||||
|
||||
; THUMB: movw r0, :lower16:L_test4g$non_lazy_ptr
|
||||
; THUMB: movt r0, :upper16:L_test4g$non_lazy_ptr
|
||||
|
||||
; Note that relocations are either movw/movt or constant pool
|
||||
; loads. Different platforms will select different approaches.
|
||||
|
||||
; THUMB: {{(movw r0, :lower16:L_test4g\$non_lazy_ptr)|(ldr.n r0, .LCPI)}}
|
||||
; THUMB: {{(movt r0, :upper16:L_test4g\$non_lazy_ptr)?}}
|
||||
; THUMB: ldr r0, [r0]
|
||||
; THUMB: ldr r1, [r0]
|
||||
; THUMB: adds r1, #1
|
||||
; THUMB: str r1, [r0]
|
||||
|
||||
; ARM: movw r0, :lower16:L_test4g$non_lazy_ptr
|
||||
; ARM: movt r0, :upper16:L_test4g$non_lazy_ptr
|
||||
; ARM: {{(movw r0, :lower16:L_test4g\$non_lazy_ptr)|(ldr r0, .LCPI)}}
|
||||
; ARM: {{(movt r0, :upper16:L_test4g\$non_lazy_ptr)?}}
|
||||
; ARM: ldr r0, [r0]
|
||||
; ARM: ldr r1, [r0]
|
||||
; ARM: add r1, r1, #1
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
; RUN: llc < %s -O0 -mcpu=cortex-a8 | FileCheck %s
|
||||
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mcpu=cortex-a8 | FileCheck %s
|
||||
target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32"
|
||||
target triple = "thumbv7-apple-ios0.0.0"
|
||||
|
||||
|
|
|
|||
|
|
@ -1,7 +1,9 @@
|
|||
;; RUN: llc -O0 -mtriple=armv7-linux-gnueabi -filetype=obj %s -o - | \
|
||||
;; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort \
|
||||
;; RUN: -mtriple=armv7-linux-gnueabi -filetype=obj %s -o - | \
|
||||
;; RUN: llvm-readobj -t | FileCheck -check-prefix=ARM %s
|
||||
|
||||
;; RUN: llc -O0 -mtriple=thumbv7-linux-gnueabi -filetype=obj %s -o - | \
|
||||
;; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort \
|
||||
;; RUN: -mtriple=thumbv7-linux-gnueabi -filetype=obj %s -o - | \
|
||||
;; RUN: llvm-readobj -t | FileCheck -check-prefix=TMB %s
|
||||
|
||||
;; Ensure that if a jump table is generated that it has Mapping Symbols
|
||||
|
|
@ -119,7 +121,7 @@ exit:
|
|||
|
||||
;; ARM: Symbol {
|
||||
;; ARM: Name: $a
|
||||
;; ARM-NEXT: Value: 0xAC
|
||||
;; ARM-NEXT: Value: 0x{{[0-9A-F]+}}
|
||||
;; ARM-NEXT: Size: 0
|
||||
;; ARM-NEXT: Binding: Local
|
||||
;; ARM-NEXT: Type: None
|
||||
|
|
@ -135,7 +137,7 @@ exit:
|
|||
|
||||
;; ARM: Symbol {
|
||||
;; ARM: Name: $d
|
||||
;; ARM-NEXT: Value: 0x30
|
||||
;; ARM-NEXT: Value: 0x{{[0-9A-F]+}}
|
||||
;; ARM-NEXT: Size: 0
|
||||
;; ARM-NEXT: Binding: Local
|
||||
;; ARM-NEXT: Type: None
|
||||
|
|
@ -146,7 +148,7 @@ exit:
|
|||
|
||||
;; TMB: Symbol {
|
||||
;; TMB: Name: $d.2
|
||||
;; TMB-NEXT: Value: 0x16
|
||||
;; TMB-NEXT: Value: 0x{{[0-9A-F]+}}
|
||||
;; TMB-NEXT: Size: 0
|
||||
;; TMB-NEXT: Binding: Local
|
||||
;; TMB-NEXT: Type: None
|
||||
|
|
@ -164,7 +166,7 @@ exit:
|
|||
|
||||
;; TMB: Symbol {
|
||||
;; TMB: Name: $t
|
||||
;; TMB-NEXT: Value: 0x36
|
||||
;; TMB-NEXT: Value: 0x{{[0-9A-F]+}}
|
||||
;; TMB-NEXT: Size: 0
|
||||
;; TMB-NEXT: Binding: Local
|
||||
;; TMB-NEXT: Type: None
|
||||
|
|
|
|||
Loading…
Reference in New Issue