forked from OSchip/llvm-project
AMDGPU/GlobalISel: Do not use terminator copy before waterfall loops
Stop using the _term variants of the mov to save the initial exec value before the waterfall loop. This cannot be glued to the bottom of the block because we may need to spill the result register. Just use a regular mov, like the loops produced on the DAG path. Fixes some verification errors with regalloc fast.
This commit is contained in:
Matt Arsenault
parent
8a16201a0b
commit
bd2c01e937
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@ -718,8 +718,11 @@ bool AMDGPURegisterBankInfo::executeInWaterfallLoop(
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const TargetRegisterClass *WaveRC = TRI->getWaveMaskRegClass();
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const unsigned WaveAndOpc = Subtarget.isWave32() ?
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AMDGPU::S_AND_B32 : AMDGPU::S_AND_B64;
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const unsigned MovTermOpc = Subtarget.isWave32() ?
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AMDGPU::S_MOV_B32_term : AMDGPU::S_MOV_B64_term;
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const unsigned MovExecOpc =
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Subtarget.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64;
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const unsigned MovExecTermOpc =
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Subtarget.isWave32() ? AMDGPU::S_MOV_B32_term : AMDGPU::S_MOV_B64_term;
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const unsigned XorTermOpc = Subtarget.isWave32() ?
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AMDGPU::S_XOR_B32_term : AMDGPU::S_XOR_B64_term;
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const unsigned AndSaveExecOpc = Subtarget.isWave32() ?
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@ -996,12 +999,12 @@ bool AMDGPURegisterBankInfo::executeInWaterfallLoop(
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B.buildInstr(AMDGPU::SI_WATERFALL_LOOP).addMBB(LoopBB);
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// Save the EXEC mask before the loop.
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BuildMI(MBB, MBB.end(), DL, TII->get(MovTermOpc), SaveExecReg)
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BuildMI(MBB, MBB.end(), DL, TII->get(MovExecOpc), SaveExecReg)
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.addReg(ExecReg);
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// Restore the EXEC mask after the loop.
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B.setMBB(*RestoreExecBB);
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B.buildInstr(MovTermOpc)
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B.buildInstr(MovExecTermOpc)
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.addDef(ExecReg)
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.addReg(SaveExecReg);
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@ -0,0 +1,165 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -global-isel -O0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1031 -verify-machineinstrs -o - %s | FileCheck %s
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; Make sure the waterfall loop does not fail the verifier after regalloc fast
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define <4 x float> @waterfall_loop(<8 x i32> %vgpr_srd) {
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; CHECK-LABEL: waterfall_loop:
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; CHECK: ; %bb.0: ; %bb
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: s_waitcnt_vscnt null, 0x0
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; CHECK-NEXT: s_or_saveexec_b32 s4, -1
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; CHECK-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
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; CHECK-NEXT: s_mov_b32 exec_lo, s4
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; CHECK-NEXT: v_mov_b32_e32 v14, v1
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; CHECK-NEXT: v_mov_b32_e32 v13, v2
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; CHECK-NEXT: v_mov_b32_e32 v12, v3
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; CHECK-NEXT: v_mov_b32_e32 v11, v4
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; CHECK-NEXT: v_mov_b32_e32 v10, v5
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; CHECK-NEXT: v_mov_b32_e32 v9, v6
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; CHECK-NEXT: v_mov_b32_e32 v8, v7
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; CHECK-NEXT: ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 killed $exec
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; CHECK-NEXT: v_mov_b32_e32 v1, v14
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; CHECK-NEXT: v_mov_b32_e32 v2, v13
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; CHECK-NEXT: v_mov_b32_e32 v3, v12
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; CHECK-NEXT: v_mov_b32_e32 v4, v11
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; CHECK-NEXT: v_mov_b32_e32 v5, v10
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; CHECK-NEXT: v_mov_b32_e32 v6, v9
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; CHECK-NEXT: v_mov_b32_e32 v7, v8
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; CHECK-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
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; CHECK-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
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; CHECK-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
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; CHECK-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
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; CHECK-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
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; CHECK-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
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; CHECK-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
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; CHECK-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
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; CHECK-NEXT: v_writelane_b32 v15, s30, 0
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; CHECK-NEXT: v_writelane_b32 v15, s31, 1
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; CHECK-NEXT: s_mov_b32 s8, 0
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; CHECK-NEXT: s_mov_b32 s4, s8
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; CHECK-NEXT: s_mov_b32 s5, s8
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; CHECK-NEXT: s_mov_b32 s6, s8
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; CHECK-NEXT: s_mov_b32 s7, s8
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; CHECK-NEXT: v_writelane_b32 v15, s4, 2
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; CHECK-NEXT: v_writelane_b32 v15, s5, 3
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; CHECK-NEXT: v_writelane_b32 v15, s6, 4
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; CHECK-NEXT: v_writelane_b32 v15, s7, 5
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; CHECK-NEXT: s_mov_b32 s6, 0
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; CHECK-NEXT: s_mov_b32 s4, s6
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; CHECK-NEXT: s_mov_b32 s5, s6
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; CHECK-NEXT: v_mov_b32_e32 v9, s5
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; CHECK-NEXT: v_mov_b32_e32 v8, s4
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; CHECK-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
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; CHECK-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
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; CHECK-NEXT: v_mov_b32_e32 v9, v1
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; CHECK-NEXT: v_mov_b32_e32 v8, v0
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; CHECK-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
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; CHECK-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
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; CHECK-NEXT: v_mov_b32_e32 v9, v3
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; CHECK-NEXT: v_mov_b32_e32 v8, v2
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; CHECK-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
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; CHECK-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
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; CHECK-NEXT: v_mov_b32_e32 v9, v5
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; CHECK-NEXT: v_mov_b32_e32 v8, v4
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; CHECK-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
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; CHECK-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
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; CHECK-NEXT: v_mov_b32_e32 v0, v6
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; CHECK-NEXT: v_mov_b32_e32 v1, v7
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; CHECK-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill
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; CHECK-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
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; CHECK-NEXT: s_mov_b32 s4, exec_lo
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; CHECK-NEXT: v_writelane_b32 v15, s4, 6
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; CHECK-NEXT: .LBB0_1: ; =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
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; CHECK-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
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; CHECK-NEXT: v_readlane_b32 s16, v15, 2
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; CHECK-NEXT: v_readlane_b32 s17, v15, 3
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; CHECK-NEXT: v_readlane_b32 s18, v15, 4
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; CHECK-NEXT: v_readlane_b32 s19, v15, 5
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; CHECK-NEXT: buffer_load_dword v2, off, s[0:3], s32 ; 4-byte Folded Reload
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; CHECK-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
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; CHECK-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
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; CHECK-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
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; CHECK-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
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; CHECK-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
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; CHECK-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
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; CHECK-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: v_readfirstlane_b32 s8, v8
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; CHECK-NEXT: v_readfirstlane_b32 s23, v9
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; CHECK-NEXT: s_mov_b32 s4, s8
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; CHECK-NEXT: s_mov_b32 s5, s23
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; CHECK-NEXT: v_writelane_b32 v15, s4, 7
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; CHECK-NEXT: v_writelane_b32 v15, s5, 8
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; CHECK-NEXT: v_cmp_eq_u64_e64 s5, s[4:5], v[8:9]
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; CHECK-NEXT: v_readfirstlane_b32 s22, v6
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; CHECK-NEXT: v_readfirstlane_b32 s21, v7
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; CHECK-NEXT: s_mov_b32 s6, s22
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; CHECK-NEXT: s_mov_b32 s7, s21
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; CHECK-NEXT: v_writelane_b32 v15, s6, 9
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; CHECK-NEXT: v_writelane_b32 v15, s7, 10
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; CHECK-NEXT: v_cmp_eq_u64_e64 s4, s[6:7], v[6:7]
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; CHECK-NEXT: s_and_b32 s5, s4, s5
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; CHECK-NEXT: v_readfirstlane_b32 s20, v4
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; CHECK-NEXT: v_readfirstlane_b32 s7, v5
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; CHECK-NEXT: s_mov_b32 s10, s20
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; CHECK-NEXT: s_mov_b32 s11, s7
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; CHECK-NEXT: v_writelane_b32 v15, s10, 11
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; CHECK-NEXT: v_writelane_b32 v15, s11, 12
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; CHECK-NEXT: v_cmp_eq_u64_e64 s4, s[10:11], v[4:5]
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; CHECK-NEXT: s_and_b32 s9, s4, s5
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; CHECK-NEXT: v_readfirstlane_b32 s6, v2
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; CHECK-NEXT: v_readfirstlane_b32 s5, v3
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; CHECK-NEXT: s_mov_b32 s10, s6
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; CHECK-NEXT: s_mov_b32 s11, s5
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; CHECK-NEXT: v_writelane_b32 v15, s10, 13
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; CHECK-NEXT: v_writelane_b32 v15, s11, 14
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; CHECK-NEXT: v_cmp_eq_u64_e64 s4, s[10:11], v[2:3]
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; CHECK-NEXT: s_and_b32 s4, s4, s9
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; CHECK-NEXT: ; kill: def $sgpr8 killed $sgpr8 def $sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
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; CHECK-NEXT: s_mov_b32 s9, s23
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; CHECK-NEXT: s_mov_b32 s10, s22
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; CHECK-NEXT: s_mov_b32 s11, s21
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; CHECK-NEXT: s_mov_b32 s12, s20
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; CHECK-NEXT: s_mov_b32 s13, s7
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; CHECK-NEXT: s_mov_b32 s14, s6
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; CHECK-NEXT: s_mov_b32 s15, s5
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; CHECK-NEXT: v_writelane_b32 v15, s8, 15
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; CHECK-NEXT: v_writelane_b32 v15, s9, 16
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; CHECK-NEXT: v_writelane_b32 v15, s10, 17
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; CHECK-NEXT: v_writelane_b32 v15, s11, 18
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; CHECK-NEXT: v_writelane_b32 v15, s12, 19
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; CHECK-NEXT: v_writelane_b32 v15, s13, 20
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; CHECK-NEXT: v_writelane_b32 v15, s14, 21
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; CHECK-NEXT: v_writelane_b32 v15, s15, 22
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; CHECK-NEXT: s_and_saveexec_b32 s4, s4
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; CHECK-NEXT: image_sample v0, v[0:1], s[8:15], s[16:19] dmask:0x1 dim:SQ_RSRC_IMG_2D
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
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; CHECK-NEXT: s_xor_b32 exec_lo, exec_lo, s4
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; CHECK-NEXT: s_cbranch_execnz .LBB0_1
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; CHECK-NEXT: ; %bb.2:
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; CHECK-NEXT: v_readlane_b32 s4, v15, 6
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; CHECK-NEXT: s_mov_b32 exec_lo, s4
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; CHECK-NEXT: ; %bb.3:
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; CHECK-NEXT: v_readlane_b32 s4, v15, 0
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; CHECK-NEXT: v_readlane_b32 s5, v15, 1
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; CHECK-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
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; CHECK-NEXT: ; implicit-def: $sgpr6
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; CHECK-NEXT: v_mov_b32_e32 v1, s6
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; CHECK-NEXT: v_mov_b32_e32 v2, s6
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; CHECK-NEXT: v_mov_b32_e32 v3, s6
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; CHECK-NEXT: s_or_saveexec_b32 s6, -1
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; CHECK-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
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; CHECK-NEXT: s_mov_b32 exec_lo, s6
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: s_waitcnt_vscnt null, 0x0
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; CHECK-NEXT: s_setpc_b64 s[4:5]
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bb:
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%ret = tail call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 1, float 0.000000e+00, float 0.000000e+00, <8 x i32> %vgpr_srd, <4 x i32> zeroinitializer, i1 false, i32 0, i32 0)
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ret <4 x float> %ret
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}
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declare <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 immarg, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #0
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attributes #0 = { nounwind readonly willreturn }
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@ -110,7 +110,7 @@ define amdgpu_ps float @raw_buffer_atomic_add_i32__sgpr_val__vgpr_rsrc__sgpr_vof
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; CHECK-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
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; CHECK-NEXT: [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
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; CHECK-NEXT: [[COPY10:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
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; CHECK-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
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; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
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@ -136,7 +136,7 @@ define amdgpu_ps float @raw_buffer_atomic_add_i32__sgpr_val__vgpr_rsrc__sgpr_vof
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; CHECK-NEXT: bb.3:
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; CHECK-NEXT: successors: %bb.4(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
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; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.4:
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; CHECK-NEXT: $vgpr0 = COPY [[BUFFER_ATOMIC_ADD_OFFEN_RTN]]
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@ -165,7 +165,7 @@ define amdgpu_ps void @raw_buffer_atomic_add_i32_noret__sgpr_val__vgpr_rsrc__sgp
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; CHECK-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
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; CHECK-NEXT: [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
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; CHECK-NEXT: [[COPY10:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
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; CHECK-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
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; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
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@ -191,7 +191,7 @@ define amdgpu_ps void @raw_buffer_atomic_add_i32_noret__sgpr_val__vgpr_rsrc__sgp
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; CHECK-NEXT: bb.3:
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; CHECK-NEXT: successors: %bb.4(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
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; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.4:
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; CHECK-NEXT: S_ENDPGM 0
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@ -70,7 +70,7 @@ define amdgpu_ps float @raw_buffer_atomic_cmpswap_i32__sgpr_val__sgpr_cmp__vgpr_
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; CHECK-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
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; CHECK-NEXT: [[COPY11:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
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; CHECK-NEXT: [[COPY12:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
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; CHECK-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
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; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
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@ -98,7 +98,7 @@ define amdgpu_ps float @raw_buffer_atomic_cmpswap_i32__sgpr_val__sgpr_cmp__vgpr_
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; CHECK-NEXT: bb.3:
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; CHECK-NEXT: successors: %bb.4(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
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; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.4:
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; CHECK-NEXT: $vgpr0 = COPY [[COPY13]]
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@ -129,7 +129,7 @@ define amdgpu_ps void @raw_buffer_atomic_cmpswap_i32_noret__sgpr_val__sgpr_cmp__
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; CHECK-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
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; CHECK-NEXT: [[COPY11:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
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; CHECK-NEXT: [[COPY12:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
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; CHECK-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
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; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.2:
|
||||
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -157,7 +157,7 @@ define amdgpu_ps void @raw_buffer_atomic_cmpswap_i32_noret__sgpr_val__sgpr_cmp__
|
|||
; CHECK-NEXT: bb.3:
|
||||
; CHECK-NEXT: successors: %bb.4(0x80000000)
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.4:
|
||||
; CHECK-NEXT: S_ENDPGM 0
|
||||
|
|
|
|||
|
|
@ -152,7 +152,7 @@ define amdgpu_ps void @raw_buffer_atomic_add_f32_noret__sgpr_val__vgpr_rsrc__sgp
|
|||
; GFX908-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
|
||||
; GFX908-NEXT: [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; GFX908-NEXT: [[COPY10:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; GFX908-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; GFX908-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; GFX908-NEXT: {{ $}}
|
||||
; GFX908-NEXT: bb.2:
|
||||
; GFX908-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -178,7 +178,7 @@ define amdgpu_ps void @raw_buffer_atomic_add_f32_noret__sgpr_val__vgpr_rsrc__sgp
|
|||
; GFX908-NEXT: bb.3:
|
||||
; GFX908-NEXT: successors: %bb.4(0x80000000)
|
||||
; GFX908-NEXT: {{ $}}
|
||||
; GFX908-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; GFX908-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; GFX908-NEXT: {{ $}}
|
||||
; GFX908-NEXT: bb.4:
|
||||
; GFX908-NEXT: S_ENDPGM 0
|
||||
|
|
@ -199,7 +199,7 @@ define amdgpu_ps void @raw_buffer_atomic_add_f32_noret__sgpr_val__vgpr_rsrc__sgp
|
|||
; GFX90A-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
|
||||
; GFX90A-NEXT: [[COPY9:%[0-9]+]]:vreg_64_align2 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; GFX90A-NEXT: [[COPY10:%[0-9]+]]:vreg_64_align2 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; GFX90A-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; GFX90A-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; GFX90A-NEXT: {{ $}}
|
||||
; GFX90A-NEXT: bb.2:
|
||||
; GFX90A-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -225,7 +225,7 @@ define amdgpu_ps void @raw_buffer_atomic_add_f32_noret__sgpr_val__vgpr_rsrc__sgp
|
|||
; GFX90A-NEXT: bb.3:
|
||||
; GFX90A-NEXT: successors: %bb.4(0x80000000)
|
||||
; GFX90A-NEXT: {{ $}}
|
||||
; GFX90A-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; GFX90A-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; GFX90A-NEXT: {{ $}}
|
||||
; GFX90A-NEXT: bb.4:
|
||||
; GFX90A-NEXT: S_ENDPGM 0
|
||||
|
|
@ -250,7 +250,7 @@ define amdgpu_ps void @raw_buffer_atomic_add_f32_noret__sgpr_val__vgpr_rsrc__0_v
|
|||
; GFX908-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
|
||||
; GFX908-NEXT: [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; GFX908-NEXT: [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; GFX908-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; GFX908-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; GFX908-NEXT: {{ $}}
|
||||
; GFX908-NEXT: bb.2:
|
||||
; GFX908-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -276,7 +276,7 @@ define amdgpu_ps void @raw_buffer_atomic_add_f32_noret__sgpr_val__vgpr_rsrc__0_v
|
|||
; GFX908-NEXT: bb.3:
|
||||
; GFX908-NEXT: successors: %bb.4(0x80000000)
|
||||
; GFX908-NEXT: {{ $}}
|
||||
; GFX908-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; GFX908-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; GFX908-NEXT: {{ $}}
|
||||
; GFX908-NEXT: bb.4:
|
||||
; GFX908-NEXT: S_ENDPGM 0
|
||||
|
|
@ -295,7 +295,7 @@ define amdgpu_ps void @raw_buffer_atomic_add_f32_noret__sgpr_val__vgpr_rsrc__0_v
|
|||
; GFX90A-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
|
||||
; GFX90A-NEXT: [[COPY7:%[0-9]+]]:vreg_64_align2 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; GFX90A-NEXT: [[COPY8:%[0-9]+]]:vreg_64_align2 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; GFX90A-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; GFX90A-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; GFX90A-NEXT: {{ $}}
|
||||
; GFX90A-NEXT: bb.2:
|
||||
; GFX90A-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -321,7 +321,7 @@ define amdgpu_ps void @raw_buffer_atomic_add_f32_noret__sgpr_val__vgpr_rsrc__0_v
|
|||
; GFX90A-NEXT: bb.3:
|
||||
; GFX90A-NEXT: successors: %bb.4(0x80000000)
|
||||
; GFX90A-NEXT: {{ $}}
|
||||
; GFX90A-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; GFX90A-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; GFX90A-NEXT: {{ $}}
|
||||
; GFX90A-NEXT: bb.4:
|
||||
; GFX90A-NEXT: S_ENDPGM 0
|
||||
|
|
|
|||
|
|
@ -160,7 +160,7 @@ define amdgpu_ps half @raw_buffer_load_format_f16__vgpr_rsrc__sgpr_voffset__vgpr
|
|||
; PACKED-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY4]]
|
||||
; PACKED-NEXT: [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; PACKED-NEXT: [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; PACKED-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; PACKED-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; PACKED-NEXT: {{ $}}
|
||||
; PACKED-NEXT: bb.2:
|
||||
; PACKED-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -186,7 +186,7 @@ define amdgpu_ps half @raw_buffer_load_format_f16__vgpr_rsrc__sgpr_voffset__vgpr
|
|||
; PACKED-NEXT: bb.3:
|
||||
; PACKED-NEXT: successors: %bb.4(0x80000000)
|
||||
; PACKED-NEXT: {{ $}}
|
||||
; PACKED-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; PACKED-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; PACKED-NEXT: {{ $}}
|
||||
; PACKED-NEXT: bb.4:
|
||||
; PACKED-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_FORMAT_D16_X_OFFEN]]
|
||||
|
|
@ -206,7 +206,7 @@ define amdgpu_ps half @raw_buffer_load_format_f16__vgpr_rsrc__sgpr_voffset__vgpr
|
|||
; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY4]]
|
||||
; UNPACKED-NEXT: [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; UNPACKED-NEXT: [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; UNPACKED-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; UNPACKED-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; UNPACKED-NEXT: {{ $}}
|
||||
; UNPACKED-NEXT: bb.2:
|
||||
; UNPACKED-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -232,7 +232,7 @@ define amdgpu_ps half @raw_buffer_load_format_f16__vgpr_rsrc__sgpr_voffset__vgpr
|
|||
; UNPACKED-NEXT: bb.3:
|
||||
; UNPACKED-NEXT: successors: %bb.4(0x80000000)
|
||||
; UNPACKED-NEXT: {{ $}}
|
||||
; UNPACKED-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; UNPACKED-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; UNPACKED-NEXT: {{ $}}
|
||||
; UNPACKED-NEXT: bb.4:
|
||||
; UNPACKED-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN]]
|
||||
|
|
|
|||
|
|
@ -110,7 +110,7 @@ define amdgpu_ps float @raw_buffer_load_format_f32__vgpr_rsrc__sgpr_voffset__vgp
|
|||
; CHECK-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY4]]
|
||||
; CHECK-NEXT: [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; CHECK-NEXT: [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; CHECK-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.2:
|
||||
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -136,7 +136,7 @@ define amdgpu_ps float @raw_buffer_load_format_f32__vgpr_rsrc__sgpr_voffset__vgp
|
|||
; CHECK-NEXT: bb.3:
|
||||
; CHECK-NEXT: successors: %bb.4(0x80000000)
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.4:
|
||||
; CHECK-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_FORMAT_X_OFFEN]]
|
||||
|
|
|
|||
|
|
@ -59,7 +59,7 @@ define amdgpu_ps float @raw_buffer_load_f32__vgpr_rsrc__vgpr_voffset__sgpr_soffs
|
|||
; CHECK-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr2
|
||||
; CHECK-NEXT: [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; CHECK-NEXT: [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; CHECK-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.2:
|
||||
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -82,7 +82,7 @@ define amdgpu_ps float @raw_buffer_load_f32__vgpr_rsrc__vgpr_voffset__sgpr_soffs
|
|||
; CHECK-NEXT: bb.3:
|
||||
; CHECK-NEXT: successors: %bb.4(0x80000000)
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.4:
|
||||
; CHECK-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
|
||||
|
|
@ -107,7 +107,7 @@ define amdgpu_ps float @raw_buffer_load_f32__vgpr_rsrc__vgpr_voffset__vgpr_soffs
|
|||
; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5
|
||||
; CHECK-NEXT: [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; CHECK-NEXT: [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; CHECK-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.2:
|
||||
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -133,7 +133,7 @@ define amdgpu_ps float @raw_buffer_load_f32__vgpr_rsrc__vgpr_voffset__vgpr_soffs
|
|||
; CHECK-NEXT: bb.3:
|
||||
; CHECK-NEXT: successors: %bb.4(0x80000000)
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.4:
|
||||
; CHECK-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
|
||||
|
|
@ -460,7 +460,7 @@ define amdgpu_ps half @raw_buffer_load_f16__vgpr_rsrc__vgpr_voffset__sgpr_soffse
|
|||
; CHECK-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr2
|
||||
; CHECK-NEXT: [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; CHECK-NEXT: [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; CHECK-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.2:
|
||||
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -483,7 +483,7 @@ define amdgpu_ps half @raw_buffer_load_f16__vgpr_rsrc__vgpr_voffset__sgpr_soffse
|
|||
; CHECK-NEXT: bb.3:
|
||||
; CHECK-NEXT: successors: %bb.4(0x80000000)
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.4:
|
||||
; CHECK-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_USHORT_OFFEN]]
|
||||
|
|
@ -508,7 +508,7 @@ define amdgpu_ps float @raw_buffer_load_i8__vgpr_rsrc__vgpr_voffset__sgpr_soffse
|
|||
; CHECK-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr2
|
||||
; CHECK-NEXT: [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; CHECK-NEXT: [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; CHECK-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.2:
|
||||
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -531,7 +531,7 @@ define amdgpu_ps float @raw_buffer_load_i8__vgpr_rsrc__vgpr_voffset__sgpr_soffse
|
|||
; CHECK-NEXT: bb.3:
|
||||
; CHECK-NEXT: successors: %bb.4(0x80000000)
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.4:
|
||||
; CHECK-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_OFFEN]]
|
||||
|
|
@ -783,7 +783,7 @@ define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffs
|
|||
; CHECK-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY5]], [[S_MOV_B32_]], implicit-def $scc
|
||||
; CHECK-NEXT: [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; CHECK-NEXT: [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; CHECK-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.2:
|
||||
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -806,7 +806,7 @@ define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffs
|
|||
; CHECK-NEXT: bb.3:
|
||||
; CHECK-NEXT: successors: %bb.4(0x80000000)
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.4:
|
||||
; CHECK-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
|
||||
|
|
@ -835,7 +835,7 @@ define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffs
|
|||
; CHECK-NEXT: %14:vgpr_32, dead %33:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY4]], [[COPY6]], 0, implicit $exec
|
||||
; CHECK-NEXT: [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; CHECK-NEXT: [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; CHECK-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.2:
|
||||
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -858,7 +858,7 @@ define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffs
|
|||
; CHECK-NEXT: bb.3:
|
||||
; CHECK-NEXT: successors: %bb.4(0x80000000)
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.4:
|
||||
; CHECK-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
|
||||
|
|
|
|||
|
|
@ -169,7 +169,7 @@ define amdgpu_ps void @raw_buffer_store_format__vgpr_rsrc__vgpr_val__vgpr_voffse
|
|||
; UNPACKED-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[V_LSHRREV_B32_e64_]], %subreg.sub1, [[COPY5]], %subreg.sub2, [[V_LSHRREV_B32_e64_1]], %subreg.sub3
|
||||
; UNPACKED-NEXT: [[COPY10:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; UNPACKED-NEXT: [[COPY11:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; UNPACKED-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; UNPACKED-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; UNPACKED-NEXT: {{ $}}
|
||||
; UNPACKED-NEXT: bb.2:
|
||||
; UNPACKED-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -192,7 +192,7 @@ define amdgpu_ps void @raw_buffer_store_format__vgpr_rsrc__vgpr_val__vgpr_voffse
|
|||
; UNPACKED-NEXT: bb.3:
|
||||
; UNPACKED-NEXT: successors: %bb.4(0x80000000)
|
||||
; UNPACKED-NEXT: {{ $}}
|
||||
; UNPACKED-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; UNPACKED-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; UNPACKED-NEXT: {{ $}}
|
||||
; UNPACKED-NEXT: bb.4:
|
||||
; UNPACKED-NEXT: S_ENDPGM 0
|
||||
|
|
@ -213,7 +213,7 @@ define amdgpu_ps void @raw_buffer_store_format__vgpr_rsrc__vgpr_val__vgpr_voffse
|
|||
; PACKED-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr2
|
||||
; PACKED-NEXT: [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; PACKED-NEXT: [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; PACKED-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; PACKED-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; PACKED-NEXT: {{ $}}
|
||||
; PACKED-NEXT: bb.2:
|
||||
; PACKED-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -236,7 +236,7 @@ define amdgpu_ps void @raw_buffer_store_format__vgpr_rsrc__vgpr_val__vgpr_voffse
|
|||
; PACKED-NEXT: bb.3:
|
||||
; PACKED-NEXT: successors: %bb.4(0x80000000)
|
||||
; PACKED-NEXT: {{ $}}
|
||||
; PACKED-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; PACKED-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; PACKED-NEXT: {{ $}}
|
||||
; PACKED-NEXT: bb.4:
|
||||
; PACKED-NEXT: S_ENDPGM 0
|
||||
|
|
@ -466,7 +466,7 @@ define amdgpu_ps void @raw_buffer_store_format__vgpr_rsrc__vgpr_val__vgpr_voffse
|
|||
; UNPACKED-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[V_LSHRREV_B32_e64_]], %subreg.sub1, [[COPY5]], %subreg.sub2, [[V_LSHRREV_B32_e64_1]], %subreg.sub3
|
||||
; UNPACKED-NEXT: [[COPY11:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; UNPACKED-NEXT: [[COPY12:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; UNPACKED-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; UNPACKED-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; UNPACKED-NEXT: {{ $}}
|
||||
; UNPACKED-NEXT: bb.2:
|
||||
; UNPACKED-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -489,7 +489,7 @@ define amdgpu_ps void @raw_buffer_store_format__vgpr_rsrc__vgpr_val__vgpr_voffse
|
|||
; UNPACKED-NEXT: bb.3:
|
||||
; UNPACKED-NEXT: successors: %bb.4(0x80000000)
|
||||
; UNPACKED-NEXT: {{ $}}
|
||||
; UNPACKED-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; UNPACKED-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; UNPACKED-NEXT: {{ $}}
|
||||
; UNPACKED-NEXT: bb.4:
|
||||
; UNPACKED-NEXT: S_ENDPGM 0
|
||||
|
|
@ -513,7 +513,7 @@ define amdgpu_ps void @raw_buffer_store_format__vgpr_rsrc__vgpr_val__vgpr_voffse
|
|||
; PACKED-NEXT: %13:vgpr_32, dead %33:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY6]], [[COPY8]], 0, implicit $exec
|
||||
; PACKED-NEXT: [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; PACKED-NEXT: [[COPY10:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; PACKED-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; PACKED-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; PACKED-NEXT: {{ $}}
|
||||
; PACKED-NEXT: bb.2:
|
||||
; PACKED-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -536,7 +536,7 @@ define amdgpu_ps void @raw_buffer_store_format__vgpr_rsrc__vgpr_val__vgpr_voffse
|
|||
; PACKED-NEXT: bb.3:
|
||||
; PACKED-NEXT: successors: %bb.4(0x80000000)
|
||||
; PACKED-NEXT: {{ $}}
|
||||
; PACKED-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; PACKED-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; PACKED-NEXT: {{ $}}
|
||||
; PACKED-NEXT: bb.4:
|
||||
; PACKED-NEXT: S_ENDPGM 0
|
||||
|
|
|
|||
|
|
@ -125,7 +125,7 @@ define amdgpu_ps void @raw_buffer_store_format__vgpr_rsrc__vgpr_val__vgpr_voffse
|
|||
; CHECK-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr2
|
||||
; CHECK-NEXT: [[COPY10:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; CHECK-NEXT: [[COPY11:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; CHECK-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.2:
|
||||
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -148,7 +148,7 @@ define amdgpu_ps void @raw_buffer_store_format__vgpr_rsrc__vgpr_val__vgpr_voffse
|
|||
; CHECK-NEXT: bb.3:
|
||||
; CHECK-NEXT: successors: %bb.4(0x80000000)
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.4:
|
||||
; CHECK-NEXT: S_ENDPGM 0
|
||||
|
|
@ -292,7 +292,7 @@ define amdgpu_ps void @raw_buffer_store_format__vgpr_rsrc__vgpr_val__vgpr_voffse
|
|||
; CHECK-NEXT: %15:vgpr_32, dead %35:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY8]], [[COPY10]], 0, implicit $exec
|
||||
; CHECK-NEXT: [[COPY11:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; CHECK-NEXT: [[COPY12:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; CHECK-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.2:
|
||||
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -315,7 +315,7 @@ define amdgpu_ps void @raw_buffer_store_format__vgpr_rsrc__vgpr_val__vgpr_voffse
|
|||
; CHECK-NEXT: bb.3:
|
||||
; CHECK-NEXT: successors: %bb.4(0x80000000)
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.4:
|
||||
; CHECK-NEXT: S_ENDPGM 0
|
||||
|
|
|
|||
|
|
@ -61,7 +61,7 @@ define amdgpu_ps void @raw_buffer_store__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr
|
|||
; CHECK-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2
|
||||
; CHECK-NEXT: [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; CHECK-NEXT: [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; CHECK-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.2:
|
||||
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -84,7 +84,7 @@ define amdgpu_ps void @raw_buffer_store__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr
|
|||
; CHECK-NEXT: bb.3:
|
||||
; CHECK-NEXT: successors: %bb.4(0x80000000)
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.4:
|
||||
; CHECK-NEXT: S_ENDPGM 0
|
||||
|
|
@ -107,7 +107,7 @@ define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__vgpr
|
|||
; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; CHECK-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
|
||||
; CHECK-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.2:
|
||||
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -122,7 +122,7 @@ define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__vgpr
|
|||
; CHECK-NEXT: bb.3:
|
||||
; CHECK-NEXT: successors: %bb.4(0x80000000)
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.4:
|
||||
; CHECK-NEXT: S_ENDPGM 0
|
||||
|
|
@ -147,7 +147,7 @@ define amdgpu_ps void @raw_buffer_store__vgpr_rsrc__vgpr_val__vgpr_voffset__vgpr
|
|||
; CHECK-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr6
|
||||
; CHECK-NEXT: [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; CHECK-NEXT: [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; CHECK-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.2:
|
||||
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -173,7 +173,7 @@ define amdgpu_ps void @raw_buffer_store__vgpr_rsrc__vgpr_val__vgpr_voffset__vgpr
|
|||
; CHECK-NEXT: bb.3:
|
||||
; CHECK-NEXT: successors: %bb.4(0x80000000)
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.4:
|
||||
; CHECK-NEXT: S_ENDPGM 0
|
||||
|
|
@ -497,7 +497,7 @@ define amdgpu_ps void @raw_buffer_store__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr
|
|||
; CHECK-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr2
|
||||
; CHECK-NEXT: [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; CHECK-NEXT: [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; CHECK-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.2:
|
||||
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -520,7 +520,7 @@ define amdgpu_ps void @raw_buffer_store__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr
|
|||
; CHECK-NEXT: bb.3:
|
||||
; CHECK-NEXT: successors: %bb.4(0x80000000)
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.4:
|
||||
; CHECK-NEXT: S_ENDPGM 0
|
||||
|
|
@ -750,7 +750,7 @@ define amdgpu_ps void @raw_buffer_store__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr
|
|||
; CHECK-NEXT: %14:vgpr_32, dead %33:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec
|
||||
; CHECK-NEXT: [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; CHECK-NEXT: [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; CHECK-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.2:
|
||||
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -773,7 +773,7 @@ define amdgpu_ps void @raw_buffer_store__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr
|
|||
; CHECK-NEXT: bb.3:
|
||||
; CHECK-NEXT: successors: %bb.4(0x80000000)
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.4:
|
||||
; CHECK-NEXT: S_ENDPGM 0
|
||||
|
|
@ -800,7 +800,7 @@ define amdgpu_ps void @raw_buffer_store__vgpr_rsrc__vgpr_val__5000_voffset__sgpr
|
|||
; CHECK-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
|
||||
; CHECK-NEXT: [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; CHECK-NEXT: [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; CHECK-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.2:
|
||||
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -823,7 +823,7 @@ define amdgpu_ps void @raw_buffer_store__vgpr_rsrc__vgpr_val__5000_voffset__sgpr
|
|||
; CHECK-NEXT: bb.3:
|
||||
; CHECK-NEXT: successors: %bb.4(0x80000000)
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.4:
|
||||
; CHECK-NEXT: S_ENDPGM 0
|
||||
|
|
|
|||
|
|
@ -158,7 +158,7 @@ define amdgpu_ps half @raw_tbuffer_load_f16__vgpr_rsrc__sgpr_voffset__vgpr_soffs
|
|||
; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY4]]
|
||||
; UNPACKED-NEXT: [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; UNPACKED-NEXT: [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; UNPACKED-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; UNPACKED-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; UNPACKED-NEXT: {{ $}}
|
||||
; UNPACKED-NEXT: bb.2:
|
||||
; UNPACKED-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -184,7 +184,7 @@ define amdgpu_ps half @raw_tbuffer_load_f16__vgpr_rsrc__sgpr_voffset__vgpr_soffs
|
|||
; UNPACKED-NEXT: bb.3:
|
||||
; UNPACKED-NEXT: successors: %bb.4(0x80000000)
|
||||
; UNPACKED-NEXT: {{ $}}
|
||||
; UNPACKED-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; UNPACKED-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; UNPACKED-NEXT: {{ $}}
|
||||
; UNPACKED-NEXT: bb.4:
|
||||
; UNPACKED-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN]]
|
||||
|
|
@ -204,7 +204,7 @@ define amdgpu_ps half @raw_tbuffer_load_f16__vgpr_rsrc__sgpr_voffset__vgpr_soffs
|
|||
; PACKED-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY4]]
|
||||
; PACKED-NEXT: [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; PACKED-NEXT: [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; PACKED-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; PACKED-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; PACKED-NEXT: {{ $}}
|
||||
; PACKED-NEXT: bb.2:
|
||||
; PACKED-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -230,7 +230,7 @@ define amdgpu_ps half @raw_tbuffer_load_f16__vgpr_rsrc__sgpr_voffset__vgpr_soffs
|
|||
; PACKED-NEXT: bb.3:
|
||||
; PACKED-NEXT: successors: %bb.4(0x80000000)
|
||||
; PACKED-NEXT: {{ $}}
|
||||
; PACKED-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; PACKED-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; PACKED-NEXT: {{ $}}
|
||||
; PACKED-NEXT: bb.4:
|
||||
; PACKED-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_D16_X_OFFEN]]
|
||||
|
|
|
|||
|
|
@ -108,7 +108,7 @@ define amdgpu_ps float @raw_tbuffer_load_f32__vgpr_rsrc__sgpr_voffset__vgpr_soff
|
|||
; CHECK-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY4]]
|
||||
; CHECK-NEXT: [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; CHECK-NEXT: [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; CHECK-NEXT: [[S_MOV_B32_term:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32_term $exec_lo
|
||||
; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.2:
|
||||
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -134,7 +134,7 @@ define amdgpu_ps float @raw_tbuffer_load_f32__vgpr_rsrc__sgpr_voffset__vgpr_soff
|
|||
; CHECK-NEXT: bb.3:
|
||||
; CHECK-NEXT: successors: %bb.4(0x80000000)
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: $exec_lo = S_MOV_B32_term [[S_MOV_B32_term]]
|
||||
; CHECK-NEXT: $exec_lo = S_MOV_B32_term [[S_MOV_B32_]]
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.4:
|
||||
; CHECK-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_X_OFFEN]]
|
||||
|
|
|
|||
|
|
@ -137,7 +137,7 @@ define amdgpu_ps void @raw_tbuffer_store_f16__vgpr_rsrc__vgpr_voffset__sgpr_soff
|
|||
; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2
|
||||
; UNPACKED-NEXT: [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; UNPACKED-NEXT: [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; UNPACKED-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; UNPACKED-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; UNPACKED-NEXT: {{ $}}
|
||||
; UNPACKED-NEXT: bb.2:
|
||||
; UNPACKED-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -160,7 +160,7 @@ define amdgpu_ps void @raw_tbuffer_store_f16__vgpr_rsrc__vgpr_voffset__sgpr_soff
|
|||
; UNPACKED-NEXT: bb.3:
|
||||
; UNPACKED-NEXT: successors: %bb.4(0x80000000)
|
||||
; UNPACKED-NEXT: {{ $}}
|
||||
; UNPACKED-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; UNPACKED-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; UNPACKED-NEXT: {{ $}}
|
||||
; UNPACKED-NEXT: bb.4:
|
||||
; UNPACKED-NEXT: S_ENDPGM 0
|
||||
|
|
@ -179,7 +179,7 @@ define amdgpu_ps void @raw_tbuffer_store_f16__vgpr_rsrc__vgpr_voffset__sgpr_soff
|
|||
; PACKED-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2
|
||||
; PACKED-NEXT: [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; PACKED-NEXT: [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; PACKED-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; PACKED-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; PACKED-NEXT: {{ $}}
|
||||
; PACKED-NEXT: bb.2:
|
||||
; PACKED-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -202,7 +202,7 @@ define amdgpu_ps void @raw_tbuffer_store_f16__vgpr_rsrc__vgpr_voffset__sgpr_soff
|
|||
; PACKED-NEXT: bb.3:
|
||||
; PACKED-NEXT: successors: %bb.4(0x80000000)
|
||||
; PACKED-NEXT: {{ $}}
|
||||
; PACKED-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; PACKED-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; PACKED-NEXT: {{ $}}
|
||||
; PACKED-NEXT: bb.4:
|
||||
; PACKED-NEXT: S_ENDPGM 0
|
||||
|
|
@ -227,7 +227,7 @@ define amdgpu_ps void @raw_tbuffer_store_f16__vgpr_rsrc__vgpr_voffset__vgpr_soff
|
|||
; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr6
|
||||
; UNPACKED-NEXT: [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; UNPACKED-NEXT: [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; UNPACKED-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; UNPACKED-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; UNPACKED-NEXT: {{ $}}
|
||||
; UNPACKED-NEXT: bb.2:
|
||||
; UNPACKED-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -253,7 +253,7 @@ define amdgpu_ps void @raw_tbuffer_store_f16__vgpr_rsrc__vgpr_voffset__vgpr_soff
|
|||
; UNPACKED-NEXT: bb.3:
|
||||
; UNPACKED-NEXT: successors: %bb.4(0x80000000)
|
||||
; UNPACKED-NEXT: {{ $}}
|
||||
; UNPACKED-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; UNPACKED-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; UNPACKED-NEXT: {{ $}}
|
||||
; UNPACKED-NEXT: bb.4:
|
||||
; UNPACKED-NEXT: S_ENDPGM 0
|
||||
|
|
@ -272,7 +272,7 @@ define amdgpu_ps void @raw_tbuffer_store_f16__vgpr_rsrc__vgpr_voffset__vgpr_soff
|
|||
; PACKED-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr6
|
||||
; PACKED-NEXT: [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; PACKED-NEXT: [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; PACKED-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; PACKED-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; PACKED-NEXT: {{ $}}
|
||||
; PACKED-NEXT: bb.2:
|
||||
; PACKED-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -298,7 +298,7 @@ define amdgpu_ps void @raw_tbuffer_store_f16__vgpr_rsrc__vgpr_voffset__vgpr_soff
|
|||
; PACKED-NEXT: bb.3:
|
||||
; PACKED-NEXT: successors: %bb.4(0x80000000)
|
||||
; PACKED-NEXT: {{ $}}
|
||||
; PACKED-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; PACKED-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; PACKED-NEXT: {{ $}}
|
||||
; PACKED-NEXT: bb.4:
|
||||
; PACKED-NEXT: S_ENDPGM 0
|
||||
|
|
@ -324,7 +324,7 @@ define amdgpu_ps void @raw_tbuffer_store_f16__vgpr_rsrc__sgpr_voffset__vgpr_soff
|
|||
; UNPACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
|
||||
; UNPACKED-NEXT: [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; UNPACKED-NEXT: [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; UNPACKED-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; UNPACKED-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; UNPACKED-NEXT: {{ $}}
|
||||
; UNPACKED-NEXT: bb.2:
|
||||
; UNPACKED-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -350,7 +350,7 @@ define amdgpu_ps void @raw_tbuffer_store_f16__vgpr_rsrc__sgpr_voffset__vgpr_soff
|
|||
; UNPACKED-NEXT: bb.3:
|
||||
; UNPACKED-NEXT: successors: %bb.4(0x80000000)
|
||||
; UNPACKED-NEXT: {{ $}}
|
||||
; UNPACKED-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; UNPACKED-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; UNPACKED-NEXT: {{ $}}
|
||||
; UNPACKED-NEXT: bb.4:
|
||||
; UNPACKED-NEXT: S_ENDPGM 0
|
||||
|
|
@ -370,7 +370,7 @@ define amdgpu_ps void @raw_tbuffer_store_f16__vgpr_rsrc__sgpr_voffset__vgpr_soff
|
|||
; PACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
|
||||
; PACKED-NEXT: [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; PACKED-NEXT: [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; PACKED-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; PACKED-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; PACKED-NEXT: {{ $}}
|
||||
; PACKED-NEXT: bb.2:
|
||||
; PACKED-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -396,7 +396,7 @@ define amdgpu_ps void @raw_tbuffer_store_f16__vgpr_rsrc__sgpr_voffset__vgpr_soff
|
|||
; PACKED-NEXT: bb.3:
|
||||
; PACKED-NEXT: successors: %bb.4(0x80000000)
|
||||
; PACKED-NEXT: {{ $}}
|
||||
; PACKED-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; PACKED-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; PACKED-NEXT: {{ $}}
|
||||
; PACKED-NEXT: bb.4:
|
||||
; PACKED-NEXT: S_ENDPGM 0
|
||||
|
|
|
|||
|
|
@ -52,7 +52,7 @@ define amdgpu_ps void @raw_tbuffer_store_i8__vgpr_rsrc__vgpr_voffset__sgpr_soffs
|
|||
; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2
|
||||
; UNPACKED-NEXT: [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; UNPACKED-NEXT: [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; UNPACKED-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; UNPACKED-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; UNPACKED-NEXT: {{ $}}
|
||||
; UNPACKED-NEXT: bb.2:
|
||||
; UNPACKED-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -75,7 +75,7 @@ define amdgpu_ps void @raw_tbuffer_store_i8__vgpr_rsrc__vgpr_voffset__sgpr_soffs
|
|||
; UNPACKED-NEXT: bb.3:
|
||||
; UNPACKED-NEXT: successors: %bb.4(0x80000000)
|
||||
; UNPACKED-NEXT: {{ $}}
|
||||
; UNPACKED-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; UNPACKED-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; UNPACKED-NEXT: {{ $}}
|
||||
; UNPACKED-NEXT: bb.4:
|
||||
; UNPACKED-NEXT: S_ENDPGM 0
|
||||
|
|
@ -94,7 +94,7 @@ define amdgpu_ps void @raw_tbuffer_store_i8__vgpr_rsrc__vgpr_voffset__sgpr_soffs
|
|||
; PACKED-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2
|
||||
; PACKED-NEXT: [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; PACKED-NEXT: [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; PACKED-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; PACKED-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; PACKED-NEXT: {{ $}}
|
||||
; PACKED-NEXT: bb.2:
|
||||
; PACKED-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -117,7 +117,7 @@ define amdgpu_ps void @raw_tbuffer_store_i8__vgpr_rsrc__vgpr_voffset__sgpr_soffs
|
|||
; PACKED-NEXT: bb.3:
|
||||
; PACKED-NEXT: successors: %bb.4(0x80000000)
|
||||
; PACKED-NEXT: {{ $}}
|
||||
; PACKED-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; PACKED-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; PACKED-NEXT: {{ $}}
|
||||
; PACKED-NEXT: bb.4:
|
||||
; PACKED-NEXT: S_ENDPGM 0
|
||||
|
|
@ -142,7 +142,7 @@ define amdgpu_ps void @raw_tbuffer_store_i8__vgpr_rsrc__vgpr_voffset__vgpr_soffs
|
|||
; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr6
|
||||
; UNPACKED-NEXT: [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; UNPACKED-NEXT: [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; UNPACKED-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; UNPACKED-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; UNPACKED-NEXT: {{ $}}
|
||||
; UNPACKED-NEXT: bb.2:
|
||||
; UNPACKED-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -168,7 +168,7 @@ define amdgpu_ps void @raw_tbuffer_store_i8__vgpr_rsrc__vgpr_voffset__vgpr_soffs
|
|||
; UNPACKED-NEXT: bb.3:
|
||||
; UNPACKED-NEXT: successors: %bb.4(0x80000000)
|
||||
; UNPACKED-NEXT: {{ $}}
|
||||
; UNPACKED-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; UNPACKED-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; UNPACKED-NEXT: {{ $}}
|
||||
; UNPACKED-NEXT: bb.4:
|
||||
; UNPACKED-NEXT: S_ENDPGM 0
|
||||
|
|
@ -187,7 +187,7 @@ define amdgpu_ps void @raw_tbuffer_store_i8__vgpr_rsrc__vgpr_voffset__vgpr_soffs
|
|||
; PACKED-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr6
|
||||
; PACKED-NEXT: [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; PACKED-NEXT: [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; PACKED-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; PACKED-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; PACKED-NEXT: {{ $}}
|
||||
; PACKED-NEXT: bb.2:
|
||||
; PACKED-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -213,7 +213,7 @@ define amdgpu_ps void @raw_tbuffer_store_i8__vgpr_rsrc__vgpr_voffset__vgpr_soffs
|
|||
; PACKED-NEXT: bb.3:
|
||||
; PACKED-NEXT: successors: %bb.4(0x80000000)
|
||||
; PACKED-NEXT: {{ $}}
|
||||
; PACKED-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; PACKED-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; PACKED-NEXT: {{ $}}
|
||||
; PACKED-NEXT: bb.4:
|
||||
; PACKED-NEXT: S_ENDPGM 0
|
||||
|
|
@ -239,7 +239,7 @@ define amdgpu_ps void @raw_tbuffer_store_i8__vgpr_rsrc__sgpr_voffset__vgpr_soffs
|
|||
; UNPACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
|
||||
; UNPACKED-NEXT: [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; UNPACKED-NEXT: [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; UNPACKED-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; UNPACKED-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; UNPACKED-NEXT: {{ $}}
|
||||
; UNPACKED-NEXT: bb.2:
|
||||
; UNPACKED-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -265,7 +265,7 @@ define amdgpu_ps void @raw_tbuffer_store_i8__vgpr_rsrc__sgpr_voffset__vgpr_soffs
|
|||
; UNPACKED-NEXT: bb.3:
|
||||
; UNPACKED-NEXT: successors: %bb.4(0x80000000)
|
||||
; UNPACKED-NEXT: {{ $}}
|
||||
; UNPACKED-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; UNPACKED-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; UNPACKED-NEXT: {{ $}}
|
||||
; UNPACKED-NEXT: bb.4:
|
||||
; UNPACKED-NEXT: S_ENDPGM 0
|
||||
|
|
@ -285,7 +285,7 @@ define amdgpu_ps void @raw_tbuffer_store_i8__vgpr_rsrc__sgpr_voffset__vgpr_soffs
|
|||
; PACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
|
||||
; PACKED-NEXT: [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; PACKED-NEXT: [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; PACKED-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; PACKED-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; PACKED-NEXT: {{ $}}
|
||||
; PACKED-NEXT: bb.2:
|
||||
; PACKED-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -311,7 +311,7 @@ define amdgpu_ps void @raw_tbuffer_store_i8__vgpr_rsrc__sgpr_voffset__vgpr_soffs
|
|||
; PACKED-NEXT: bb.3:
|
||||
; PACKED-NEXT: successors: %bb.4(0x80000000)
|
||||
; PACKED-NEXT: {{ $}}
|
||||
; PACKED-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; PACKED-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; PACKED-NEXT: {{ $}}
|
||||
; PACKED-NEXT: bb.4:
|
||||
; PACKED-NEXT: S_ENDPGM 0
|
||||
|
|
|
|||
|
|
@ -128,7 +128,7 @@ define amdgpu_ps void @raw_tbuffer_store_f32__vgpr_rsrc__vgpr_voffset__sgpr_soff
|
|||
; CHECK-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2
|
||||
; CHECK-NEXT: [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; CHECK-NEXT: [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; CHECK-NEXT: [[S_MOV_B32_term:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32_term $exec_lo
|
||||
; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.2:
|
||||
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -151,7 +151,7 @@ define amdgpu_ps void @raw_tbuffer_store_f32__vgpr_rsrc__vgpr_voffset__sgpr_soff
|
|||
; CHECK-NEXT: bb.3:
|
||||
; CHECK-NEXT: successors: %bb.4(0x80000000)
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: $exec_lo = S_MOV_B32_term [[S_MOV_B32_term]]
|
||||
; CHECK-NEXT: $exec_lo = S_MOV_B32_term [[S_MOV_B32_]]
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.4:
|
||||
; CHECK-NEXT: S_ENDPGM 0
|
||||
|
|
@ -176,7 +176,7 @@ define amdgpu_ps void @raw_tbuffer_store_f32__vgpr_rsrc__vgpr_voffset__vgpr_soff
|
|||
; CHECK-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr6
|
||||
; CHECK-NEXT: [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; CHECK-NEXT: [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; CHECK-NEXT: [[S_MOV_B32_term:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32_term $exec_lo
|
||||
; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.2:
|
||||
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -202,7 +202,7 @@ define amdgpu_ps void @raw_tbuffer_store_f32__vgpr_rsrc__vgpr_voffset__vgpr_soff
|
|||
; CHECK-NEXT: bb.3:
|
||||
; CHECK-NEXT: successors: %bb.4(0x80000000)
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: $exec_lo = S_MOV_B32_term [[S_MOV_B32_term]]
|
||||
; CHECK-NEXT: $exec_lo = S_MOV_B32_term [[S_MOV_B32_]]
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.4:
|
||||
; CHECK-NEXT: S_ENDPGM 0
|
||||
|
|
@ -228,7 +228,7 @@ define amdgpu_ps void @raw_tbuffer_store_f32__vgpr_rsrc__sgpr_voffset__vgpr_soff
|
|||
; CHECK-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
|
||||
; CHECK-NEXT: [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; CHECK-NEXT: [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; CHECK-NEXT: [[S_MOV_B32_term:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32_term $exec_lo
|
||||
; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.2:
|
||||
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -254,7 +254,7 @@ define amdgpu_ps void @raw_tbuffer_store_f32__vgpr_rsrc__sgpr_voffset__vgpr_soff
|
|||
; CHECK-NEXT: bb.3:
|
||||
; CHECK-NEXT: successors: %bb.4(0x80000000)
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: $exec_lo = S_MOV_B32_term [[S_MOV_B32_term]]
|
||||
; CHECK-NEXT: $exec_lo = S_MOV_B32_term [[S_MOV_B32_]]
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.4:
|
||||
; CHECK-NEXT: S_ENDPGM 0
|
||||
|
|
@ -586,7 +586,7 @@ define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soff
|
|||
; CHECK-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY6]], [[S_MOV_B32_]], implicit-def $scc
|
||||
; CHECK-NEXT: [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; CHECK-NEXT: [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; CHECK-NEXT: [[S_MOV_B32_term:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32_term $exec_lo
|
||||
; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.2:
|
||||
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -609,7 +609,7 @@ define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soff
|
|||
; CHECK-NEXT: bb.3:
|
||||
; CHECK-NEXT: successors: %bb.4(0x80000000)
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: $exec_lo = S_MOV_B32_term [[S_MOV_B32_term]]
|
||||
; CHECK-NEXT: $exec_lo = S_MOV_B32_term [[S_MOV_B32_1]]
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.4:
|
||||
; CHECK-NEXT: S_ENDPGM 0
|
||||
|
|
@ -638,7 +638,7 @@ define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soff
|
|||
; CHECK-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec
|
||||
; CHECK-NEXT: [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; CHECK-NEXT: [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; CHECK-NEXT: [[S_MOV_B32_term:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32_term $exec_lo
|
||||
; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.2:
|
||||
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -661,7 +661,7 @@ define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soff
|
|||
; CHECK-NEXT: bb.3:
|
||||
; CHECK-NEXT: successors: %bb.4(0x80000000)
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: $exec_lo = S_MOV_B32_term [[S_MOV_B32_term]]
|
||||
; CHECK-NEXT: $exec_lo = S_MOV_B32_term [[S_MOV_B32_1]]
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.4:
|
||||
; CHECK-NEXT: S_ENDPGM 0
|
||||
|
|
|
|||
|
|
@ -2698,7 +2698,7 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc(<4 x i32> %rsrc, i32 inreg %
|
|||
; GFX6-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
|
||||
; GFX6-NEXT: [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; GFX6-NEXT: [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; GFX6-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; GFX6-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; GFX6-NEXT: {{ $}}
|
||||
; GFX6-NEXT: bb.2:
|
||||
; GFX6-NEXT: successors: %bb.3, %bb.2
|
||||
|
|
@ -2719,7 +2719,7 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc(<4 x i32> %rsrc, i32 inreg %
|
|||
; GFX6-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
|
||||
; GFX6-NEXT: {{ $}}
|
||||
; GFX6-NEXT: bb.3:
|
||||
; GFX6-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; GFX6-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; GFX6-NEXT: {{ $}}
|
||||
; GFX6-NEXT: bb.4:
|
||||
; GFX6-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
|
||||
|
|
@ -2738,7 +2738,7 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc(<4 x i32> %rsrc, i32 inreg %
|
|||
; GFX7-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
|
||||
; GFX7-NEXT: [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; GFX7-NEXT: [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; GFX7-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; GFX7-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; GFX7-NEXT: {{ $}}
|
||||
; GFX7-NEXT: bb.2:
|
||||
; GFX7-NEXT: successors: %bb.3, %bb.2
|
||||
|
|
@ -2759,7 +2759,7 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc(<4 x i32> %rsrc, i32 inreg %
|
|||
; GFX7-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
|
||||
; GFX7-NEXT: {{ $}}
|
||||
; GFX7-NEXT: bb.3:
|
||||
; GFX7-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; GFX7-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; GFX7-NEXT: {{ $}}
|
||||
; GFX7-NEXT: bb.4:
|
||||
; GFX7-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
|
||||
|
|
@ -2778,7 +2778,7 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc(<4 x i32> %rsrc, i32 inreg %
|
|||
; GFX8-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
|
||||
; GFX8-NEXT: [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; GFX8-NEXT: [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; GFX8-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; GFX8-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; GFX8-NEXT: {{ $}}
|
||||
; GFX8-NEXT: bb.2:
|
||||
; GFX8-NEXT: successors: %bb.3, %bb.2
|
||||
|
|
@ -2799,7 +2799,7 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc(<4 x i32> %rsrc, i32 inreg %
|
|||
; GFX8-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
|
||||
; GFX8-NEXT: {{ $}}
|
||||
; GFX8-NEXT: bb.3:
|
||||
; GFX8-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; GFX8-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; GFX8-NEXT: {{ $}}
|
||||
; GFX8-NEXT: bb.4:
|
||||
; GFX8-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
|
||||
|
|
@ -2822,7 +2822,7 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_soffset_add_4092(<4 x i32> %
|
|||
; GFX6-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2
|
||||
; GFX6-NEXT: [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; GFX6-NEXT: [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; GFX6-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; GFX6-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; GFX6-NEXT: {{ $}}
|
||||
; GFX6-NEXT: bb.2:
|
||||
; GFX6-NEXT: successors: %bb.3, %bb.2
|
||||
|
|
@ -2843,7 +2843,7 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_soffset_add_4092(<4 x i32> %
|
|||
; GFX6-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
|
||||
; GFX6-NEXT: {{ $}}
|
||||
; GFX6-NEXT: bb.3:
|
||||
; GFX6-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; GFX6-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; GFX6-NEXT: {{ $}}
|
||||
; GFX6-NEXT: bb.4:
|
||||
; GFX6-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFSET]]
|
||||
|
|
@ -2860,7 +2860,7 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_soffset_add_4092(<4 x i32> %
|
|||
; GFX7-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2
|
||||
; GFX7-NEXT: [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; GFX7-NEXT: [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; GFX7-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; GFX7-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; GFX7-NEXT: {{ $}}
|
||||
; GFX7-NEXT: bb.2:
|
||||
; GFX7-NEXT: successors: %bb.3, %bb.2
|
||||
|
|
@ -2881,7 +2881,7 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_soffset_add_4092(<4 x i32> %
|
|||
; GFX7-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
|
||||
; GFX7-NEXT: {{ $}}
|
||||
; GFX7-NEXT: bb.3:
|
||||
; GFX7-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; GFX7-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; GFX7-NEXT: {{ $}}
|
||||
; GFX7-NEXT: bb.4:
|
||||
; GFX7-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFSET]]
|
||||
|
|
@ -2898,7 +2898,7 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_soffset_add_4092(<4 x i32> %
|
|||
; GFX8-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2
|
||||
; GFX8-NEXT: [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; GFX8-NEXT: [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; GFX8-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; GFX8-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; GFX8-NEXT: {{ $}}
|
||||
; GFX8-NEXT: bb.2:
|
||||
; GFX8-NEXT: successors: %bb.3, %bb.2
|
||||
|
|
@ -2919,7 +2919,7 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_soffset_add_4092(<4 x i32> %
|
|||
; GFX8-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
|
||||
; GFX8-NEXT: {{ $}}
|
||||
; GFX8-NEXT: bb.3:
|
||||
; GFX8-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; GFX8-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; GFX8-NEXT: {{ $}}
|
||||
; GFX8-NEXT: bb.4:
|
||||
; GFX8-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFSET]]
|
||||
|
|
@ -2947,7 +2947,7 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_soffset_add_4096(<4 x i32> %
|
|||
; GFX6-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0
|
||||
; GFX6-NEXT: [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; GFX6-NEXT: [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; GFX6-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; GFX6-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; GFX6-NEXT: {{ $}}
|
||||
; GFX6-NEXT: bb.2:
|
||||
; GFX6-NEXT: successors: %bb.3, %bb.2
|
||||
|
|
@ -2968,7 +2968,7 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_soffset_add_4096(<4 x i32> %
|
|||
; GFX6-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
|
||||
; GFX6-NEXT: {{ $}}
|
||||
; GFX6-NEXT: bb.3:
|
||||
; GFX6-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; GFX6-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; GFX6-NEXT: {{ $}}
|
||||
; GFX6-NEXT: bb.4:
|
||||
; GFX6-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
|
||||
|
|
@ -2989,7 +2989,7 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_soffset_add_4096(<4 x i32> %
|
|||
; GFX7-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0
|
||||
; GFX7-NEXT: [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; GFX7-NEXT: [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; GFX7-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; GFX7-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; GFX7-NEXT: {{ $}}
|
||||
; GFX7-NEXT: bb.2:
|
||||
; GFX7-NEXT: successors: %bb.3, %bb.2
|
||||
|
|
@ -3010,7 +3010,7 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_soffset_add_4096(<4 x i32> %
|
|||
; GFX7-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
|
||||
; GFX7-NEXT: {{ $}}
|
||||
; GFX7-NEXT: bb.3:
|
||||
; GFX7-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; GFX7-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; GFX7-NEXT: {{ $}}
|
||||
; GFX7-NEXT: bb.4:
|
||||
; GFX7-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
|
||||
|
|
@ -3031,7 +3031,7 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_soffset_add_4096(<4 x i32> %
|
|||
; GFX8-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0
|
||||
; GFX8-NEXT: [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; GFX8-NEXT: [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; GFX8-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; GFX8-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; GFX8-NEXT: {{ $}}
|
||||
; GFX8-NEXT: bb.2:
|
||||
; GFX8-NEXT: successors: %bb.3, %bb.2
|
||||
|
|
@ -3052,7 +3052,7 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_soffset_add_4096(<4 x i32> %
|
|||
; GFX8-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
|
||||
; GFX8-NEXT: {{ $}}
|
||||
; GFX8-NEXT: bb.3:
|
||||
; GFX8-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; GFX8-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; GFX8-NEXT: {{ $}}
|
||||
; GFX8-NEXT: bb.4:
|
||||
; GFX8-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
|
||||
|
|
@ -3076,7 +3076,7 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_offset_4095(<4 x i32> %rsrc)
|
|||
; GFX6-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
|
||||
; GFX6-NEXT: [[COPY4:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; GFX6-NEXT: [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; GFX6-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; GFX6-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; GFX6-NEXT: {{ $}}
|
||||
; GFX6-NEXT: bb.2:
|
||||
; GFX6-NEXT: successors: %bb.3, %bb.2
|
||||
|
|
@ -3097,7 +3097,7 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_offset_4095(<4 x i32> %rsrc)
|
|||
; GFX6-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
|
||||
; GFX6-NEXT: {{ $}}
|
||||
; GFX6-NEXT: bb.3:
|
||||
; GFX6-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; GFX6-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; GFX6-NEXT: {{ $}}
|
||||
; GFX6-NEXT: bb.4:
|
||||
; GFX6-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFSET]]
|
||||
|
|
@ -3114,7 +3114,7 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_offset_4095(<4 x i32> %rsrc)
|
|||
; GFX7-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
|
||||
; GFX7-NEXT: [[COPY4:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; GFX7-NEXT: [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; GFX7-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; GFX7-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; GFX7-NEXT: {{ $}}
|
||||
; GFX7-NEXT: bb.2:
|
||||
; GFX7-NEXT: successors: %bb.3, %bb.2
|
||||
|
|
@ -3135,7 +3135,7 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_offset_4095(<4 x i32> %rsrc)
|
|||
; GFX7-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
|
||||
; GFX7-NEXT: {{ $}}
|
||||
; GFX7-NEXT: bb.3:
|
||||
; GFX7-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; GFX7-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; GFX7-NEXT: {{ $}}
|
||||
; GFX7-NEXT: bb.4:
|
||||
; GFX7-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFSET]]
|
||||
|
|
@ -3152,7 +3152,7 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_offset_4095(<4 x i32> %rsrc)
|
|||
; GFX8-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
|
||||
; GFX8-NEXT: [[COPY4:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; GFX8-NEXT: [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; GFX8-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; GFX8-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; GFX8-NEXT: {{ $}}
|
||||
; GFX8-NEXT: bb.2:
|
||||
; GFX8-NEXT: successors: %bb.3, %bb.2
|
||||
|
|
@ -3173,7 +3173,7 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_offset_4095(<4 x i32> %rsrc)
|
|||
; GFX8-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
|
||||
; GFX8-NEXT: {{ $}}
|
||||
; GFX8-NEXT: bb.3:
|
||||
; GFX8-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; GFX8-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; GFX8-NEXT: {{ $}}
|
||||
; GFX8-NEXT: bb.4:
|
||||
; GFX8-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFSET]]
|
||||
|
|
@ -3198,7 +3198,7 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_offset_4096(<4 x i32> %rsrc)
|
|||
; GFX6-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0
|
||||
; GFX6-NEXT: [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; GFX6-NEXT: [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; GFX6-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; GFX6-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; GFX6-NEXT: {{ $}}
|
||||
; GFX6-NEXT: bb.2:
|
||||
; GFX6-NEXT: successors: %bb.3, %bb.2
|
||||
|
|
@ -3219,7 +3219,7 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_offset_4096(<4 x i32> %rsrc)
|
|||
; GFX6-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
|
||||
; GFX6-NEXT: {{ $}}
|
||||
; GFX6-NEXT: bb.3:
|
||||
; GFX6-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; GFX6-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; GFX6-NEXT: {{ $}}
|
||||
; GFX6-NEXT: bb.4:
|
||||
; GFX6-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
|
||||
|
|
@ -3238,7 +3238,7 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_offset_4096(<4 x i32> %rsrc)
|
|||
; GFX7-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0
|
||||
; GFX7-NEXT: [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; GFX7-NEXT: [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; GFX7-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; GFX7-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; GFX7-NEXT: {{ $}}
|
||||
; GFX7-NEXT: bb.2:
|
||||
; GFX7-NEXT: successors: %bb.3, %bb.2
|
||||
|
|
@ -3259,7 +3259,7 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_offset_4096(<4 x i32> %rsrc)
|
|||
; GFX7-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
|
||||
; GFX7-NEXT: {{ $}}
|
||||
; GFX7-NEXT: bb.3:
|
||||
; GFX7-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; GFX7-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; GFX7-NEXT: {{ $}}
|
||||
; GFX7-NEXT: bb.4:
|
||||
; GFX7-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
|
||||
|
|
@ -3276,7 +3276,7 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_offset_4096(<4 x i32> %rsrc)
|
|||
; GFX8-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1
|
||||
; GFX8-NEXT: [[COPY4:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; GFX8-NEXT: [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; GFX8-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; GFX8-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; GFX8-NEXT: {{ $}}
|
||||
; GFX8-NEXT: bb.2:
|
||||
; GFX8-NEXT: successors: %bb.3, %bb.2
|
||||
|
|
@ -3297,7 +3297,7 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_offset_4096(<4 x i32> %rsrc)
|
|||
; GFX8-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
|
||||
; GFX8-NEXT: {{ $}}
|
||||
; GFX8-NEXT: bb.3:
|
||||
; GFX8-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; GFX8-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; GFX8-NEXT: {{ $}}
|
||||
; GFX8-NEXT: bb.4:
|
||||
; GFX8-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFSET]]
|
||||
|
|
@ -3321,7 +3321,7 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4064(<4 x i32> %
|
|||
; GFX6-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2
|
||||
; GFX6-NEXT: [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; GFX6-NEXT: [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; GFX6-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; GFX6-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; GFX6-NEXT: {{ $}}
|
||||
; GFX6-NEXT: bb.2:
|
||||
; GFX6-NEXT: successors: %bb.3, %bb.2
|
||||
|
|
@ -3343,7 +3343,7 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4064(<4 x i32> %
|
|||
; GFX6-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
|
||||
; GFX6-NEXT: {{ $}}
|
||||
; GFX6-NEXT: bb.3:
|
||||
; GFX6-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; GFX6-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; GFX6-NEXT: {{ $}}
|
||||
; GFX6-NEXT: bb.4:
|
||||
; GFX6-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFSET]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFSET1]], %subreg.sub4_sub5_sub6_sub7
|
||||
|
|
@ -3376,7 +3376,7 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4064(<4 x i32> %
|
|||
; GFX7-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2
|
||||
; GFX7-NEXT: [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; GFX7-NEXT: [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; GFX7-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; GFX7-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; GFX7-NEXT: {{ $}}
|
||||
; GFX7-NEXT: bb.2:
|
||||
; GFX7-NEXT: successors: %bb.3, %bb.2
|
||||
|
|
@ -3398,7 +3398,7 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4064(<4 x i32> %
|
|||
; GFX7-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
|
||||
; GFX7-NEXT: {{ $}}
|
||||
; GFX7-NEXT: bb.3:
|
||||
; GFX7-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; GFX7-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; GFX7-NEXT: {{ $}}
|
||||
; GFX7-NEXT: bb.4:
|
||||
; GFX7-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFSET]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFSET1]], %subreg.sub4_sub5_sub6_sub7
|
||||
|
|
@ -3431,7 +3431,7 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4064(<4 x i32> %
|
|||
; GFX8-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2
|
||||
; GFX8-NEXT: [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; GFX8-NEXT: [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; GFX8-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; GFX8-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; GFX8-NEXT: {{ $}}
|
||||
; GFX8-NEXT: bb.2:
|
||||
; GFX8-NEXT: successors: %bb.3, %bb.2
|
||||
|
|
@ -3453,7 +3453,7 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4064(<4 x i32> %
|
|||
; GFX8-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
|
||||
; GFX8-NEXT: {{ $}}
|
||||
; GFX8-NEXT: bb.3:
|
||||
; GFX8-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; GFX8-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; GFX8-NEXT: {{ $}}
|
||||
; GFX8-NEXT: bb.4:
|
||||
; GFX8-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFSET]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFSET1]], %subreg.sub4_sub5_sub6_sub7
|
||||
|
|
@ -3498,7 +3498,7 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4068(<4 x i32> %
|
|||
; GFX6-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0
|
||||
; GFX6-NEXT: [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; GFX6-NEXT: [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; GFX6-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; GFX6-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; GFX6-NEXT: {{ $}}
|
||||
; GFX6-NEXT: bb.2:
|
||||
; GFX6-NEXT: successors: %bb.3, %bb.2
|
||||
|
|
@ -3520,7 +3520,7 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4068(<4 x i32> %
|
|||
; GFX6-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
|
||||
; GFX6-NEXT: {{ $}}
|
||||
; GFX6-NEXT: bb.3:
|
||||
; GFX6-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; GFX6-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; GFX6-NEXT: {{ $}}
|
||||
; GFX6-NEXT: bb.4:
|
||||
; GFX6-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7
|
||||
|
|
@ -3557,7 +3557,7 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4068(<4 x i32> %
|
|||
; GFX7-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0
|
||||
; GFX7-NEXT: [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; GFX7-NEXT: [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; GFX7-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; GFX7-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; GFX7-NEXT: {{ $}}
|
||||
; GFX7-NEXT: bb.2:
|
||||
; GFX7-NEXT: successors: %bb.3, %bb.2
|
||||
|
|
@ -3579,7 +3579,7 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4068(<4 x i32> %
|
|||
; GFX7-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
|
||||
; GFX7-NEXT: {{ $}}
|
||||
; GFX7-NEXT: bb.3:
|
||||
; GFX7-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; GFX7-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; GFX7-NEXT: {{ $}}
|
||||
; GFX7-NEXT: bb.4:
|
||||
; GFX7-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7
|
||||
|
|
@ -3616,7 +3616,7 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4068(<4 x i32> %
|
|||
; GFX8-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0
|
||||
; GFX8-NEXT: [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; GFX8-NEXT: [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; GFX8-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; GFX8-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; GFX8-NEXT: {{ $}}
|
||||
; GFX8-NEXT: bb.2:
|
||||
; GFX8-NEXT: successors: %bb.3, %bb.2
|
||||
|
|
@ -3638,7 +3638,7 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4068(<4 x i32> %
|
|||
; GFX8-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
|
||||
; GFX8-NEXT: {{ $}}
|
||||
; GFX8-NEXT: bb.3:
|
||||
; GFX8-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; GFX8-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; GFX8-NEXT: {{ $}}
|
||||
; GFX8-NEXT: bb.4:
|
||||
; GFX8-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7
|
||||
|
|
@ -3681,7 +3681,7 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4096(<4 x i32> %
|
|||
; GFX6-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0
|
||||
; GFX6-NEXT: [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; GFX6-NEXT: [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; GFX6-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; GFX6-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; GFX6-NEXT: {{ $}}
|
||||
; GFX6-NEXT: bb.2:
|
||||
; GFX6-NEXT: successors: %bb.3, %bb.2
|
||||
|
|
@ -3703,7 +3703,7 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4096(<4 x i32> %
|
|||
; GFX6-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
|
||||
; GFX6-NEXT: {{ $}}
|
||||
; GFX6-NEXT: bb.3:
|
||||
; GFX6-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; GFX6-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; GFX6-NEXT: {{ $}}
|
||||
; GFX6-NEXT: bb.4:
|
||||
; GFX6-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7
|
||||
|
|
@ -3740,7 +3740,7 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4096(<4 x i32> %
|
|||
; GFX7-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0
|
||||
; GFX7-NEXT: [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; GFX7-NEXT: [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; GFX7-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; GFX7-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; GFX7-NEXT: {{ $}}
|
||||
; GFX7-NEXT: bb.2:
|
||||
; GFX7-NEXT: successors: %bb.3, %bb.2
|
||||
|
|
@ -3762,7 +3762,7 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4096(<4 x i32> %
|
|||
; GFX7-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
|
||||
; GFX7-NEXT: {{ $}}
|
||||
; GFX7-NEXT: bb.3:
|
||||
; GFX7-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; GFX7-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; GFX7-NEXT: {{ $}}
|
||||
; GFX7-NEXT: bb.4:
|
||||
; GFX7-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7
|
||||
|
|
@ -3799,7 +3799,7 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4096(<4 x i32> %
|
|||
; GFX8-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0
|
||||
; GFX8-NEXT: [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; GFX8-NEXT: [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; GFX8-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; GFX8-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; GFX8-NEXT: {{ $}}
|
||||
; GFX8-NEXT: bb.2:
|
||||
; GFX8-NEXT: successors: %bb.3, %bb.2
|
||||
|
|
@ -3821,7 +3821,7 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4096(<4 x i32> %
|
|||
; GFX8-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
|
||||
; GFX8-NEXT: {{ $}}
|
||||
; GFX8-NEXT: bb.3:
|
||||
; GFX8-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; GFX8-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; GFX8-NEXT: {{ $}}
|
||||
; GFX8-NEXT: bb.4:
|
||||
; GFX8-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7
|
||||
|
|
@ -3861,7 +3861,7 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_5000
|
|||
; GFX6-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 5000
|
||||
; GFX6-NEXT: [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; GFX6-NEXT: [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; GFX6-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; GFX6-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; GFX6-NEXT: {{ $}}
|
||||
; GFX6-NEXT: bb.2:
|
||||
; GFX6-NEXT: successors: %bb.3, %bb.2
|
||||
|
|
@ -3883,7 +3883,7 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_5000
|
|||
; GFX6-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
|
||||
; GFX6-NEXT: {{ $}}
|
||||
; GFX6-NEXT: bb.3:
|
||||
; GFX6-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; GFX6-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; GFX6-NEXT: {{ $}}
|
||||
; GFX6-NEXT: bb.4:
|
||||
; GFX6-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7
|
||||
|
|
@ -3917,7 +3917,7 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_5000
|
|||
; GFX7-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 5000
|
||||
; GFX7-NEXT: [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; GFX7-NEXT: [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; GFX7-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; GFX7-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; GFX7-NEXT: {{ $}}
|
||||
; GFX7-NEXT: bb.2:
|
||||
; GFX7-NEXT: successors: %bb.3, %bb.2
|
||||
|
|
@ -3939,7 +3939,7 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_5000
|
|||
; GFX7-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
|
||||
; GFX7-NEXT: {{ $}}
|
||||
; GFX7-NEXT: bb.3:
|
||||
; GFX7-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; GFX7-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; GFX7-NEXT: {{ $}}
|
||||
; GFX7-NEXT: bb.4:
|
||||
; GFX7-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7
|
||||
|
|
@ -3973,7 +3973,7 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_5000
|
|||
; GFX8-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4064
|
||||
; GFX8-NEXT: [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; GFX8-NEXT: [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; GFX8-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; GFX8-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; GFX8-NEXT: {{ $}}
|
||||
; GFX8-NEXT: bb.2:
|
||||
; GFX8-NEXT: successors: %bb.3, %bb.2
|
||||
|
|
@ -3995,7 +3995,7 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_5000
|
|||
; GFX8-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
|
||||
; GFX8-NEXT: {{ $}}
|
||||
; GFX8-NEXT: bb.3:
|
||||
; GFX8-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; GFX8-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; GFX8-NEXT: {{ $}}
|
||||
; GFX8-NEXT: bb.4:
|
||||
; GFX8-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7
|
||||
|
|
@ -4035,7 +4035,7 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4076
|
|||
; GFX6-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4076
|
||||
; GFX6-NEXT: [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; GFX6-NEXT: [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; GFX6-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; GFX6-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; GFX6-NEXT: {{ $}}
|
||||
; GFX6-NEXT: bb.2:
|
||||
; GFX6-NEXT: successors: %bb.3, %bb.2
|
||||
|
|
@ -4057,7 +4057,7 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4076
|
|||
; GFX6-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
|
||||
; GFX6-NEXT: {{ $}}
|
||||
; GFX6-NEXT: bb.3:
|
||||
; GFX6-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; GFX6-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; GFX6-NEXT: {{ $}}
|
||||
; GFX6-NEXT: bb.4:
|
||||
; GFX6-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7
|
||||
|
|
@ -4091,7 +4091,7 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4076
|
|||
; GFX7-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4076
|
||||
; GFX7-NEXT: [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; GFX7-NEXT: [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; GFX7-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; GFX7-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; GFX7-NEXT: {{ $}}
|
||||
; GFX7-NEXT: bb.2:
|
||||
; GFX7-NEXT: successors: %bb.3, %bb.2
|
||||
|
|
@ -4113,7 +4113,7 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4076
|
|||
; GFX7-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
|
||||
; GFX7-NEXT: {{ $}}
|
||||
; GFX7-NEXT: bb.3:
|
||||
; GFX7-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; GFX7-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; GFX7-NEXT: {{ $}}
|
||||
; GFX7-NEXT: bb.4:
|
||||
; GFX7-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7
|
||||
|
|
@ -4147,7 +4147,7 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4076
|
|||
; GFX8-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 12
|
||||
; GFX8-NEXT: [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; GFX8-NEXT: [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; GFX8-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; GFX8-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; GFX8-NEXT: {{ $}}
|
||||
; GFX8-NEXT: bb.2:
|
||||
; GFX8-NEXT: successors: %bb.3, %bb.2
|
||||
|
|
@ -4169,7 +4169,7 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4076
|
|||
; GFX8-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
|
||||
; GFX8-NEXT: {{ $}}
|
||||
; GFX8-NEXT: bb.3:
|
||||
; GFX8-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; GFX8-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; GFX8-NEXT: {{ $}}
|
||||
; GFX8-NEXT: bb.4:
|
||||
; GFX8-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7
|
||||
|
|
@ -4209,7 +4209,7 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4080
|
|||
; GFX6-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4080
|
||||
; GFX6-NEXT: [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; GFX6-NEXT: [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; GFX6-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; GFX6-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; GFX6-NEXT: {{ $}}
|
||||
; GFX6-NEXT: bb.2:
|
||||
; GFX6-NEXT: successors: %bb.3, %bb.2
|
||||
|
|
@ -4231,7 +4231,7 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4080
|
|||
; GFX6-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
|
||||
; GFX6-NEXT: {{ $}}
|
||||
; GFX6-NEXT: bb.3:
|
||||
; GFX6-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; GFX6-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; GFX6-NEXT: {{ $}}
|
||||
; GFX6-NEXT: bb.4:
|
||||
; GFX6-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7
|
||||
|
|
@ -4265,7 +4265,7 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4080
|
|||
; GFX7-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4080
|
||||
; GFX7-NEXT: [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; GFX7-NEXT: [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; GFX7-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; GFX7-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; GFX7-NEXT: {{ $}}
|
||||
; GFX7-NEXT: bb.2:
|
||||
; GFX7-NEXT: successors: %bb.3, %bb.2
|
||||
|
|
@ -4287,7 +4287,7 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4080
|
|||
; GFX7-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
|
||||
; GFX7-NEXT: {{ $}}
|
||||
; GFX7-NEXT: bb.3:
|
||||
; GFX7-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; GFX7-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; GFX7-NEXT: {{ $}}
|
||||
; GFX7-NEXT: bb.4:
|
||||
; GFX7-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7
|
||||
|
|
@ -4321,7 +4321,7 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4080
|
|||
; GFX8-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16
|
||||
; GFX8-NEXT: [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; GFX8-NEXT: [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; GFX8-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; GFX8-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; GFX8-NEXT: {{ $}}
|
||||
; GFX8-NEXT: bb.2:
|
||||
; GFX8-NEXT: successors: %bb.3, %bb.2
|
||||
|
|
@ -4343,7 +4343,7 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4080
|
|||
; GFX8-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
|
||||
; GFX8-NEXT: {{ $}}
|
||||
; GFX8-NEXT: bb.3:
|
||||
; GFX8-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; GFX8-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; GFX8-NEXT: {{ $}}
|
||||
; GFX8-NEXT: bb.4:
|
||||
; GFX8-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFEN]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFEN1]], %subreg.sub4_sub5_sub6_sub7
|
||||
|
|
@ -4382,7 +4382,7 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_offset_4
|
|||
; GFX6-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
|
||||
; GFX6-NEXT: [[COPY4:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; GFX6-NEXT: [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; GFX6-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; GFX6-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; GFX6-NEXT: {{ $}}
|
||||
; GFX6-NEXT: bb.2:
|
||||
; GFX6-NEXT: successors: %bb.3, %bb.2
|
||||
|
|
@ -4404,7 +4404,7 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_offset_4
|
|||
; GFX6-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
|
||||
; GFX6-NEXT: {{ $}}
|
||||
; GFX6-NEXT: bb.3:
|
||||
; GFX6-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; GFX6-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; GFX6-NEXT: {{ $}}
|
||||
; GFX6-NEXT: bb.4:
|
||||
; GFX6-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFSET]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFSET1]], %subreg.sub4_sub5_sub6_sub7
|
||||
|
|
@ -4437,7 +4437,7 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_offset_4
|
|||
; GFX7-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
|
||||
; GFX7-NEXT: [[COPY4:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; GFX7-NEXT: [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; GFX7-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; GFX7-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; GFX7-NEXT: {{ $}}
|
||||
; GFX7-NEXT: bb.2:
|
||||
; GFX7-NEXT: successors: %bb.3, %bb.2
|
||||
|
|
@ -4459,7 +4459,7 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_offset_4
|
|||
; GFX7-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
|
||||
; GFX7-NEXT: {{ $}}
|
||||
; GFX7-NEXT: bb.3:
|
||||
; GFX7-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; GFX7-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; GFX7-NEXT: {{ $}}
|
||||
; GFX7-NEXT: bb.4:
|
||||
; GFX7-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFSET]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFSET1]], %subreg.sub4_sub5_sub6_sub7
|
||||
|
|
@ -4492,7 +4492,7 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_offset_4
|
|||
; GFX8-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
|
||||
; GFX8-NEXT: [[COPY4:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; GFX8-NEXT: [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; GFX8-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; GFX8-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; GFX8-NEXT: {{ $}}
|
||||
; GFX8-NEXT: bb.2:
|
||||
; GFX8-NEXT: successors: %bb.3, %bb.2
|
||||
|
|
@ -4514,7 +4514,7 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_offset_4
|
|||
; GFX8-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
|
||||
; GFX8-NEXT: {{ $}}
|
||||
; GFX8-NEXT: bb.3:
|
||||
; GFX8-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; GFX8-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; GFX8-NEXT: {{ $}}
|
||||
; GFX8-NEXT: bb.4:
|
||||
; GFX8-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:vreg_256 = REG_SEQUENCE [[BUFFER_LOAD_DWORDX4_OFFSET]], %subreg.sub0_sub1_sub2_sub3, [[BUFFER_LOAD_DWORDX4_OFFSET1]], %subreg.sub4_sub5_sub6_sub7
|
||||
|
|
|
|||
|
|
@ -120,7 +120,7 @@ define amdgpu_ps float @struct_buffer_atomic_add_i32__sgpr_val__vgpr_rsrc__sgpr_
|
|||
; CHECK-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
|
||||
; CHECK-NEXT: [[COPY11:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; CHECK-NEXT: [[COPY12:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; CHECK-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.2:
|
||||
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -147,7 +147,7 @@ define amdgpu_ps float @struct_buffer_atomic_add_i32__sgpr_val__vgpr_rsrc__sgpr_
|
|||
; CHECK-NEXT: bb.3:
|
||||
; CHECK-NEXT: successors: %bb.4(0x80000000)
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.4:
|
||||
; CHECK-NEXT: $vgpr0 = COPY [[BUFFER_ATOMIC_ADD_BOTHEN_RTN]]
|
||||
|
|
@ -178,7 +178,7 @@ define amdgpu_ps void @struct_buffer_atomic_add_i32_noret__sgpr_val__vgpr_rsrc__
|
|||
; CHECK-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
|
||||
; CHECK-NEXT: [[COPY11:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; CHECK-NEXT: [[COPY12:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; CHECK-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.2:
|
||||
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -205,7 +205,7 @@ define amdgpu_ps void @struct_buffer_atomic_add_i32_noret__sgpr_val__vgpr_rsrc__
|
|||
; CHECK-NEXT: bb.3:
|
||||
; CHECK-NEXT: successors: %bb.4(0x80000000)
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.4:
|
||||
; CHECK-NEXT: S_ENDPGM 0
|
||||
|
|
|
|||
|
|
@ -77,7 +77,7 @@ define amdgpu_ps float @struct_buffer_atomic_cmpswap_i32__sgpr_val__sgpr_cmp__vg
|
|||
; CHECK-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[COPY7]]
|
||||
; CHECK-NEXT: [[COPY13:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; CHECK-NEXT: [[COPY14:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; CHECK-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.2:
|
||||
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -106,7 +106,7 @@ define amdgpu_ps float @struct_buffer_atomic_cmpswap_i32__sgpr_val__sgpr_cmp__vg
|
|||
; CHECK-NEXT: bb.3:
|
||||
; CHECK-NEXT: successors: %bb.4(0x80000000)
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.4:
|
||||
; CHECK-NEXT: $vgpr0 = COPY [[COPY15]]
|
||||
|
|
@ -139,7 +139,7 @@ define amdgpu_ps void @struct_buffer_atomic_cmpswap_i32_noret__sgpr_val__sgpr_cm
|
|||
; CHECK-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[COPY7]]
|
||||
; CHECK-NEXT: [[COPY13:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; CHECK-NEXT: [[COPY14:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; CHECK-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.2:
|
||||
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -168,7 +168,7 @@ define amdgpu_ps void @struct_buffer_atomic_cmpswap_i32_noret__sgpr_val__sgpr_cm
|
|||
; CHECK-NEXT: bb.3:
|
||||
; CHECK-NEXT: successors: %bb.4(0x80000000)
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.4:
|
||||
; CHECK-NEXT: S_ENDPGM 0
|
||||
|
|
|
|||
|
|
@ -166,7 +166,7 @@ define amdgpu_ps void @struct_buffer_atomic_add_f32_noret__sgpr_val__vgpr_rsrc__
|
|||
; GFX908-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
|
||||
; GFX908-NEXT: [[COPY11:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; GFX908-NEXT: [[COPY12:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; GFX908-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; GFX908-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; GFX908-NEXT: {{ $}}
|
||||
; GFX908-NEXT: bb.2:
|
||||
; GFX908-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -193,7 +193,7 @@ define amdgpu_ps void @struct_buffer_atomic_add_f32_noret__sgpr_val__vgpr_rsrc__
|
|||
; GFX908-NEXT: bb.3:
|
||||
; GFX908-NEXT: successors: %bb.4(0x80000000)
|
||||
; GFX908-NEXT: {{ $}}
|
||||
; GFX908-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; GFX908-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; GFX908-NEXT: {{ $}}
|
||||
; GFX908-NEXT: bb.4:
|
||||
; GFX908-NEXT: S_ENDPGM 0
|
||||
|
|
@ -216,7 +216,7 @@ define amdgpu_ps void @struct_buffer_atomic_add_f32_noret__sgpr_val__vgpr_rsrc__
|
|||
; GFX90A-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
|
||||
; GFX90A-NEXT: [[COPY11:%[0-9]+]]:vreg_64_align2 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; GFX90A-NEXT: [[COPY12:%[0-9]+]]:vreg_64_align2 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; GFX90A-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; GFX90A-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; GFX90A-NEXT: {{ $}}
|
||||
; GFX90A-NEXT: bb.2:
|
||||
; GFX90A-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -243,7 +243,7 @@ define amdgpu_ps void @struct_buffer_atomic_add_f32_noret__sgpr_val__vgpr_rsrc__
|
|||
; GFX90A-NEXT: bb.3:
|
||||
; GFX90A-NEXT: successors: %bb.4(0x80000000)
|
||||
; GFX90A-NEXT: {{ $}}
|
||||
; GFX90A-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; GFX90A-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; GFX90A-NEXT: {{ $}}
|
||||
; GFX90A-NEXT: bb.4:
|
||||
; GFX90A-NEXT: S_ENDPGM 0
|
||||
|
|
@ -270,7 +270,7 @@ define amdgpu_ps void @struct_buffer_atomic_add_f32_noret__sgpr_val__vgpr_rsrc__
|
|||
; GFX908-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
|
||||
; GFX908-NEXT: [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; GFX908-NEXT: [[COPY10:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; GFX908-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; GFX908-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; GFX908-NEXT: {{ $}}
|
||||
; GFX908-NEXT: bb.2:
|
||||
; GFX908-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -296,7 +296,7 @@ define amdgpu_ps void @struct_buffer_atomic_add_f32_noret__sgpr_val__vgpr_rsrc__
|
|||
; GFX908-NEXT: bb.3:
|
||||
; GFX908-NEXT: successors: %bb.4(0x80000000)
|
||||
; GFX908-NEXT: {{ $}}
|
||||
; GFX908-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; GFX908-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; GFX908-NEXT: {{ $}}
|
||||
; GFX908-NEXT: bb.4:
|
||||
; GFX908-NEXT: S_ENDPGM 0
|
||||
|
|
@ -317,7 +317,7 @@ define amdgpu_ps void @struct_buffer_atomic_add_f32_noret__sgpr_val__vgpr_rsrc__
|
|||
; GFX90A-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
|
||||
; GFX90A-NEXT: [[COPY9:%[0-9]+]]:vreg_64_align2 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; GFX90A-NEXT: [[COPY10:%[0-9]+]]:vreg_64_align2 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; GFX90A-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; GFX90A-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; GFX90A-NEXT: {{ $}}
|
||||
; GFX90A-NEXT: bb.2:
|
||||
; GFX90A-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -343,7 +343,7 @@ define amdgpu_ps void @struct_buffer_atomic_add_f32_noret__sgpr_val__vgpr_rsrc__
|
|||
; GFX90A-NEXT: bb.3:
|
||||
; GFX90A-NEXT: successors: %bb.4(0x80000000)
|
||||
; GFX90A-NEXT: {{ $}}
|
||||
; GFX90A-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; GFX90A-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; GFX90A-NEXT: {{ $}}
|
||||
; GFX90A-NEXT: bb.4:
|
||||
; GFX90A-NEXT: S_ENDPGM 0
|
||||
|
|
|
|||
|
|
@ -173,7 +173,7 @@ define amdgpu_ps <4 x half> @struct_buffer_load_format_v4f16__vpr_rsrc__sgpr_vin
|
|||
; UNPACKED-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
|
||||
; UNPACKED-NEXT: [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; UNPACKED-NEXT: [[COPY10:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; UNPACKED-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; UNPACKED-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; UNPACKED-NEXT: {{ $}}
|
||||
; UNPACKED-NEXT: bb.2:
|
||||
; UNPACKED-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -200,7 +200,7 @@ define amdgpu_ps <4 x half> @struct_buffer_load_format_v4f16__vpr_rsrc__sgpr_vin
|
|||
; UNPACKED-NEXT: bb.3:
|
||||
; UNPACKED-NEXT: successors: %bb.4(0x80000000)
|
||||
; UNPACKED-NEXT: {{ $}}
|
||||
; UNPACKED-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; UNPACKED-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; UNPACKED-NEXT: {{ $}}
|
||||
; UNPACKED-NEXT: bb.4:
|
||||
; UNPACKED-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_BOTHEN]].sub0
|
||||
|
|
@ -243,7 +243,7 @@ define amdgpu_ps <4 x half> @struct_buffer_load_format_v4f16__vpr_rsrc__sgpr_vin
|
|||
; PACKED-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
|
||||
; PACKED-NEXT: [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; PACKED-NEXT: [[COPY10:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; PACKED-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; PACKED-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; PACKED-NEXT: {{ $}}
|
||||
; PACKED-NEXT: bb.2:
|
||||
; PACKED-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -270,7 +270,7 @@ define amdgpu_ps <4 x half> @struct_buffer_load_format_v4f16__vpr_rsrc__sgpr_vin
|
|||
; PACKED-NEXT: bb.3:
|
||||
; PACKED-NEXT: successors: %bb.4(0x80000000)
|
||||
; PACKED-NEXT: {{ $}}
|
||||
; PACKED-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; PACKED-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; PACKED-NEXT: {{ $}}
|
||||
; PACKED-NEXT: bb.4:
|
||||
; PACKED-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN]].sub0
|
||||
|
|
|
|||
|
|
@ -120,7 +120,7 @@ define amdgpu_ps <4 x float> @struct_buffer_load_format_v4f32__vpr_rsrc__sgpr_vi
|
|||
; CHECK-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
|
||||
; CHECK-NEXT: [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; CHECK-NEXT: [[COPY10:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; CHECK-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.2:
|
||||
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -147,7 +147,7 @@ define amdgpu_ps <4 x float> @struct_buffer_load_format_v4f32__vpr_rsrc__sgpr_vi
|
|||
; CHECK-NEXT: bb.3:
|
||||
; CHECK-NEXT: successors: %bb.4(0x80000000)
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.4:
|
||||
; CHECK-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZW_BOTHEN]].sub0
|
||||
|
|
|
|||
|
|
@ -191,7 +191,7 @@ define amdgpu_ps float @struct_buffer_load_f32__vgpr_rsrc__sgpr_vindex__sgpr_vof
|
|||
; CHECK-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
|
||||
; CHECK-NEXT: [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; CHECK-NEXT: [[COPY10:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; CHECK-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.2:
|
||||
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -218,7 +218,7 @@ define amdgpu_ps float @struct_buffer_load_f32__vgpr_rsrc__sgpr_vindex__sgpr_vof
|
|||
; CHECK-NEXT: bb.3:
|
||||
; CHECK-NEXT: successors: %bb.4(0x80000000)
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.4:
|
||||
; CHECK-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_BOTHEN]]
|
||||
|
|
|
|||
|
|
@ -152,7 +152,7 @@ define amdgpu_ps void @struct_buffer_store_format_f16__sgpr_val__vgpr_rsrc__sgpr
|
|||
; UNPACKED-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
|
||||
; UNPACKED-NEXT: [[COPY11:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; UNPACKED-NEXT: [[COPY12:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; UNPACKED-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; UNPACKED-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; UNPACKED-NEXT: {{ $}}
|
||||
; UNPACKED-NEXT: bb.2:
|
||||
; UNPACKED-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -179,7 +179,7 @@ define amdgpu_ps void @struct_buffer_store_format_f16__sgpr_val__vgpr_rsrc__sgpr
|
|||
; UNPACKED-NEXT: bb.3:
|
||||
; UNPACKED-NEXT: successors: %bb.4(0x80000000)
|
||||
; UNPACKED-NEXT: {{ $}}
|
||||
; UNPACKED-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; UNPACKED-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; UNPACKED-NEXT: {{ $}}
|
||||
; UNPACKED-NEXT: bb.4:
|
||||
; UNPACKED-NEXT: S_ENDPGM 0
|
||||
|
|
@ -202,7 +202,7 @@ define amdgpu_ps void @struct_buffer_store_format_f16__sgpr_val__vgpr_rsrc__sgpr
|
|||
; PACKED-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
|
||||
; PACKED-NEXT: [[COPY11:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; PACKED-NEXT: [[COPY12:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; PACKED-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; PACKED-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; PACKED-NEXT: {{ $}}
|
||||
; PACKED-NEXT: bb.2:
|
||||
; PACKED-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -229,7 +229,7 @@ define amdgpu_ps void @struct_buffer_store_format_f16__sgpr_val__vgpr_rsrc__sgpr
|
|||
; PACKED-NEXT: bb.3:
|
||||
; PACKED-NEXT: successors: %bb.4(0x80000000)
|
||||
; PACKED-NEXT: {{ $}}
|
||||
; PACKED-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; PACKED-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; PACKED-NEXT: {{ $}}
|
||||
; PACKED-NEXT: bb.4:
|
||||
; PACKED-NEXT: S_ENDPGM 0
|
||||
|
|
|
|||
|
|
@ -114,7 +114,7 @@ define amdgpu_ps void @struct_buffer_store_format_f32__sgpr_val__vgpr_rsrc__sgpr
|
|||
; CHECK-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
|
||||
; CHECK-NEXT: [[COPY11:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; CHECK-NEXT: [[COPY12:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; CHECK-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.2:
|
||||
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -141,7 +141,7 @@ define amdgpu_ps void @struct_buffer_store_format_f32__sgpr_val__vgpr_rsrc__sgpr
|
|||
; CHECK-NEXT: bb.3:
|
||||
; CHECK-NEXT: successors: %bb.4(0x80000000)
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.4:
|
||||
; CHECK-NEXT: S_ENDPGM 0
|
||||
|
|
|
|||
|
|
@ -120,7 +120,7 @@ define amdgpu_ps void @struct_buffer_store_v4f32_vgpr_rsrc__sgpr_val__sgpr_vinde
|
|||
; CHECK-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[COPY9]]
|
||||
; CHECK-NEXT: [[COPY14:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE1]].sub0_sub1
|
||||
; CHECK-NEXT: [[COPY15:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE1]].sub2_sub3
|
||||
; CHECK-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.2:
|
||||
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -147,7 +147,7 @@ define amdgpu_ps void @struct_buffer_store_v4f32_vgpr_rsrc__sgpr_val__sgpr_vinde
|
|||
; CHECK-NEXT: bb.3:
|
||||
; CHECK-NEXT: successors: %bb.4(0x80000000)
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.4:
|
||||
; CHECK-NEXT: S_ENDPGM 0
|
||||
|
|
|
|||
|
|
@ -212,7 +212,7 @@ define amdgpu_ps <4 x half> @struct_tbuffer_load_v4f16__vgpr_rsrc__sgpr_vindex__
|
|||
; PACKED-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
|
||||
; PACKED-NEXT: [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; PACKED-NEXT: [[COPY10:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; PACKED-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; PACKED-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; PACKED-NEXT: {{ $}}
|
||||
; PACKED-NEXT: bb.2:
|
||||
; PACKED-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -239,7 +239,7 @@ define amdgpu_ps <4 x half> @struct_tbuffer_load_v4f16__vgpr_rsrc__sgpr_vindex__
|
|||
; PACKED-NEXT: bb.3:
|
||||
; PACKED-NEXT: successors: %bb.4(0x80000000)
|
||||
; PACKED-NEXT: {{ $}}
|
||||
; PACKED-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; PACKED-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; PACKED-NEXT: {{ $}}
|
||||
; PACKED-NEXT: bb.4:
|
||||
; PACKED-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN]].sub0
|
||||
|
|
@ -264,7 +264,7 @@ define amdgpu_ps <4 x half> @struct_tbuffer_load_v4f16__vgpr_rsrc__sgpr_vindex__
|
|||
; UNPACKED-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
|
||||
; UNPACKED-NEXT: [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; UNPACKED-NEXT: [[COPY10:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; UNPACKED-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; UNPACKED-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; UNPACKED-NEXT: {{ $}}
|
||||
; UNPACKED-NEXT: bb.2:
|
||||
; UNPACKED-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -291,7 +291,7 @@ define amdgpu_ps <4 x half> @struct_tbuffer_load_v4f16__vgpr_rsrc__sgpr_vindex__
|
|||
; UNPACKED-NEXT: bb.3:
|
||||
; UNPACKED-NEXT: successors: %bb.4(0x80000000)
|
||||
; UNPACKED-NEXT: {{ $}}
|
||||
; UNPACKED-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; UNPACKED-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; UNPACKED-NEXT: {{ $}}
|
||||
; UNPACKED-NEXT: bb.4:
|
||||
; UNPACKED-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_BOTHEN]].sub0
|
||||
|
|
|
|||
|
|
@ -141,7 +141,7 @@ define amdgpu_ps <4 x float> @struct_tbuffer_load_v4f32__vgpr_rsrc__sgpr_vindex_
|
|||
; CHECK-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
|
||||
; CHECK-NEXT: [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
|
||||
; CHECK-NEXT: [[COPY10:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
|
||||
; CHECK-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.2:
|
||||
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -168,7 +168,7 @@ define amdgpu_ps <4 x float> @struct_tbuffer_load_v4f32__vgpr_rsrc__sgpr_vindex_
|
|||
; CHECK-NEXT: bb.3:
|
||||
; CHECK-NEXT: successors: %bb.4(0x80000000)
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.4:
|
||||
; CHECK-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZW_BOTHEN]].sub0
|
||||
|
|
|
|||
|
|
@ -63,7 +63,7 @@ body: |
|
|||
; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
|
||||
; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
|
||||
; CHECK-NEXT: [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
|
||||
; CHECK-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: .1:
|
||||
; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
|
||||
|
|
@ -87,7 +87,7 @@ body: |
|
|||
; CHECK-NEXT: .2:
|
||||
; CHECK-NEXT: successors: %bb.3(0x80000000)
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: .3:
|
||||
%0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
|
||||
|
|
@ -114,7 +114,7 @@ body: |
|
|||
; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
|
||||
; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
|
||||
; CHECK-NEXT: [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
|
||||
; CHECK-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: .1:
|
||||
; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
|
||||
|
|
@ -138,7 +138,7 @@ body: |
|
|||
; CHECK-NEXT: .2:
|
||||
; CHECK-NEXT: successors: %bb.3(0x80000000)
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: .3:
|
||||
%0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
|
||||
|
|
|
|||
|
|
@ -114,7 +114,7 @@ define amdgpu_ps void @load_1d_vgpr_vaddr__vgpr_srsrc(<8 x i32> %rsrc, i32 %s) {
|
|||
; FAST-NEXT: [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF
|
||||
; FAST-NEXT: [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
|
||||
; FAST-NEXT: [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64), [[UV2:%[0-9]+]]:vreg_64(s64), [[UV3:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<8 x s32>)
|
||||
; FAST-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; FAST-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; FAST-NEXT: {{ $}}
|
||||
; FAST-NEXT: bb.2:
|
||||
; FAST-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -148,7 +148,7 @@ define amdgpu_ps void @load_1d_vgpr_vaddr__vgpr_srsrc(<8 x i32> %rsrc, i32 %s) {
|
|||
; FAST-NEXT: bb.3:
|
||||
; FAST-NEXT: successors: %bb.4(0x80000000)
|
||||
; FAST-NEXT: {{ $}}
|
||||
; FAST-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; FAST-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; FAST-NEXT: {{ $}}
|
||||
; FAST-NEXT: bb.4:
|
||||
; FAST-NEXT: [[COPY9:%[0-9]+]]:vgpr(p1) = COPY [[DEF]](p1)
|
||||
|
|
@ -172,7 +172,7 @@ define amdgpu_ps void @load_1d_vgpr_vaddr__vgpr_srsrc(<8 x i32> %rsrc, i32 %s) {
|
|||
; GREEDY-NEXT: [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF
|
||||
; GREEDY-NEXT: [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
|
||||
; GREEDY-NEXT: [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64), [[UV2:%[0-9]+]]:vreg_64(s64), [[UV3:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<8 x s32>)
|
||||
; GREEDY-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; GREEDY-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; GREEDY-NEXT: {{ $}}
|
||||
; GREEDY-NEXT: bb.2:
|
||||
; GREEDY-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -206,7 +206,7 @@ define amdgpu_ps void @load_1d_vgpr_vaddr__vgpr_srsrc(<8 x i32> %rsrc, i32 %s) {
|
|||
; GREEDY-NEXT: bb.3:
|
||||
; GREEDY-NEXT: successors: %bb.4(0x80000000)
|
||||
; GREEDY-NEXT: {{ $}}
|
||||
; GREEDY-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; GREEDY-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; GREEDY-NEXT: {{ $}}
|
||||
; GREEDY-NEXT: bb.4:
|
||||
; GREEDY-NEXT: [[COPY9:%[0-9]+]]:vgpr(p1) = COPY [[DEF]](p1)
|
||||
|
|
@ -238,7 +238,7 @@ define amdgpu_ps void @load_1d_sgpr_vaddr__vgpr_srsrc(<8 x i32> %rsrc, i32 inreg
|
|||
; FAST-NEXT: [[COPY9:%[0-9]+]]:vgpr(s32) = COPY [[COPY8]](s32)
|
||||
; FAST-NEXT: [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
|
||||
; FAST-NEXT: [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64), [[UV2:%[0-9]+]]:vreg_64(s64), [[UV3:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<8 x s32>)
|
||||
; FAST-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; FAST-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; FAST-NEXT: {{ $}}
|
||||
; FAST-NEXT: bb.2:
|
||||
; FAST-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -272,7 +272,7 @@ define amdgpu_ps void @load_1d_sgpr_vaddr__vgpr_srsrc(<8 x i32> %rsrc, i32 inreg
|
|||
; FAST-NEXT: bb.3:
|
||||
; FAST-NEXT: successors: %bb.4(0x80000000)
|
||||
; FAST-NEXT: {{ $}}
|
||||
; FAST-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; FAST-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; FAST-NEXT: {{ $}}
|
||||
; FAST-NEXT: bb.4:
|
||||
; FAST-NEXT: [[COPY10:%[0-9]+]]:vgpr(p1) = COPY [[DEF]](p1)
|
||||
|
|
@ -297,7 +297,7 @@ define amdgpu_ps void @load_1d_sgpr_vaddr__vgpr_srsrc(<8 x i32> %rsrc, i32 inreg
|
|||
; GREEDY-NEXT: [[COPY9:%[0-9]+]]:vgpr(s32) = COPY [[COPY8]](s32)
|
||||
; GREEDY-NEXT: [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
|
||||
; GREEDY-NEXT: [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64), [[UV2:%[0-9]+]]:vreg_64(s64), [[UV3:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<8 x s32>)
|
||||
; GREEDY-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; GREEDY-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; GREEDY-NEXT: {{ $}}
|
||||
; GREEDY-NEXT: bb.2:
|
||||
; GREEDY-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -331,7 +331,7 @@ define amdgpu_ps void @load_1d_sgpr_vaddr__vgpr_srsrc(<8 x i32> %rsrc, i32 inreg
|
|||
; GREEDY-NEXT: bb.3:
|
||||
; GREEDY-NEXT: successors: %bb.4(0x80000000)
|
||||
; GREEDY-NEXT: {{ $}}
|
||||
; GREEDY-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; GREEDY-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; GREEDY-NEXT: {{ $}}
|
||||
; GREEDY-NEXT: bb.4:
|
||||
; GREEDY-NEXT: [[COPY10:%[0-9]+]]:vgpr(p1) = COPY [[DEF]](p1)
|
||||
|
|
|
|||
|
|
@ -135,7 +135,7 @@ define amdgpu_ps void @sample_1d_vgpr_vaddr__vgpr_rsrc__sgpr_samp(<8 x i32> %rsr
|
|||
; FAST-NEXT: [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF
|
||||
; FAST-NEXT: [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
|
||||
; FAST-NEXT: [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64), [[UV2:%[0-9]+]]:vreg_64(s64), [[UV3:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<8 x s32>)
|
||||
; FAST-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; FAST-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; FAST-NEXT: {{ $}}
|
||||
; FAST-NEXT: bb.2:
|
||||
; FAST-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -169,7 +169,7 @@ define amdgpu_ps void @sample_1d_vgpr_vaddr__vgpr_rsrc__sgpr_samp(<8 x i32> %rsr
|
|||
; FAST-NEXT: bb.3:
|
||||
; FAST-NEXT: successors: %bb.4(0x80000000)
|
||||
; FAST-NEXT: {{ $}}
|
||||
; FAST-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; FAST-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; FAST-NEXT: {{ $}}
|
||||
; FAST-NEXT: bb.4:
|
||||
; FAST-NEXT: G_STORE [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>), [[DEF]](p1) :: (store (<4 x s32>) into `<4 x float> addrspace(1)* undef`, addrspace 1)
|
||||
|
|
@ -197,7 +197,7 @@ define amdgpu_ps void @sample_1d_vgpr_vaddr__vgpr_rsrc__sgpr_samp(<8 x i32> %rsr
|
|||
; GREEDY-NEXT: [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF
|
||||
; GREEDY-NEXT: [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
|
||||
; GREEDY-NEXT: [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64), [[UV2:%[0-9]+]]:vreg_64(s64), [[UV3:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<8 x s32>)
|
||||
; GREEDY-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; GREEDY-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; GREEDY-NEXT: {{ $}}
|
||||
; GREEDY-NEXT: bb.2:
|
||||
; GREEDY-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -231,7 +231,7 @@ define amdgpu_ps void @sample_1d_vgpr_vaddr__vgpr_rsrc__sgpr_samp(<8 x i32> %rsr
|
|||
; GREEDY-NEXT: bb.3:
|
||||
; GREEDY-NEXT: successors: %bb.4(0x80000000)
|
||||
; GREEDY-NEXT: {{ $}}
|
||||
; GREEDY-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; GREEDY-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; GREEDY-NEXT: {{ $}}
|
||||
; GREEDY-NEXT: bb.4:
|
||||
; GREEDY-NEXT: G_STORE [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>), [[DEF]](p1) :: (store (<4 x s32>) into `<4 x float> addrspace(1)* undef`, addrspace 1)
|
||||
|
|
@ -266,7 +266,7 @@ define amdgpu_ps void @sample_1d_vgpr_vaddr__sgpr_rsrc__vgpr_samp(<8 x i32> inre
|
|||
; FAST-NEXT: [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF
|
||||
; FAST-NEXT: [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
|
||||
; FAST-NEXT: [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x s32>)
|
||||
; FAST-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; FAST-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; FAST-NEXT: {{ $}}
|
||||
; FAST-NEXT: bb.2:
|
||||
; FAST-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -290,7 +290,7 @@ define amdgpu_ps void @sample_1d_vgpr_vaddr__sgpr_rsrc__vgpr_samp(<8 x i32> inre
|
|||
; FAST-NEXT: bb.3:
|
||||
; FAST-NEXT: successors: %bb.4(0x80000000)
|
||||
; FAST-NEXT: {{ $}}
|
||||
; FAST-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; FAST-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; FAST-NEXT: {{ $}}
|
||||
; FAST-NEXT: bb.4:
|
||||
; FAST-NEXT: G_STORE [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>), [[DEF]](p1) :: (store (<4 x s32>) into `<4 x float> addrspace(1)* undef`, addrspace 1)
|
||||
|
|
@ -318,7 +318,7 @@ define amdgpu_ps void @sample_1d_vgpr_vaddr__sgpr_rsrc__vgpr_samp(<8 x i32> inre
|
|||
; GREEDY-NEXT: [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF
|
||||
; GREEDY-NEXT: [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
|
||||
; GREEDY-NEXT: [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x s32>)
|
||||
; GREEDY-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; GREEDY-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; GREEDY-NEXT: {{ $}}
|
||||
; GREEDY-NEXT: bb.2:
|
||||
; GREEDY-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -342,7 +342,7 @@ define amdgpu_ps void @sample_1d_vgpr_vaddr__sgpr_rsrc__vgpr_samp(<8 x i32> inre
|
|||
; GREEDY-NEXT: bb.3:
|
||||
; GREEDY-NEXT: successors: %bb.4(0x80000000)
|
||||
; GREEDY-NEXT: {{ $}}
|
||||
; GREEDY-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; GREEDY-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; GREEDY-NEXT: {{ $}}
|
||||
; GREEDY-NEXT: bb.4:
|
||||
; GREEDY-NEXT: G_STORE [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>), [[DEF]](p1) :: (store (<4 x s32>) into `<4 x float> addrspace(1)* undef`, addrspace 1)
|
||||
|
|
@ -378,7 +378,7 @@ define amdgpu_ps void @sample_1d_vgpr_vaddr__vgpr_rsrc__vgpr_samp(<8 x i32> %rsr
|
|||
; FAST-NEXT: [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
|
||||
; FAST-NEXT: [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64), [[UV2:%[0-9]+]]:vreg_64(s64), [[UV3:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<8 x s32>)
|
||||
; FAST-NEXT: [[UV4:%[0-9]+]]:vreg_64(s64), [[UV5:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x s32>)
|
||||
; FAST-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; FAST-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; FAST-NEXT: {{ $}}
|
||||
; FAST-NEXT: bb.2:
|
||||
; FAST-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -423,7 +423,7 @@ define amdgpu_ps void @sample_1d_vgpr_vaddr__vgpr_rsrc__vgpr_samp(<8 x i32> %rsr
|
|||
; FAST-NEXT: bb.3:
|
||||
; FAST-NEXT: successors: %bb.4(0x80000000)
|
||||
; FAST-NEXT: {{ $}}
|
||||
; FAST-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; FAST-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; FAST-NEXT: {{ $}}
|
||||
; FAST-NEXT: bb.4:
|
||||
; FAST-NEXT: G_STORE [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>), [[DEF]](p1) :: (store (<4 x s32>) into `<4 x float> addrspace(1)* undef`, addrspace 1)
|
||||
|
|
@ -452,7 +452,7 @@ define amdgpu_ps void @sample_1d_vgpr_vaddr__vgpr_rsrc__vgpr_samp(<8 x i32> %rsr
|
|||
; GREEDY-NEXT: [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
|
||||
; GREEDY-NEXT: [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64), [[UV2:%[0-9]+]]:vreg_64(s64), [[UV3:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<8 x s32>)
|
||||
; GREEDY-NEXT: [[UV4:%[0-9]+]]:vreg_64(s64), [[UV5:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x s32>)
|
||||
; GREEDY-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; GREEDY-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; GREEDY-NEXT: {{ $}}
|
||||
; GREEDY-NEXT: bb.2:
|
||||
; GREEDY-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -497,7 +497,7 @@ define amdgpu_ps void @sample_1d_vgpr_vaddr__vgpr_rsrc__vgpr_samp(<8 x i32> %rsr
|
|||
; GREEDY-NEXT: bb.3:
|
||||
; GREEDY-NEXT: successors: %bb.4(0x80000000)
|
||||
; GREEDY-NEXT: {{ $}}
|
||||
; GREEDY-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; GREEDY-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; GREEDY-NEXT: {{ $}}
|
||||
; GREEDY-NEXT: bb.4:
|
||||
; GREEDY-NEXT: G_STORE [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>), [[DEF]](p1) :: (store (<4 x s32>) into `<4 x float> addrspace(1)* undef`, addrspace 1)
|
||||
|
|
|
|||
|
|
@ -65,7 +65,7 @@ define amdgpu_ps float @raw_buffer_load__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr
|
|||
; CHECK-NEXT: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
|
||||
; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
|
||||
; CHECK-NEXT: [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
|
||||
; CHECK-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.2:
|
||||
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -89,7 +89,7 @@ define amdgpu_ps float @raw_buffer_load__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr
|
|||
; CHECK-NEXT: bb.3:
|
||||
; CHECK-NEXT: successors: %bb.4(0x80000000)
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.4:
|
||||
; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32)
|
||||
|
|
@ -115,7 +115,7 @@ define amdgpu_ps float @raw_buffer_load__sgpr_rsrc__vgpr_val__vgpr_voffset__vgpr
|
|||
; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
|
||||
; CHECK-NEXT: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
|
||||
; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
|
||||
; CHECK-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.2:
|
||||
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -131,7 +131,7 @@ define amdgpu_ps float @raw_buffer_load__sgpr_rsrc__vgpr_val__vgpr_voffset__vgpr
|
|||
; CHECK-NEXT: bb.3:
|
||||
; CHECK-NEXT: successors: %bb.4(0x80000000)
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.4:
|
||||
; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32)
|
||||
|
|
@ -158,7 +158,7 @@ define amdgpu_ps float @raw_buffer_load__vgpr_rsrc__vgpr_val__vgpr_voffset__vgpr
|
|||
; CHECK-NEXT: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
|
||||
; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
|
||||
; CHECK-NEXT: [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
|
||||
; CHECK-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.2:
|
||||
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -185,7 +185,7 @@ define amdgpu_ps float @raw_buffer_load__vgpr_rsrc__vgpr_val__vgpr_voffset__vgpr
|
|||
; CHECK-NEXT: bb.3:
|
||||
; CHECK-NEXT: successors: %bb.4(0x80000000)
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.4:
|
||||
; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32)
|
||||
|
|
|
|||
|
|
@ -1564,7 +1564,7 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc(<4 x i32> %rsrc, i32 inreg %
|
|||
; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
|
||||
; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
|
||||
; CHECK-NEXT: [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
|
||||
; CHECK-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.2:
|
||||
; CHECK-NEXT: successors: %bb.3, %bb.2
|
||||
|
|
@ -1586,7 +1586,7 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc(<4 x i32> %rsrc, i32 inreg %
|
|||
; CHECK-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.3:
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.4:
|
||||
; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32)
|
||||
|
|
@ -1606,7 +1606,7 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc(<4 x i32> %rsrc, i32 inreg %
|
|||
; GREEDY-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
|
||||
; GREEDY-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
|
||||
; GREEDY-NEXT: [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
|
||||
; GREEDY-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; GREEDY-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; GREEDY-NEXT: {{ $}}
|
||||
; GREEDY-NEXT: bb.2:
|
||||
; GREEDY-NEXT: successors: %bb.3, %bb.2
|
||||
|
|
@ -1628,7 +1628,7 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc(<4 x i32> %rsrc, i32 inreg %
|
|||
; GREEDY-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
|
||||
; GREEDY-NEXT: {{ $}}
|
||||
; GREEDY-NEXT: bb.3:
|
||||
; GREEDY-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; GREEDY-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; GREEDY-NEXT: {{ $}}
|
||||
; GREEDY-NEXT: bb.4:
|
||||
; GREEDY-NEXT: $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32)
|
||||
|
|
@ -1655,7 +1655,7 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_soffset_add_4092(<4 x i32> %
|
|||
; CHECK-NEXT: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
|
||||
; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
|
||||
; CHECK-NEXT: [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
|
||||
; CHECK-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.2:
|
||||
; CHECK-NEXT: successors: %bb.3, %bb.2
|
||||
|
|
@ -1677,7 +1677,7 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_soffset_add_4092(<4 x i32> %
|
|||
; CHECK-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.3:
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.4:
|
||||
; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32)
|
||||
|
|
@ -1698,7 +1698,7 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_soffset_add_4092(<4 x i32> %
|
|||
; GREEDY-NEXT: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
|
||||
; GREEDY-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
|
||||
; GREEDY-NEXT: [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
|
||||
; GREEDY-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; GREEDY-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; GREEDY-NEXT: {{ $}}
|
||||
; GREEDY-NEXT: bb.2:
|
||||
; GREEDY-NEXT: successors: %bb.3, %bb.2
|
||||
|
|
@ -1720,7 +1720,7 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_soffset_add_4092(<4 x i32> %
|
|||
; GREEDY-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
|
||||
; GREEDY-NEXT: {{ $}}
|
||||
; GREEDY-NEXT: bb.3:
|
||||
; GREEDY-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; GREEDY-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; GREEDY-NEXT: {{ $}}
|
||||
; GREEDY-NEXT: bb.4:
|
||||
; GREEDY-NEXT: $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32)
|
||||
|
|
@ -1749,7 +1749,7 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_soffset_add_4096(<4 x i32> %
|
|||
; CHECK-NEXT: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
|
||||
; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
|
||||
; CHECK-NEXT: [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
|
||||
; CHECK-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.2:
|
||||
; CHECK-NEXT: successors: %bb.3, %bb.2
|
||||
|
|
@ -1771,7 +1771,7 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_soffset_add_4096(<4 x i32> %
|
|||
; CHECK-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.3:
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.4:
|
||||
; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32)
|
||||
|
|
@ -1793,7 +1793,7 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_soffset_add_4096(<4 x i32> %
|
|||
; GREEDY-NEXT: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
|
||||
; GREEDY-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
|
||||
; GREEDY-NEXT: [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
|
||||
; GREEDY-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; GREEDY-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; GREEDY-NEXT: {{ $}}
|
||||
; GREEDY-NEXT: bb.2:
|
||||
; GREEDY-NEXT: successors: %bb.3, %bb.2
|
||||
|
|
@ -1815,7 +1815,7 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_soffset_add_4096(<4 x i32> %
|
|||
; GREEDY-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
|
||||
; GREEDY-NEXT: {{ $}}
|
||||
; GREEDY-NEXT: bb.3:
|
||||
; GREEDY-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; GREEDY-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; GREEDY-NEXT: {{ $}}
|
||||
; GREEDY-NEXT: bb.4:
|
||||
; GREEDY-NEXT: $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32)
|
||||
|
|
@ -1842,7 +1842,7 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_offset_4095(<4 x i32> %rsrc)
|
|||
; CHECK-NEXT: [[C3:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
|
||||
; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
|
||||
; CHECK-NEXT: [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
|
||||
; CHECK-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.2:
|
||||
; CHECK-NEXT: successors: %bb.3, %bb.2
|
||||
|
|
@ -1864,7 +1864,7 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_offset_4095(<4 x i32> %rsrc)
|
|||
; CHECK-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.3:
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.4:
|
||||
; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32)
|
||||
|
|
@ -1884,7 +1884,7 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_offset_4095(<4 x i32> %rsrc)
|
|||
; GREEDY-NEXT: [[C3:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
|
||||
; GREEDY-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
|
||||
; GREEDY-NEXT: [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
|
||||
; GREEDY-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; GREEDY-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; GREEDY-NEXT: {{ $}}
|
||||
; GREEDY-NEXT: bb.2:
|
||||
; GREEDY-NEXT: successors: %bb.3, %bb.2
|
||||
|
|
@ -1906,7 +1906,7 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_offset_4095(<4 x i32> %rsrc)
|
|||
; GREEDY-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
|
||||
; GREEDY-NEXT: {{ $}}
|
||||
; GREEDY-NEXT: bb.3:
|
||||
; GREEDY-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; GREEDY-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; GREEDY-NEXT: {{ $}}
|
||||
; GREEDY-NEXT: bb.4:
|
||||
; GREEDY-NEXT: $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32)
|
||||
|
|
@ -1932,7 +1932,7 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_offset_4096(<4 x i32> %rsrc)
|
|||
; CHECK-NEXT: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
|
||||
; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
|
||||
; CHECK-NEXT: [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
|
||||
; CHECK-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.2:
|
||||
; CHECK-NEXT: successors: %bb.3, %bb.2
|
||||
|
|
@ -1954,7 +1954,7 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_offset_4096(<4 x i32> %rsrc)
|
|||
; CHECK-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.3:
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.4:
|
||||
; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32)
|
||||
|
|
@ -1974,7 +1974,7 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_offset_4096(<4 x i32> %rsrc)
|
|||
; GREEDY-NEXT: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
|
||||
; GREEDY-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
|
||||
; GREEDY-NEXT: [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
|
||||
; GREEDY-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; GREEDY-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; GREEDY-NEXT: {{ $}}
|
||||
; GREEDY-NEXT: bb.2:
|
||||
; GREEDY-NEXT: successors: %bb.3, %bb.2
|
||||
|
|
@ -1996,7 +1996,7 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_offset_4096(<4 x i32> %rsrc)
|
|||
; GREEDY-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
|
||||
; GREEDY-NEXT: {{ $}}
|
||||
; GREEDY-NEXT: bb.3:
|
||||
; GREEDY-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; GREEDY-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; GREEDY-NEXT: {{ $}}
|
||||
; GREEDY-NEXT: bb.4:
|
||||
; GREEDY-NEXT: $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32)
|
||||
|
|
@ -2024,7 +2024,7 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4064(<4 x i32> %
|
|||
; CHECK-NEXT: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
|
||||
; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
|
||||
; CHECK-NEXT: [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
|
||||
; CHECK-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.2:
|
||||
; CHECK-NEXT: successors: %bb.3, %bb.2
|
||||
|
|
@ -2047,7 +2047,7 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4064(<4 x i32> %
|
|||
; CHECK-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.3:
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.4:
|
||||
; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x s32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x s32>), [[AMDGPU_BUFFER_LOAD1]](<4 x s32>)
|
||||
|
|
@ -2077,7 +2077,7 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4064(<4 x i32> %
|
|||
; GREEDY-NEXT: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
|
||||
; GREEDY-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
|
||||
; GREEDY-NEXT: [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
|
||||
; GREEDY-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; GREEDY-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; GREEDY-NEXT: {{ $}}
|
||||
; GREEDY-NEXT: bb.2:
|
||||
; GREEDY-NEXT: successors: %bb.3, %bb.2
|
||||
|
|
@ -2100,7 +2100,7 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4064(<4 x i32> %
|
|||
; GREEDY-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
|
||||
; GREEDY-NEXT: {{ $}}
|
||||
; GREEDY-NEXT: bb.3:
|
||||
; GREEDY-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; GREEDY-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; GREEDY-NEXT: {{ $}}
|
||||
; GREEDY-NEXT: bb.4:
|
||||
; GREEDY-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x s32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x s32>), [[AMDGPU_BUFFER_LOAD1]](<4 x s32>)
|
||||
|
|
@ -2139,7 +2139,7 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4068(<4 x i32> %
|
|||
; CHECK-NEXT: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
|
||||
; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
|
||||
; CHECK-NEXT: [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
|
||||
; CHECK-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.2:
|
||||
; CHECK-NEXT: successors: %bb.3, %bb.2
|
||||
|
|
@ -2162,7 +2162,7 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4068(<4 x i32> %
|
|||
; CHECK-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.3:
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.4:
|
||||
; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x s32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x s32>), [[AMDGPU_BUFFER_LOAD1]](<4 x s32>)
|
||||
|
|
@ -2193,7 +2193,7 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4068(<4 x i32> %
|
|||
; GREEDY-NEXT: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
|
||||
; GREEDY-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
|
||||
; GREEDY-NEXT: [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
|
||||
; GREEDY-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; GREEDY-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; GREEDY-NEXT: {{ $}}
|
||||
; GREEDY-NEXT: bb.2:
|
||||
; GREEDY-NEXT: successors: %bb.3, %bb.2
|
||||
|
|
@ -2216,7 +2216,7 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4068(<4 x i32> %
|
|||
; GREEDY-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
|
||||
; GREEDY-NEXT: {{ $}}
|
||||
; GREEDY-NEXT: bb.3:
|
||||
; GREEDY-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; GREEDY-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; GREEDY-NEXT: {{ $}}
|
||||
; GREEDY-NEXT: bb.4:
|
||||
; GREEDY-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x s32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x s32>), [[AMDGPU_BUFFER_LOAD1]](<4 x s32>)
|
||||
|
|
@ -2253,7 +2253,7 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4096(<4 x i32> %
|
|||
; CHECK-NEXT: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
|
||||
; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
|
||||
; CHECK-NEXT: [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
|
||||
; CHECK-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.2:
|
||||
; CHECK-NEXT: successors: %bb.3, %bb.2
|
||||
|
|
@ -2276,7 +2276,7 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4096(<4 x i32> %
|
|||
; CHECK-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.3:
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.4:
|
||||
; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x s32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x s32>), [[AMDGPU_BUFFER_LOAD1]](<4 x s32>)
|
||||
|
|
@ -2307,7 +2307,7 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4096(<4 x i32> %
|
|||
; GREEDY-NEXT: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
|
||||
; GREEDY-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
|
||||
; GREEDY-NEXT: [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
|
||||
; GREEDY-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; GREEDY-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; GREEDY-NEXT: {{ $}}
|
||||
; GREEDY-NEXT: bb.2:
|
||||
; GREEDY-NEXT: successors: %bb.3, %bb.2
|
||||
|
|
@ -2330,7 +2330,7 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4096(<4 x i32> %
|
|||
; GREEDY-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
|
||||
; GREEDY-NEXT: {{ $}}
|
||||
; GREEDY-NEXT: bb.3:
|
||||
; GREEDY-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; GREEDY-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; GREEDY-NEXT: {{ $}}
|
||||
; GREEDY-NEXT: bb.4:
|
||||
; GREEDY-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x s32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x s32>), [[AMDGPU_BUFFER_LOAD1]](<4 x s32>)
|
||||
|
|
@ -2366,7 +2366,7 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_5000
|
|||
; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
|
||||
; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
|
||||
; CHECK-NEXT: [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
|
||||
; CHECK-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.2:
|
||||
; CHECK-NEXT: successors: %bb.3, %bb.2
|
||||
|
|
@ -2389,7 +2389,7 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_5000
|
|||
; CHECK-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.3:
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.4:
|
||||
; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x s32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x s32>), [[AMDGPU_BUFFER_LOAD1]](<4 x s32>)
|
||||
|
|
@ -2419,7 +2419,7 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_5000
|
|||
; GREEDY-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
|
||||
; GREEDY-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
|
||||
; GREEDY-NEXT: [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
|
||||
; GREEDY-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; GREEDY-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; GREEDY-NEXT: {{ $}}
|
||||
; GREEDY-NEXT: bb.2:
|
||||
; GREEDY-NEXT: successors: %bb.3, %bb.2
|
||||
|
|
@ -2442,7 +2442,7 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_5000
|
|||
; GREEDY-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
|
||||
; GREEDY-NEXT: {{ $}}
|
||||
; GREEDY-NEXT: bb.3:
|
||||
; GREEDY-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; GREEDY-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; GREEDY-NEXT: {{ $}}
|
||||
; GREEDY-NEXT: bb.4:
|
||||
; GREEDY-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x s32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x s32>), [[AMDGPU_BUFFER_LOAD1]](<4 x s32>)
|
||||
|
|
@ -2478,7 +2478,7 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4076
|
|||
; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
|
||||
; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
|
||||
; CHECK-NEXT: [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
|
||||
; CHECK-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.2:
|
||||
; CHECK-NEXT: successors: %bb.3, %bb.2
|
||||
|
|
@ -2501,7 +2501,7 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4076
|
|||
; CHECK-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.3:
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.4:
|
||||
; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x s32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x s32>), [[AMDGPU_BUFFER_LOAD1]](<4 x s32>)
|
||||
|
|
@ -2531,7 +2531,7 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4076
|
|||
; GREEDY-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
|
||||
; GREEDY-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
|
||||
; GREEDY-NEXT: [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
|
||||
; GREEDY-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; GREEDY-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; GREEDY-NEXT: {{ $}}
|
||||
; GREEDY-NEXT: bb.2:
|
||||
; GREEDY-NEXT: successors: %bb.3, %bb.2
|
||||
|
|
@ -2554,7 +2554,7 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4076
|
|||
; GREEDY-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
|
||||
; GREEDY-NEXT: {{ $}}
|
||||
; GREEDY-NEXT: bb.3:
|
||||
; GREEDY-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; GREEDY-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; GREEDY-NEXT: {{ $}}
|
||||
; GREEDY-NEXT: bb.4:
|
||||
; GREEDY-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x s32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x s32>), [[AMDGPU_BUFFER_LOAD1]](<4 x s32>)
|
||||
|
|
@ -2590,7 +2590,7 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4080
|
|||
; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
|
||||
; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
|
||||
; CHECK-NEXT: [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
|
||||
; CHECK-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.2:
|
||||
; CHECK-NEXT: successors: %bb.3, %bb.2
|
||||
|
|
@ -2613,7 +2613,7 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4080
|
|||
; CHECK-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.3:
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.4:
|
||||
; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x s32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x s32>), [[AMDGPU_BUFFER_LOAD1]](<4 x s32>)
|
||||
|
|
@ -2643,7 +2643,7 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4080
|
|||
; GREEDY-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
|
||||
; GREEDY-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
|
||||
; GREEDY-NEXT: [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
|
||||
; GREEDY-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; GREEDY-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; GREEDY-NEXT: {{ $}}
|
||||
; GREEDY-NEXT: bb.2:
|
||||
; GREEDY-NEXT: successors: %bb.3, %bb.2
|
||||
|
|
@ -2666,7 +2666,7 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_add_4080
|
|||
; GREEDY-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
|
||||
; GREEDY-NEXT: {{ $}}
|
||||
; GREEDY-NEXT: bb.3:
|
||||
; GREEDY-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; GREEDY-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; GREEDY-NEXT: {{ $}}
|
||||
; GREEDY-NEXT: bb.4:
|
||||
; GREEDY-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x s32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x s32>), [[AMDGPU_BUFFER_LOAD1]](<4 x s32>)
|
||||
|
|
@ -2701,7 +2701,7 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_offset_4
|
|||
; CHECK-NEXT: [[C3:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
|
||||
; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
|
||||
; CHECK-NEXT: [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
|
||||
; CHECK-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.2:
|
||||
; CHECK-NEXT: successors: %bb.3, %bb.2
|
||||
|
|
@ -2724,7 +2724,7 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_offset_4
|
|||
; CHECK-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.3:
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.4:
|
||||
; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x s32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x s32>), [[AMDGPU_BUFFER_LOAD1]](<4 x s32>)
|
||||
|
|
@ -2753,7 +2753,7 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_offset_4
|
|||
; GREEDY-NEXT: [[C3:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
|
||||
; GREEDY-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
|
||||
; GREEDY-NEXT: [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
|
||||
; GREEDY-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; GREEDY-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; GREEDY-NEXT: {{ $}}
|
||||
; GREEDY-NEXT: bb.2:
|
||||
; GREEDY-NEXT: successors: %bb.3, %bb.2
|
||||
|
|
@ -2776,7 +2776,7 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_vgpr_rsrc_offset_4
|
|||
; GREEDY-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
|
||||
; GREEDY-NEXT: {{ $}}
|
||||
; GREEDY-NEXT: bb.3:
|
||||
; GREEDY-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; GREEDY-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; GREEDY-NEXT: {{ $}}
|
||||
; GREEDY-NEXT: bb.4:
|
||||
; GREEDY-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x s32>) = G_CONCAT_VECTORS [[AMDGPU_BUFFER_LOAD]](<4 x s32>), [[AMDGPU_BUFFER_LOAD1]](<4 x s32>)
|
||||
|
|
|
|||
|
|
@ -63,7 +63,7 @@ define amdgpu_ps float @struct_buffer_load__vgpr_rsrc__vgpr_val__vgpr_vindex__vg
|
|||
; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
|
||||
; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
|
||||
; CHECK-NEXT: [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
|
||||
; CHECK-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.2:
|
||||
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -87,7 +87,7 @@ define amdgpu_ps float @struct_buffer_load__vgpr_rsrc__vgpr_val__vgpr_vindex__vg
|
|||
; CHECK-NEXT: bb.3:
|
||||
; CHECK-NEXT: successors: %bb.4(0x80000000)
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.4:
|
||||
; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32)
|
||||
|
|
@ -112,7 +112,7 @@ define amdgpu_ps float @struct_buffer_load__sgpr_rsrc__vgpr_val__vgpr_vindex_vgp
|
|||
; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
|
||||
; CHECK-NEXT: [[COPY6:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2
|
||||
; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
|
||||
; CHECK-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.2:
|
||||
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -128,7 +128,7 @@ define amdgpu_ps float @struct_buffer_load__sgpr_rsrc__vgpr_val__vgpr_vindex_vgp
|
|||
; CHECK-NEXT: bb.3:
|
||||
; CHECK-NEXT: successors: %bb.4(0x80000000)
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.4:
|
||||
; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32)
|
||||
|
|
@ -154,7 +154,7 @@ define amdgpu_ps float @struct_buffer_load__vgpr_rsrc__vgpr_val__vgpr_vindex__vg
|
|||
; CHECK-NEXT: [[COPY6:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr6
|
||||
; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
|
||||
; CHECK-NEXT: [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
|
||||
; CHECK-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.2:
|
||||
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -181,7 +181,7 @@ define amdgpu_ps float @struct_buffer_load__vgpr_rsrc__vgpr_val__vgpr_vindex__vg
|
|||
; CHECK-NEXT: bb.3:
|
||||
; CHECK-NEXT: successors: %bb.4(0x80000000)
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.4:
|
||||
; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_BUFFER_LOAD]](s32)
|
||||
|
|
|
|||
|
|
@ -65,7 +65,7 @@ define amdgpu_ps void @struct_buffer_store__vgpr_rsrc__vgpr_val__vgpr_vindex__vg
|
|||
; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
|
||||
; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
|
||||
; CHECK-NEXT: [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
|
||||
; CHECK-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.2:
|
||||
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -89,7 +89,7 @@ define amdgpu_ps void @struct_buffer_store__vgpr_rsrc__vgpr_val__vgpr_vindex__vg
|
|||
; CHECK-NEXT: bb.3:
|
||||
; CHECK-NEXT: successors: %bb.4(0x80000000)
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.4:
|
||||
; CHECK-NEXT: S_ENDPGM 0
|
||||
|
|
@ -114,7 +114,7 @@ define amdgpu_ps void @struct_buffer_store__sgpr_rsrc__vgpr_val__vgpr_vindex__vg
|
|||
; CHECK-NEXT: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
|
||||
; CHECK-NEXT: [[COPY7:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr3
|
||||
; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
|
||||
; CHECK-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.2:
|
||||
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -130,7 +130,7 @@ define amdgpu_ps void @struct_buffer_store__sgpr_rsrc__vgpr_val__vgpr_vindex__vg
|
|||
; CHECK-NEXT: bb.3:
|
||||
; CHECK-NEXT: successors: %bb.4(0x80000000)
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.4:
|
||||
; CHECK-NEXT: S_ENDPGM 0
|
||||
|
|
@ -156,7 +156,7 @@ define amdgpu_ps void @struct_buffer_store__vgpr_rsrc__vgpr_val__vgpr_vindex__vg
|
|||
; CHECK-NEXT: [[COPY7:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr7
|
||||
; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
|
||||
; CHECK-NEXT: [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)
|
||||
; CHECK-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.2:
|
||||
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -183,7 +183,7 @@ define amdgpu_ps void @struct_buffer_store__vgpr_rsrc__vgpr_val__vgpr_vindex__vg
|
|||
; CHECK-NEXT: bb.3:
|
||||
; CHECK-NEXT: successors: %bb.4(0x80000000)
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: bb.4:
|
||||
; CHECK-NEXT: S_ENDPGM 0
|
||||
|
|
|
|||
|
|
@ -25,7 +25,7 @@ body: |
|
|||
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY %zero(s32)
|
||||
; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
|
||||
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY %agpr(s32)
|
||||
; CHECK-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: .1:
|
||||
; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
|
||||
|
|
@ -41,7 +41,7 @@ body: |
|
|||
; CHECK-NEXT: .2:
|
||||
; CHECK-NEXT: successors: %bb.3(0x80000000)
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: .3:
|
||||
; CHECK-NEXT: S_ENDPGM 0
|
||||
|
|
@ -72,7 +72,7 @@ body: |
|
|||
; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
|
||||
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(<8 x s32>) = COPY [[COPY]](<8 x s32>)
|
||||
; CHECK-NEXT: [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64), [[UV2:%[0-9]+]]:vreg_64(s64), [[UV3:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[COPY2]](<8 x s32>)
|
||||
; CHECK-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: .1:
|
||||
; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
|
||||
|
|
@ -106,7 +106,7 @@ body: |
|
|||
; CHECK-NEXT: .2:
|
||||
; CHECK-NEXT: successors: %bb.3(0x80000000)
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
|
||||
; CHECK-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]]
|
||||
; CHECK-NEXT: {{ $}}
|
||||
; CHECK-NEXT: .3:
|
||||
; CHECK-NEXT: S_ENDPGM 0, implicit [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
|
||||
|
|
|
|||
|
|
@ -1199,8 +1199,8 @@ define void @test_indirect_call_vgpr_ptr_inreg_arg(void(i32)* %fptr) {
|
|||
; GISEL-NEXT: v_writelane_b32 v40, s62, 28
|
||||
; GISEL-NEXT: v_writelane_b32 v40, s63, 29
|
||||
; GISEL-NEXT: s_mov_b64 s[6:7], s[30:31]
|
||||
; GISEL-NEXT: s_movk_i32 s4, 0x7b
|
||||
; GISEL-NEXT: s_mov_b64 s[8:9], exec
|
||||
; GISEL-NEXT: s_movk_i32 s4, 0x7b
|
||||
; GISEL-NEXT: .LBB6_1: ; =>This Inner Loop Header: Depth=1
|
||||
; GISEL-NEXT: v_readfirstlane_b32 s10, v0
|
||||
; GISEL-NEXT: v_readfirstlane_b32 s11, v1
|
||||
|
|
|
|||
Loading…
Reference in New Issue