forked from OSchip/llvm-project
AMDGPU/GlobalISel: Make sure <2 x s1> phis are scalarized
This commit is contained in:
Matt Arsenault
parent
6f961a1e7e
commit
bcf5184a68
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@ -415,11 +415,12 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
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.legalFor(AllS64Vectors)
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.legalFor(AddrSpaces64)
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.legalFor(AddrSpaces32)
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.legalIf(isPointer(0))
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.clampScalar(0, S32, S256)
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.widenScalarToNextPow2(0, 32)
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.clampMaxNumElements(0, S32, 16)
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.moreElementsIf(isSmallOddVector(0), oneMoreElement(0))
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.legalIf(isPointer(0));
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.scalarize(0);
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if (ST.hasVOP3PInsts()) {
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assert(ST.hasIntClamp() && "all targets with VOP3P should support clamp");
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@ -1547,3 +1547,94 @@ body: |
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S_SETPC_B64 undef $sgpr30_sgpr31
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...
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---
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name: test_phi_v2s1
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: test_phi_v2s1
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; CHECK: bb.0:
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; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
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; CHECK: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
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; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2
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; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr1
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
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; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
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; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C1]](s32)
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; CHECK: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
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; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
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; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
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; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
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; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C2]]
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; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
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; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C2]]
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; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[AND]](s32), [[AND1]]
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; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
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; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C2]]
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; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
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; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C2]]
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; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[AND2]](s32), [[AND3]]
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; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY3]](s32), [[C]]
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; CHECK: G_BRCOND [[ICMP2]](s1), %bb.1
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; CHECK: G_BR %bb.2
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; CHECK: bb.1:
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; CHECK: successors: %bb.2(0x80000000)
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; CHECK: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
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; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
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; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C3]](s32)
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; CHECK: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[COPY2]](<2 x s16>)
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; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C3]](s32)
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; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
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; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
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; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C4]]
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; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
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; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C4]]
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; CHECK: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND4]](s32), [[AND5]]
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; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
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; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C4]]
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; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
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; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C4]]
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; CHECK: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND6]](s32), [[AND7]]
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; CHECK: G_BR %bb.2
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; CHECK: bb.2:
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; CHECK: [[PHI:%[0-9]+]]:_(s1) = G_PHI [[ICMP]](s1), %bb.0, [[ICMP3]](s1), %bb.1
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; CHECK: [[PHI1:%[0-9]+]]:_(s1) = G_PHI [[ICMP1]](s1), %bb.0, [[ICMP4]](s1), %bb.1
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; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI]](s1)
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; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI1]](s1)
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; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
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; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
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; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C5]]
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; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
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; CHECK: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C5]]
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[AND8]](s32), [[AND9]](s32)
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; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
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; CHECK: S_SETPC_B64 undef $sgpr30_sgpr31
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bb.0:
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successors: %bb.1, %bb.2
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liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
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%0:_(<2 x s16>) = COPY $vgpr0
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%1:_(<2 x s16>) = COPY $vgpr1
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%2:_(<2 x s16>) = COPY $vgpr2
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%3:_(s32) = COPY $vgpr1
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%4:_(s32) = G_CONSTANT i32 0
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%5:_(<2 x s1>) = G_ICMP intpred(eq), %0, %1
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%6:_(s1) = G_ICMP intpred(eq), %3, %4
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G_BRCOND %6, %bb.1
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G_BR %bb.2
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bb.1:
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successors: %bb.2
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%7:_(<2 x s1>) = G_ICMP intpred(ne), %0, %2
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G_BR %bb.2
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bb.2:
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%8:_(<2 x s1>) = G_PHI %5, %bb.0, %7, %bb.1
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%9:_(<2 x s32>) = G_ZEXT %8
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$vgpr0_vgpr1 = COPY %9
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S_SETPC_B64 undef $sgpr30_sgpr31
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...
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