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[AArch64] Handle ISD::LROUND and ISD::LLROUND for float16 

This patch is a follow up for D61391 to add lround/llround
support for float16.

Reviewed By: SjoerdMeijer

Differential Revision: https://reviews.llvm.org/D62861

llvm-svn: 362698
This commit is contained in:
Adhemerval Zanella 2019-06-06 11:53:26 +00:00
parent dc8affe607
commit bce9e11a7b
4 changed files with 105 additions and 0 deletions
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8
llvm/lib/Target/AArch64/AArch64InstrInfo.td
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@ -3083,6 +3083,14 @@ defm : FPToIntegerPats<fp_to_uint, ftrunc, "FCVTZU">;
defm : FPToIntegerPats<fp_to_sint, fround, "FCVTAS">;
defm : FPToIntegerPats<fp_to_uint, fround, "FCVTAU">;
let Predicates = [HasFullFP16] in {
def : Pat<(i32 (lround f16:$Rn)),
(!cast<Instruction>(FCVTASUWHr) f16:$Rn)>;
def : Pat<(i64 (lround f16:$Rn)),
(!cast<Instruction>(FCVTASUXHr) f16:$Rn)>;
def : Pat<(i64 (llround f16:$Rn)),
(!cast<Instruction>(FCVTASUXHr) f16:$Rn)>;
}
def : Pat<(i32 (lround f32:$Rn)),
(!cast<Instruction>(FCVTASUWSr) f32:$Rn)>;
def : Pat<(i32 (lround f64:$Rn)),

32
llvm/test/CodeGen/AArch64/llround-conv-fp16.ll Normal file
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@ -0,0 +1,32 @@
; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 | FileCheck %s
; CHECK-LABEL: testmhhs:
; CHECK: fcvtas x0, h0
; CHECK: ret
define i16 @testmhhs(half %x) {
entry:
%0 = tail call i64 @llvm.llround.i64.f16(half %x)
%conv = trunc i64 %0 to i16
ret i16 %conv
}
; CHECK-LABEL: testmhws:
; CHECK: fcvtas x0, h0
; CHECK: ret
define i32 @testmhws(half %x) {
entry:
%0 = tail call i64 @llvm.llround.i64.f16(half %x)
%conv = trunc i64 %0 to i32
ret i32 %conv
}
; CHECK-LABEL: testmhxs:
; CHECK: fcvtas x0, h0
; CHECK-NEXT: ret
define i64 @testmhxs(half %x) {
entry:
%0 = tail call i64 @llvm.llround.i64.f16(half %x)
ret i64 %0
}
declare i64 @llvm.llround.i64.f16(half) nounwind readnone

33
llvm/test/CodeGen/AArch64/lround-conv-fp16-win.ll Normal file
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@ -0,0 +1,33 @@
; RUN: llc < %s -mtriple=aarch64-windows -mattr=+fullfp16 | FileCheck %s
; CHECK-LABEL: testmhhs:
; CHECK: fcvtas w0, h0
; CHECK: ret
define i16 @testmhhs(half %x) {
entry:
%0 = tail call i32 @llvm.lround.i32.f16(half %x)
%conv = trunc i32 %0 to i16
ret i16 %conv
}
; CHECK-LABEL: testmhws:
; CHECK: fcvtas w0, h0
; CHECK: ret
define i32 @testmhws(half %x) {
entry:
%0 = tail call i32 @llvm.lround.i32.f16(half %x)
ret i32 %0
}
; CHECK-LABEL: testmhxs:
; CHECK: fcvtas w8, h0
; CHECK-NEXT: sxtw x0, w8
; CHECK-NEXT: ret
define i64 @testmhxs(half %x) {
entry:
%0 = tail call i32 @llvm.lround.i32.f16(half %x)
%conv = sext i32 %0 to i64
ret i64 %conv
}
declare i32 @llvm.lround.i32.f16(half) nounwind readnone

32
llvm/test/CodeGen/AArch64/lround-conv-fp16.ll Normal file
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@ -0,0 +1,32 @@
; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 | FileCheck %s
; CHECK-LABEL: testmhhs:
; CHECK: fcvtas x0, h0
; CHECK: ret
define i16 @testmhhs(half %x) {
entry:
%0 = tail call i64 @llvm.lround.i64.f16(half %x)
%conv = trunc i64 %0 to i16
ret i16 %conv
}
; CHECK-LABEL: testmhws:
; CHECK: fcvtas x0, h0
; CHECK: ret
define i32 @testmhws(half %x) {
entry:
%0 = tail call i64 @llvm.lround.i64.f16(half %x)
%conv = trunc i64 %0 to i32
ret i32 %conv
}
; CHECK-LABEL: testmhxs:
; CHECK: fcvtas x0, h0
; CHECK-NEXT: ret
define i64 @testmhxs(half %x) {
entry:
%0 = tail call i64 @llvm.lround.i64.f16(half %x)
ret i64 %0
}
declare i64 @llvm.lround.i64.f16(half) nounwind readnone