forked from OSchip/llvm-project
[InstCombine] add tests for funnel shift demanded bits; NFC
llvm-svn: 346762
This commit is contained in:
Sanjay Patel
parent
3635c89070
commit
bcc5a74261
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -instcombine -S | FileCheck %s
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declare i32 @llvm.fshl.i32(i32, i32, i32)
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declare i33 @llvm.fshr.i33(i33, i33, i33)
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declare <2 x i32> @llvm.fshr.v2i32(<2 x i32>, <2 x i32>, <2 x i32>)
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declare <2 x i31> @llvm.fshl.v2i31(<2 x i31>, <2 x i31>, <2 x i31>)
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; If the shift mask doesn't include any demanded bits, the funnel shift can be eliminated.
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define i32 @fshl_mask_simplify1(i32 %x, i32 %y, i32 %sh) {
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; CHECK-LABEL: @fshl_mask_simplify1(
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; CHECK-NEXT: [[MASKEDSH:%.*]] = and i32 [[SH:%.*]], 32
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; CHECK-NEXT: [[R:%.*]] = call i32 @llvm.fshl.i32(i32 [[X:%.*]], i32 [[Y:%.*]], i32 [[MASKEDSH]])
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; CHECK-NEXT: ret i32 [[R]]
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;
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%maskedsh = and i32 %sh, 32
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%r = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 %maskedsh)
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ret i32 %r
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}
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define <2 x i32> @fshr_mask_simplify2(<2 x i32> %x, <2 x i32> %y, <2 x i32> %sh) {
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; CHECK-LABEL: @fshr_mask_simplify2(
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; CHECK-NEXT: [[MASKEDSH:%.*]] = and <2 x i32> [[SH:%.*]], <i32 64, i32 64>
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; CHECK-NEXT: [[R:%.*]] = call <2 x i32> @llvm.fshr.v2i32(<2 x i32> [[X:%.*]], <2 x i32> [[Y:%.*]], <2 x i32> [[MASKEDSH]])
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; CHECK-NEXT: ret <2 x i32> [[R]]
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;
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%maskedsh = and <2 x i32> %sh, <i32 64, i32 64>
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%r = call <2 x i32> @llvm.fshr.v2i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> %maskedsh)
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ret <2 x i32> %r
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}
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; Negative test.
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define i32 @fshl_mask_simplify3(i32 %x, i32 %y, i32 %sh) {
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; CHECK-LABEL: @fshl_mask_simplify3(
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; CHECK-NEXT: [[MASKEDSH:%.*]] = and i32 [[SH:%.*]], 16
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; CHECK-NEXT: [[R:%.*]] = call i32 @llvm.fshl.i32(i32 [[X:%.*]], i32 [[Y:%.*]], i32 [[MASKEDSH]])
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; CHECK-NEXT: ret i32 [[R]]
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;
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%maskedsh = and i32 %sh, 16
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%r = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 %maskedsh)
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ret i32 %r
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}
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; Check again with weird bitwidths; log2(33) means we demand the low 6 bits.
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define i33 @fshr_mask_simplify1(i33 %x, i33 %y, i33 %sh) {
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; CHECK-LABEL: @fshr_mask_simplify1(
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; CHECK-NEXT: [[MASKEDSH:%.*]] = and i33 [[SH:%.*]], 64
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; CHECK-NEXT: [[R:%.*]] = call i33 @llvm.fshr.i33(i33 [[X:%.*]], i33 [[Y:%.*]], i33 [[MASKEDSH]])
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; CHECK-NEXT: ret i33 [[R]]
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;
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%maskedsh = and i33 %sh, 64
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%r = call i33 @llvm.fshr.i33(i33 %x, i33 %y, i33 %maskedsh)
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ret i33 %r
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}
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; Check again with weird bitwidths; log2(31) means we demand the low 5 bits.
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define <2 x i31> @fshl_mask_simplify2(<2 x i31> %x, <2 x i31> %y, <2 x i31> %sh) {
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; CHECK-LABEL: @fshl_mask_simplify2(
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; CHECK-NEXT: [[MASKEDSH:%.*]] = and <2 x i31> [[SH:%.*]], <i31 32, i31 32>
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; CHECK-NEXT: [[R:%.*]] = call <2 x i31> @llvm.fshl.v2i31(<2 x i31> [[X:%.*]], <2 x i31> [[Y:%.*]], <2 x i31> [[MASKEDSH]])
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; CHECK-NEXT: ret <2 x i31> [[R]]
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;
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%maskedsh = and <2 x i31> %sh, <i31 32, i31 32>
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%r = call <2 x i31> @llvm.fshl.v2i31(<2 x i31> %x, <2 x i31> %y, <2 x i31> %maskedsh)
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ret <2 x i31> %r
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}
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; Negative test.
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define i33 @fshr_mask_simplify3(i33 %x, i33 %y, i33 %sh) {
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; CHECK-LABEL: @fshr_mask_simplify3(
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; CHECK-NEXT: [[MASKEDSH:%.*]] = and i33 [[SH:%.*]], 32
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; CHECK-NEXT: [[R:%.*]] = call i33 @llvm.fshr.i33(i33 [[X:%.*]], i33 [[Y:%.*]], i33 [[MASKEDSH]])
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; CHECK-NEXT: ret i33 [[R]]
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;
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%maskedsh = and i33 %sh, 32
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%r = call i33 @llvm.fshr.i33(i33 %x, i33 %y, i33 %maskedsh)
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ret i33 %r
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}
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; This mask op is unnecessary.
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define i32 @fshl_mask_not_required(i32 %x, i32 %y, i32 %sh) {
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; CHECK-LABEL: @fshl_mask_not_required(
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; CHECK-NEXT: [[MASKEDSH:%.*]] = and i32 [[SH:%.*]], 31
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; CHECK-NEXT: [[R:%.*]] = call i32 @llvm.fshl.i32(i32 [[X:%.*]], i32 [[Y:%.*]], i32 [[MASKEDSH]])
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; CHECK-NEXT: ret i32 [[R]]
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;
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%maskedsh = and i32 %sh, 31
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%r = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 %maskedsh)
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ret i32 %r
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}
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; This mask op can be reduced.
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define i32 @fshl_mask_reduce_constant(i32 %x, i32 %y, i32 %sh) {
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; CHECK-LABEL: @fshl_mask_reduce_constant(
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; CHECK-NEXT: [[MASKEDSH:%.*]] = and i32 [[SH:%.*]], 33
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; CHECK-NEXT: [[R:%.*]] = call i32 @llvm.fshl.i32(i32 [[X:%.*]], i32 [[Y:%.*]], i32 [[MASKEDSH]])
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; CHECK-NEXT: ret i32 [[R]]
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;
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%maskedsh = and i32 %sh, 33
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%r = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 %maskedsh)
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ret i32 %r
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}
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; But this mask op is required.
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define i32 @fshl_mask_negative(i32 %x, i32 %y, i32 %sh) {
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; CHECK-LABEL: @fshl_mask_negative(
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; CHECK-NEXT: [[MASKEDSH:%.*]] = and i32 [[SH:%.*]], 15
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; CHECK-NEXT: [[R:%.*]] = call i32 @llvm.fshl.i32(i32 [[X:%.*]], i32 [[Y:%.*]], i32 [[MASKEDSH]])
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; CHECK-NEXT: ret i32 [[R]]
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;
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%maskedsh = and i32 %sh, 15
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%r = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 %maskedsh)
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ret i32 %r
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}
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; The transform is not limited to mask ops.
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define <2 x i32> @fshr_set_but_not_demanded_vec(<2 x i32> %x, <2 x i32> %y, <2 x i32> %sh) {
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; CHECK-LABEL: @fshr_set_but_not_demanded_vec(
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; CHECK-NEXT: [[BOGUSBITS:%.*]] = or <2 x i32> [[SH:%.*]], <i32 32, i32 32>
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; CHECK-NEXT: [[R:%.*]] = call <2 x i32> @llvm.fshr.v2i32(<2 x i32> [[X:%.*]], <2 x i32> [[Y:%.*]], <2 x i32> [[BOGUSBITS]])
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; CHECK-NEXT: ret <2 x i32> [[R]]
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;
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%bogusbits = or <2 x i32> %sh, <i32 32, i32 32>
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%r = call <2 x i32> @llvm.fshr.v2i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> %bogusbits)
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ret <2 x i32> %r
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}
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define <2 x i31> @fshl_set_but_not_demanded_vec(<2 x i31> %x, <2 x i31> %y, <2 x i31> %sh) {
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; CHECK-LABEL: @fshl_set_but_not_demanded_vec(
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; CHECK-NEXT: [[BOGUSBITS:%.*]] = or <2 x i31> [[SH:%.*]], <i31 32, i31 32>
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; CHECK-NEXT: [[R:%.*]] = call <2 x i31> @llvm.fshl.v2i31(<2 x i31> [[X:%.*]], <2 x i31> [[Y:%.*]], <2 x i31> [[BOGUSBITS]])
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; CHECK-NEXT: ret <2 x i31> [[R]]
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;
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%bogusbits = or <2 x i31> %sh, <i31 32, i31 32>
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%r = call <2 x i31> @llvm.fshl.v2i31(<2 x i31> %x, <2 x i31> %y, <2 x i31> %bogusbits)
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ret <2 x i31> %r
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}
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