forked from OSchip/llvm-project
[AMDGPU][MC] Corrected parsing of carry in/out operands in VOP3
Disabled constants as carry in/out operands. See bug 48711. Differential Revision: https://reviews.llvm.org/D100642
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@ -1924,8 +1924,9 @@ bool AMDGPUOperand::isSDWAInt32Operand() const {
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}
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bool AMDGPUOperand::isBoolReg() const {
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return (AsmParser->getFeatureBits()[AMDGPU::FeatureWavefrontSize64] && isSCSrcB64()) ||
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(AsmParser->getFeatureBits()[AMDGPU::FeatureWavefrontSize32] && isSCSrcB32());
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auto FB = AsmParser->getFeatureBits();
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return isReg() && ((FB[AMDGPU::FeatureWavefrontSize64] && isSCSrcB64()) ||
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(FB[AMDGPU::FeatureWavefrontSize32] && isSCSrcB32()));
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}
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uint64_t AMDGPUOperand::applyInputFPModifiers(uint64_t Val, unsigned Size) const
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@ -273,3 +273,27 @@ s_endpgm_saved
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v_mov_b32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7]
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// GFX6-7: error: dpp variant of this instruction is not supported
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// GFX8-9: error: not a valid operand
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//===----------------------------------------------------------------------===//
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// VOP2 E64.
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//===----------------------------------------------------------------------===//
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v_add_co_ci_u32 v5, 0, v1, v2, vcc
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// GFX6-7: error: instruction not supported on this GPU
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// GFX8-9: error: instruction not supported on this GPU
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// GFX10: error: invalid operand for instruction
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v_add_co_ci_u32 v5, vcc, v1, v2, 0
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// GFX6-7: error: instruction not supported on this GPU
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// GFX8-9: error: instruction not supported on this GPU
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// GFX10: error: invalid operand for instruction
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v_add_co_ci_u32 v5, 0, v1, v2, vcc_lo
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// GFX6-7: error: instruction not supported on this GPU
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// GFX8-9: error: instruction not supported on this GPU
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// GFX10: error: invalid operand for instruction
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v_add_co_ci_u32 v5, vcc_lo, v1, v2, 0
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// GFX6-7: error: instruction not supported on this GPU
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// GFX8-9: error: instruction not supported on this GPU
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// GFX10: error: invalid operand for instruction
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@ -56,9 +56,21 @@ v_addc_u32_e32 v1, vcc, v2, v3, s0
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v_addc_u32_e32 v1, -1, v2, v3, s0
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// CHECK: error: invalid operand for instruction
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v_addc_u32 v1, -1, v2, v3, vcc
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// CHECK: error: invalid operand for instruction
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v_addc_u32 v1, vcc, v2, v3, 0
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// CHECK: error: invalid operand for instruction
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v_addc_u32_e64 v1, s[0:1], v2, v3, 123
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// CHECK: error: invalid operand for instruction
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v_addc_u32_e64 v1, 0, v2, v3, s[0:1]
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// CHECK: error: invalid operand for instruction
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v_addc_u32_e64 v1, s[0:1], v2, v3, 0
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// CHECK: error: invalid operand for instruction
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v_addc_u32 v1, s[0:1], v2, v3, 123
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// CHECK: error: invalid operand for instruction
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