forked from OSchip/llvm-project
[X86] Use X86ISD::VFPROUND instead of ISD::FP_ROUND for 256 and 512 bit cvtpd2ps intrinsics.
Summary: Use X86ISD::VFPROUND in the instruction isel patterns. Add new patterns for ISD::FP_ROUND to maintain support for fptrunc in IR. In the process I found a couple duplicate isel patterns which I also deleted in this patch. Reviewers: RKSimon, spatel Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D56991 llvm-svn: 351762
This commit is contained in:
Craig Topper
parent
c2087d8f3f
commit
bcbdf61078
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@ -21881,35 +21881,6 @@ SDValue X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
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// first.
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return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(),
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Op.getOperand(2), Op.getOperand(3), Op.getOperand(1));
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case CVTPD2PS:
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// ISD::FP_ROUND has a second argument that indicates if the truncation
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// does not change the value. Set it to 0 since it can change.
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return DAG.getNode(IntrData->Opc0, dl, VT, Op.getOperand(1),
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DAG.getIntPtrConstant(0, dl));
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case CVTPD2PS_RND_MASK: {
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SDValue Src = Op.getOperand(1);
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SDValue PassThru = Op.getOperand(2);
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SDValue Mask = Op.getOperand(3);
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// We add rounding mode to the Node when
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// - RM Opcode is specified and
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// - RM is not "current direction".
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unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
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if (IntrWithRoundingModeOpcode != 0) {
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SDValue Rnd = Op.getOperand(4);
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if (!isRoundModeCurDirection(Rnd)) {
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return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
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dl, Op.getValueType(),
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Src, Rnd),
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Mask, PassThru, Subtarget, DAG);
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}
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}
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assert(IntrData->Opc0 == ISD::FP_ROUND && "Unexpected opcode!");
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// ISD::FP_ROUND has a second argument that indicates if the truncation
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// does not change the value. Set it to 0 since it can change.
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return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
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DAG.getIntPtrConstant(0, dl)),
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Mask, PassThru, Subtarget, DAG);
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}
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case FPCLASSS: {
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SDValue Src1 = Op.getOperand(1);
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SDValue Imm = Op.getOperand(2);
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@ -8092,7 +8092,7 @@ multiclass avx512_cvtps2pd<bits<8> opc, string OpcodeStr,
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// Truncate Double to Float
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multiclass avx512_cvtpd2ps<bits<8> opc, string OpcodeStr, X86SchedWriteWidths sched> {
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let Predicates = [HasAVX512] in {
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defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8f64_info, fpround, sched.ZMM>,
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defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8f64_info, X86vfpround, sched.ZMM>,
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avx512_vcvt_fp_rc<opc, OpcodeStr, v8f32x_info, v8f64_info,
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X86vfproundRnd, sched.ZMM>, EVEX_V512;
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}
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@ -8100,7 +8100,7 @@ multiclass avx512_cvtpd2ps<bits<8> opc, string OpcodeStr, X86SchedWriteWidths sc
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defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v2f64x_info,
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null_frag, sched.XMM, "{1to2}", "{x}", f128mem, VK2WM>,
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EVEX_V128;
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defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4f64x_info, fpround,
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defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4f64x_info, X86vfpround,
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sched.YMM, "{1to4}", "{y}">, EVEX_V256;
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def : InstAlias<OpcodeStr##"x\t{$src, $dst|$dst, $src}",
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@ -8119,10 +8119,70 @@ defm VCVTPD2PS : avx512_cvtpd2ps<0x5A, "vcvtpd2ps", SchedWriteCvtPD2PS>,
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defm VCVTPS2PD : avx512_cvtps2pd<0x5A, "vcvtps2pd", SchedWriteCvtPS2PD>,
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PS, EVEX_CD8<32, CD8VH>;
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def : Pat<(v8f64 (extloadv8f32 addr:$src)),
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(VCVTPS2PDZrm addr:$src)>;
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let Predicates = [HasAVX512] in {
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def : Pat<(v8f32 (fpround (v8f64 VR512:$src))),
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(VCVTPD2PSZrr VR512:$src)>;
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def : Pat<(vselect VK8WM:$mask, (v8f32 (fpround (v8f64 VR512:$src))),
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VR256X:$src0),
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(VCVTPD2PSZrrk VR256X:$src0, VK8WM:$mask, VR512:$src)>;
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def : Pat<(vselect VK8WM:$mask, (v8f32 (fpround (v8f64 VR512:$src))),
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v8f32x_info.ImmAllZerosV),
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(VCVTPD2PSZrrkz VK8WM:$mask, VR512:$src)>;
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def : Pat<(v8f32 (fpround (loadv8f64 addr:$src))),
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(VCVTPD2PSZrm addr:$src)>;
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def : Pat<(vselect VK8WM:$mask, (v8f32 (fpround (loadv8f64 addr:$src))),
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VR256X:$src0),
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(VCVTPD2PSZrmk VR256X:$src0, VK8WM:$mask, addr:$src)>;
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def : Pat<(vselect VK8WM:$mask, (v8f32 (fpround (loadv8f64 addr:$src))),
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v8f32x_info.ImmAllZerosV),
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(VCVTPD2PSZrmkz VK8WM:$mask, addr:$src)>;
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def : Pat<(v8f32 (fpround (v8f64 (X86VBroadcast (loadf64 addr:$src))))),
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(VCVTPD2PSZrmb addr:$src)>;
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def : Pat<(vselect VK8WM:$mask,
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(fpround (v8f64 (X86VBroadcast (loadf64 addr:$src)))),
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(v8f32 VR256X:$src0)),
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(VCVTPD2PSZrmbk VR256X:$src0, VK8WM:$mask, addr:$src)>;
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def : Pat<(vselect VK8WM:$mask,
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(fpround (v8f64 (X86VBroadcast (loadf64 addr:$src)))),
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v8f32x_info.ImmAllZerosV),
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(VCVTPD2PSZrmbkz VK8WM:$mask, addr:$src)>;
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def : Pat<(v8f64 (extloadv8f32 addr:$src)),
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(VCVTPS2PDZrm addr:$src)>;
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}
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let Predicates = [HasVLX] in {
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def : Pat<(v4f32 (fpround (v4f64 VR256X:$src))),
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(VCVTPD2PSZ256rr VR256X:$src)>;
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def : Pat<(vselect VK4WM:$mask, (v4f32 (fpround (v4f64 VR256X:$src))),
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VR128X:$src0),
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(VCVTPD2PSZ256rrk VR128X:$src0, VK4WM:$mask, VR256X:$src)>;
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def : Pat<(vselect VK4WM:$mask, (v4f32 (fpround (v4f64 VR256X:$src))),
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v4f32x_info.ImmAllZerosV),
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(VCVTPD2PSZ256rrkz VK4WM:$mask, VR256X:$src)>;
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def : Pat<(v4f32 (fpround (loadv4f64 addr:$src))),
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(VCVTPD2PSZ256rm addr:$src)>;
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def : Pat<(vselect VK4WM:$mask, (v4f32 (fpround (loadv4f64 addr:$src))),
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VR128X:$src0),
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(VCVTPD2PSZ256rmk VR128X:$src0, VK4WM:$mask, addr:$src)>;
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def : Pat<(vselect VK4WM:$mask, (v4f32 (fpround (loadv4f64 addr:$src))),
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v4f32x_info.ImmAllZerosV),
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(VCVTPD2PSZ256rmkz VK4WM:$mask, addr:$src)>;
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def : Pat<(v4f32 (fpround (v4f64 (X86VBroadcast (loadf64 addr:$src))))),
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(VCVTPD2PSZ256rmb addr:$src)>;
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def : Pat<(vselect VK4WM:$mask,
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(v4f32 (fpround (v4f64 (X86VBroadcast (loadf64 addr:$src))))),
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VR128X:$src0),
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(VCVTPD2PSZ256rmbk VR128X:$src0, VK4WM:$mask, addr:$src)>;
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def : Pat<(vselect VK4WM:$mask,
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(v4f32 (fpround (v4f64 (X86VBroadcast (loadf64 addr:$src))))),
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v4f32x_info.ImmAllZerosV),
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(VCVTPD2PSZ256rmbkz VK4WM:$mask, addr:$src)>;
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def : Pat<(X86vzmovl (v2f64 (bitconvert
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(v4f32 (X86vfpround (v2f64 VR128X:$src)))))),
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(VCVTPD2PSZ128rr VR128X:$src)>;
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@ -8800,13 +8860,6 @@ let Predicates = [HasAVX512, HasVLX] in {
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(VCVTUDQ2PDZ128rm addr:$src)>;
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}
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let Predicates = [HasAVX512] in {
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def : Pat<(v8f32 (fpround (loadv8f64 addr:$src))),
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(VCVTPD2PSZrm addr:$src)>;
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def : Pat<(v8f64 (extloadv8f32 addr:$src)),
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(VCVTPS2PDZrm addr:$src)>;
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}
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let Predicates = [HasDQI, HasVLX] in {
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def : Pat<(X86vzmovl (v2f64 (bitconvert
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(v4f32 (X86VSintToFP (v2i64 VR128X:$src)))))),
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@ -126,7 +126,7 @@ def X86vfpext : SDNode<"X86ISD::VFPEXT",
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def X86vfpround: SDNode<"X86ISD::VFPROUND",
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SDTypeProfile<1, 1, [SDTCVecEltisVT<0, f32>,
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SDTCVecEltisVT<1, f64>,
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SDTCisSameSizeAs<0, 1>]>>;
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SDTCisOpSmallerThanOp<0, 1>]>>;
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def X86froundRnd: SDNode<"X86ISD::VFPROUNDS_RND",
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SDTypeProfile<1, 3, [SDTCVecEltisVT<0, f32>,
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@ -1769,11 +1769,11 @@ def : InstAlias<"vcvtpd2psx\t{$src, $dst|$dst, $src}",
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let Predicates = [HasAVX, NoVLX] in {
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def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
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"cvtpd2ps\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (fpround VR256:$src))]>,
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[(set VR128:$dst, (X86vfpround VR256:$src))]>,
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VEX, VEX_L, Sched<[WriteCvtPD2PSY]>, VEX_WIG;
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def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
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"cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (fpround (loadv4f64 addr:$src)))]>,
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[(set VR128:$dst, (X86vfpround (loadv4f64 addr:$src)))]>,
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VEX, VEX_L, Sched<[WriteCvtPD2PSY.Folded]>, VEX_WIG;
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}
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def : InstAlias<"vcvtpd2psy\t{$src, $dst|$dst, $src}",
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@ -1795,6 +1795,11 @@ def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
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// whenever possible to avoid declaring two versions of each one.
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let Predicates = [HasAVX, NoVLX] in {
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def : Pat<(v4f32 (fpround (v4f64 VR256:$src))),
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(VCVTPD2PSYrr VR256:$src)>;
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def : Pat<(v4f32 (fpround (loadv4f64 addr:$src))),
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(VCVTPD2PSYrm addr:$src)>;
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// Match fpround and fpextend for 128/256-bit conversions
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def : Pat<(X86vzmovl (v2f64 (bitconvert
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(v4f32 (X86vfpround (v2f64 VR128:$src)))))),
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@ -23,7 +23,7 @@ enum IntrinsicType : uint16_t {
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INTR_TYPE_1OP, INTR_TYPE_2OP, INTR_TYPE_3OP, INTR_TYPE_4OP,
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INTR_TYPE_3OP_IMM8,
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CMP_MASK_CC,CMP_MASK_SCALAR_CC, VSHIFT, COMI, COMI_RM, BLENDV,
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CVTPD2PS, CVTPD2PS_MASK, CVTPD2PS_RND_MASK,
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CVTPD2PS_MASK,
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INTR_TYPE_1OP_MASK, INTR_TYPE_1OP_MASK_RM,
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INTR_TYPE_2OP_MASK, INTR_TYPE_2OP_MASK_RM,
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INTR_TYPE_3OP_MASK,
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@ -343,7 +343,7 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
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X86_INTRINSIC_DATA(avx_blendv_ps_256, BLENDV, X86ISD::BLENDV, 0),
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X86_INTRINSIC_DATA(avx_cmp_pd_256, INTR_TYPE_3OP, X86ISD::CMPP, 0),
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X86_INTRINSIC_DATA(avx_cmp_ps_256, INTR_TYPE_3OP, X86ISD::CMPP, 0),
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X86_INTRINSIC_DATA(avx_cvt_pd2_ps_256,CVTPD2PS, ISD::FP_ROUND, 0),
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X86_INTRINSIC_DATA(avx_cvt_pd2_ps_256,INTR_TYPE_1OP, X86ISD::VFPROUND, 0),
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X86_INTRINSIC_DATA(avx_cvt_pd2dq_256, INTR_TYPE_1OP, X86ISD::CVTP2SI, 0),
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X86_INTRINSIC_DATA(avx_cvt_ps2dq_256, INTR_TYPE_1OP, X86ISD::CVTP2SI, 0),
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X86_INTRINSIC_DATA(avx_cvtt_pd2dq_256,INTR_TYPE_1OP, X86ISD::CVTTP2SI, 0),
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@ -515,8 +515,8 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
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X86ISD::CVTP2SI, X86ISD::CVTP2SI_RND),
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X86_INTRINSIC_DATA(avx512_mask_cvtpd2ps, CVTPD2PS_MASK,
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X86ISD::VFPROUND, X86ISD::VMFPROUND),
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X86_INTRINSIC_DATA(avx512_mask_cvtpd2ps_512, CVTPD2PS_RND_MASK,
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ISD::FP_ROUND, X86ISD::VFPROUND_RND),
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X86_INTRINSIC_DATA(avx512_mask_cvtpd2ps_512, INTR_TYPE_1OP_MASK,
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X86ISD::VFPROUND, X86ISD::VFPROUND_RND),
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X86_INTRINSIC_DATA(avx512_mask_cvtpd2qq_128, INTR_TYPE_1OP_MASK,
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X86ISD::CVTP2SI, 0),
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X86_INTRINSIC_DATA(avx512_mask_cvtpd2qq_256, INTR_TYPE_1OP_MASK,
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