forked from OSchip/llvm-project
[libomptarget] Fix devicertl build
[libomptarget] Fix devicertl build The target specific functions in target_interface are extern C, but the implementations for nvptx were mostly C++ mangling. That worked out as a quirk of DEVICE macro expanding to nothing, except for shuffle.h which only forward declared the functions with C++ linkage. Also implements GetWarpSize, as used by shuffle, and includes target_interface in nvptx target_impl.cu to help catch future divergence between interface and implementation. Reviewed By: jdoerfert Differential Revision: https://reviews.llvm.org/D98651
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@ -130,6 +130,7 @@ EXTERN int GetNumberOfThreadsInBlock() {
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}
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EXTERN unsigned GetWarpId() { return GetThreadIdInBlock() / WARPSIZE; }
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EXTERN unsigned GetWarpSize() { return WARPSIZE; }
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EXTERN unsigned GetLaneId() {
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return __builtin_amdgcn_mbcnt_hi(~0u, __builtin_amdgcn_mbcnt_lo(~0u, 0u));
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}
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@ -33,10 +33,12 @@ int64_t __kmpc_shuffle_int64(int64_t val, int16_t delta, int16_t size);
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/// Forward declarations
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///
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///{
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extern "C" {
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unsigned GetLaneId();
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unsigned GetWarpSize();
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void __kmpc_impl_unpack(uint64_t val, uint32_t &lo, uint32_t &hi);
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uint64_t __kmpc_impl_pack(uint32_t lo, uint32_t hi);
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}
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///}
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/// Fallback implementations of the shuffle sync idiom.
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@ -13,64 +13,65 @@
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#include "common/debug.h"
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#include "target_impl.h"
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#include "target_interface.h"
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DEVICE void __kmpc_impl_unpack(uint64_t val, uint32_t &lo, uint32_t &hi) {
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EXTERN void __kmpc_impl_unpack(uint64_t val, uint32_t &lo, uint32_t &hi) {
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asm volatile("mov.b64 {%0,%1}, %2;" : "=r"(lo), "=r"(hi) : "l"(val));
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}
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DEVICE uint64_t __kmpc_impl_pack(uint32_t lo, uint32_t hi) {
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EXTERN uint64_t __kmpc_impl_pack(uint32_t lo, uint32_t hi) {
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uint64_t val;
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asm volatile("mov.b64 %0, {%1,%2};" : "=l"(val) : "r"(lo), "r"(hi));
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return val;
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}
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DEVICE __kmpc_impl_lanemask_t __kmpc_impl_lanemask_lt() {
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EXTERN __kmpc_impl_lanemask_t __kmpc_impl_lanemask_lt() {
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__kmpc_impl_lanemask_t res;
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asm("mov.u32 %0, %%lanemask_lt;" : "=r"(res));
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return res;
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}
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DEVICE __kmpc_impl_lanemask_t __kmpc_impl_lanemask_gt() {
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EXTERN __kmpc_impl_lanemask_t __kmpc_impl_lanemask_gt() {
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__kmpc_impl_lanemask_t res;
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asm("mov.u32 %0, %%lanemask_gt;" : "=r"(res));
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return res;
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}
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DEVICE uint32_t __kmpc_impl_smid() {
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EXTERN uint32_t __kmpc_impl_smid() {
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uint32_t id;
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asm("mov.u32 %0, %%smid;" : "=r"(id));
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return id;
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}
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DEVICE double __kmpc_impl_get_wtick() {
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EXTERN double __kmpc_impl_get_wtick() {
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// Timer precision is 1ns
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return ((double)1E-9);
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}
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DEVICE double __kmpc_impl_get_wtime() {
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EXTERN double __kmpc_impl_get_wtime() {
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unsigned long long nsecs;
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asm("mov.u64 %0, %%globaltimer;" : "=l"(nsecs));
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return (double)nsecs * __kmpc_impl_get_wtick();
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}
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DEVICE __kmpc_impl_lanemask_t __kmpc_impl_activemask() {
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EXTERN __kmpc_impl_lanemask_t __kmpc_impl_activemask() {
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unsigned int Mask;
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asm volatile("activemask.b32 %0;" : "=r"(Mask));
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return Mask;
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}
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DEVICE void __kmpc_impl_syncthreads() { __syncthreads(); }
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EXTERN void __kmpc_impl_syncthreads() { __syncthreads(); }
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DEVICE void __kmpc_impl_syncwarp(__kmpc_impl_lanemask_t Mask) {
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EXTERN void __kmpc_impl_syncwarp(__kmpc_impl_lanemask_t Mask) {
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__nvvm_bar_warp_sync(Mask);
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}
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// NVPTX specific kernel initialization
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DEVICE void __kmpc_impl_target_init() { /* nvptx needs no extra setup */
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EXTERN void __kmpc_impl_target_init() { /* nvptx needs no extra setup */
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}
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// Barrier until num_threads arrive.
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DEVICE void __kmpc_impl_named_sync(uint32_t num_threads) {
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EXTERN void __kmpc_impl_named_sync(uint32_t num_threads) {
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// The named barrier for active parallel threads of a team in an L1 parallel
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// region to synchronize with each other.
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int barrier = 1;
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@ -80,19 +81,20 @@ DEVICE void __kmpc_impl_named_sync(uint32_t num_threads) {
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: "memory");
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}
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DEVICE void __kmpc_impl_threadfence() { __nvvm_membar_gl(); }
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DEVICE void __kmpc_impl_threadfence_block() { __nvvm_membar_cta(); }
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DEVICE void __kmpc_impl_threadfence_system() { __nvvm_membar_sys(); }
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EXTERN void __kmpc_impl_threadfence() { __nvvm_membar_gl(); }
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EXTERN void __kmpc_impl_threadfence_block() { __nvvm_membar_cta(); }
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EXTERN void __kmpc_impl_threadfence_system() { __nvvm_membar_sys(); }
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// Calls to the NVPTX layer (assuming 1D layout)
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DEVICE int GetThreadIdInBlock() { return __nvvm_read_ptx_sreg_tid_x(); }
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DEVICE int GetBlockIdInKernel() { return __nvvm_read_ptx_sreg_ctaid_x(); }
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DEVICE int GetNumberOfBlocksInKernel() {
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EXTERN int GetThreadIdInBlock() { return __nvvm_read_ptx_sreg_tid_x(); }
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EXTERN int GetBlockIdInKernel() { return __nvvm_read_ptx_sreg_ctaid_x(); }
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EXTERN int GetNumberOfBlocksInKernel() {
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return __nvvm_read_ptx_sreg_nctaid_x();
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}
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DEVICE int GetNumberOfThreadsInBlock() { return __nvvm_read_ptx_sreg_ntid_x(); }
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DEVICE unsigned GetWarpId() { return GetThreadIdInBlock() / WARPSIZE; }
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DEVICE unsigned GetLaneId() { return GetThreadIdInBlock() & (WARPSIZE - 1); }
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EXTERN int GetNumberOfThreadsInBlock() { return __nvvm_read_ptx_sreg_ntid_x(); }
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EXTERN unsigned GetWarpId() { return GetThreadIdInBlock() / WARPSIZE; }
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EXTERN unsigned GetWarpSize() { return WARPSIZE; }
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EXTERN unsigned GetLaneId() { return GetThreadIdInBlock() & (WARPSIZE - 1); }
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// Atomics
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DEVICE uint32_t __kmpc_atomic_add(uint32_t *Address, uint32_t Val) {
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@ -135,15 +137,15 @@ DEVICE unsigned long long __kmpc_atomic_add(unsigned long long *Address,
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#define UNSET 0u
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#define SET 1u
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DEVICE void __kmpc_impl_init_lock(omp_lock_t *lock) {
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EXTERN void __kmpc_impl_init_lock(omp_lock_t *lock) {
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__kmpc_impl_unset_lock(lock);
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}
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DEVICE void __kmpc_impl_destroy_lock(omp_lock_t *lock) {
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EXTERN void __kmpc_impl_destroy_lock(omp_lock_t *lock) {
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__kmpc_impl_unset_lock(lock);
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}
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DEVICE void __kmpc_impl_set_lock(omp_lock_t *lock) {
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EXTERN void __kmpc_impl_set_lock(omp_lock_t *lock) {
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// TODO: not sure spinning is a good idea here..
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while (__kmpc_atomic_cas(lock, UNSET, SET) != UNSET) {
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int32_t start = __nvvm_read_ptx_sreg_clock();
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@ -158,15 +160,15 @@ DEVICE void __kmpc_impl_set_lock(omp_lock_t *lock) {
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} // wait for 0 to be the read value
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}
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DEVICE void __kmpc_impl_unset_lock(omp_lock_t *lock) {
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EXTERN void __kmpc_impl_unset_lock(omp_lock_t *lock) {
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(void)__kmpc_atomic_exchange(lock, UNSET);
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}
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DEVICE int __kmpc_impl_test_lock(omp_lock_t *lock) {
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EXTERN int __kmpc_impl_test_lock(omp_lock_t *lock) {
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return __kmpc_atomic_add(lock, 0u);
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}
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DEVICE void *__kmpc_impl_malloc(size_t x) { return malloc(x); }
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DEVICE void __kmpc_impl_free(void *x) { free(x); }
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EXTERN void *__kmpc_impl_malloc(size_t x) { return malloc(x); }
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EXTERN void __kmpc_impl_free(void *x) { free(x); }
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#pragma omp end declare target
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@ -21,19 +21,20 @@ EXTERN int GetBlockIdInKernel();
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EXTERN int GetNumberOfBlocksInKernel();
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EXTERN int GetNumberOfThreadsInBlock();
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EXTERN unsigned GetWarpId();
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EXTERN unsigned GetWarpSize();
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EXTERN unsigned GetLaneId();
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// Atomics
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extern DEVICE uint32_t __kmpc_atomic_add(uint32_t *, uint32_t);
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extern DEVICE uint32_t __kmpc_atomic_inc(uint32_t *, uint32_t);
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extern DEVICE uint32_t __kmpc_atomic_max(uint32_t *, uint32_t);
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extern DEVICE uint32_t __kmpc_atomic_exchange(uint32_t *, uint32_t);
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extern DEVICE uint32_t __kmpc_atomic_cas(uint32_t *, uint32_t, uint32_t);
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DEVICE uint32_t __kmpc_atomic_add(uint32_t *, uint32_t);
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DEVICE uint32_t __kmpc_atomic_inc(uint32_t *, uint32_t);
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DEVICE uint32_t __kmpc_atomic_max(uint32_t *, uint32_t);
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DEVICE uint32_t __kmpc_atomic_exchange(uint32_t *, uint32_t);
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DEVICE uint32_t __kmpc_atomic_cas(uint32_t *, uint32_t, uint32_t);
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static_assert(sizeof(unsigned long long) == sizeof(uint64_t), "");
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extern DEVICE unsigned long long __kmpc_atomic_exchange(unsigned long long *,
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unsigned long long);
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extern DEVICE unsigned long long __kmpc_atomic_add(unsigned long long *,
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unsigned long long);
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DEVICE unsigned long long __kmpc_atomic_exchange(unsigned long long *,
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unsigned long long);
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DEVICE unsigned long long __kmpc_atomic_add(unsigned long long *,
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unsigned long long);
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// Locks
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EXTERN void __kmpc_impl_init_lock(omp_lock_t *lock);
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