forked from OSchip/llvm-project
Enable partial libcall inlining for all targets by default.
This pass attempts to speculatively use a sqrt instruction if one exists on the target, falling back to a libcall if the target instruction returned NaN. This was enabled for MIPS and System-Z, but is well guarded and is good for most targets - GCC does this for (that I've checked) X86, ARM and AArch64. llvm-svn: 213752
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@ -71,6 +71,8 @@ static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
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cl::desc("Disable Codegen Prepare"));
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static cl::opt<bool> DisableCopyProp("disable-copyprop", cl::Hidden,
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cl::desc("Disable Copy Propagation pass"));
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static cl::opt<bool> DisablePartialLibcallInlining("disable-partial-libcall-inlining",
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cl::Hidden, cl::desc("Disable Partial Libcall Inlining"));
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static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
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cl::desc("Print LLVM IR produced by the loop-reduce pass"));
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static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
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@ -399,6 +401,9 @@ void TargetPassConfig::addIRPasses() {
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// Prepare expensive constants for SelectionDAG.
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if (getOptLevel() != CodeGenOpt::None && !DisableConstantHoisting)
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addPass(createConstantHoistingPass());
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if (getOptLevel() != CodeGenOpt::None && !DisablePartialLibcallInlining)
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addPass(createPartiallyInlineLibCallsPass());
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}
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/// Turn exception handling constructs into something the code generators can
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@ -141,7 +141,6 @@ void MipsPassConfig::addIRPasses() {
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addPass(createMipsOs16(getMipsTargetMachine()));
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if (getMipsSubtarget().inMips16HardFloat())
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addPass(createMips16HardFloat(getMipsTargetMachine()));
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addPass(createPartiallyInlineLibCallsPass());
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}
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// Install an instruction selector pass using
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// the ISelDag to gen Mips code.
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@ -49,7 +49,6 @@ public:
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void SystemZPassConfig::addIRPasses() {
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TargetPassConfig::addIRPasses();
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addPass(createPartiallyInlineLibCallsPass());
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}
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bool SystemZPassConfig::addInstSelector() {
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