forked from OSchip/llvm-project
[NFC][PowerPC] Style and ordering changes for PPCInstrP10.td
Renamed the two classes 8LS_DForm_R_SI34_RTA5 and 8LS_DForm_R_SI34_XT6_RA5 to 8LS_DForm_R_SI34_RTA5_MEM and 8LS_DForm_R_SI34_XT6_RA5_MEM because the instructions that use the classes use memory reads/writes. Moved the instruction defs up closer to the classes. Removed unnecessary whitespace.
This commit is contained in:
Stefan Pintilie
parent
21b251624b
commit
bc9916fff2
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@ -254,8 +254,8 @@ multiclass MLS_DForm_R_SI34_RTA5_p<bits<6> opcode, dag OOL, dag IOL,
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!strconcat(asmstr, ", 1"), itin, []>, isPCRel;
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}
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class 8LS_DForm_R_SI34_RTA5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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class 8LS_DForm_R_SI34_RTA5_MEM<bits<6> opcode, dag OOL, dag IOL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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: PI<1, opcode, OOL, IOL, asmstr, itin> {
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bits<5> RT;
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bits<39> D_RA;
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@ -276,8 +276,9 @@ class 8LS_DForm_R_SI34_RTA5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
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// 8LS:D-Form: [ 1 0 0 // R // d0
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// PO TX T RA d1 ]
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class 8LS_DForm_R_SI34_XT6_RA5<bits<5> opcode, dag OOL, dag IOL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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class 8LS_DForm_R_SI34_XT6_RA5_MEM<bits<5> opcode, dag OOL, dag IOL,
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string asmstr, InstrItinClass itin,
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list<dag> pattern>
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: PI<1, { opcode, ? }, OOL, IOL, asmstr, itin> {
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bits<6> XT;
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bits<39> D_RA;
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@ -578,23 +579,189 @@ multiclass MLS_DForm_R_SI34_RTA5_MEM_p<bits<6> opcode, dag OOL, dag IOL,
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isPCRel;
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}
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multiclass 8LS_DForm_R_SI34_RTA5_p<bits<6> opcode, dag OOL, dag IOL,
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dag PCRel_IOL, string asmstr,
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InstrItinClass itin> {
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def NAME : 8LS_DForm_R_SI34_RTA5<opcode, OOL, IOL,
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!strconcat(asmstr, ", 0"), itin, []>;
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def pc : 8LS_DForm_R_SI34_RTA5<opcode, OOL, PCRel_IOL,
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!strconcat(asmstr, ", 1"), itin, []>, isPCRel;
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multiclass 8LS_DForm_R_SI34_RTA5_MEM_p<bits<6> opcode, dag OOL, dag IOL,
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dag PCRel_IOL, string asmstr,
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InstrItinClass itin> {
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def NAME : 8LS_DForm_R_SI34_RTA5_MEM<opcode, OOL, IOL,
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!strconcat(asmstr, ", 0"), itin, []>;
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def pc : 8LS_DForm_R_SI34_RTA5_MEM<opcode, OOL, PCRel_IOL,
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!strconcat(asmstr, ", 1"), itin, []>,
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isPCRel;
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}
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multiclass 8LS_DForm_R_SI34_XT6_RA5_p<bits<5> opcode, dag OOL, dag IOL,
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dag PCRel_IOL, string asmstr,
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InstrItinClass itin> {
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def NAME : 8LS_DForm_R_SI34_XT6_RA5<opcode, OOL, IOL,
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!strconcat(asmstr, ", 0"), itin, []>;
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def pc : 8LS_DForm_R_SI34_XT6_RA5<opcode, OOL, PCRel_IOL,
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!strconcat(asmstr, ", 1"), itin, []>,
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isPCRel;
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multiclass 8LS_DForm_R_SI34_XT6_RA5_MEM_p<bits<5> opcode, dag OOL, dag IOL,
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dag PCRel_IOL, string asmstr,
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InstrItinClass itin> {
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def NAME : 8LS_DForm_R_SI34_XT6_RA5_MEM<opcode, OOL, IOL,
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!strconcat(asmstr, ", 0"), itin, []>;
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def pc : 8LS_DForm_R_SI34_XT6_RA5_MEM<opcode, OOL, PCRel_IOL,
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!strconcat(asmstr, ", 1"), itin, []>,
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isPCRel;
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}
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def PrefixInstrs : Predicate<"Subtarget->hasPrefixInstrs()">;
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def IsISA3_1 : Predicate<"Subtarget->isISA3_1()">;
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def PairedVectorMemops : Predicate<"Subtarget->pairedVectorMemops()">;
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def RCCp {
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dag AToVSRC = (COPY_TO_REGCLASS $XA, VSRC);
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dag BToVSRC = (COPY_TO_REGCLASS $XB, VSRC);
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}
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let Predicates = [PrefixInstrs] in {
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let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
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defm PADDI8 :
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MLS_DForm_R_SI34_RTA5_p<14, (outs g8rc:$RT), (ins g8rc:$RA, s34imm:$SI),
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(ins immZero:$RA, s34imm_pcrel:$SI),
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"paddi $RT, $RA, $SI", IIC_LdStLFD>;
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let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
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def PLI8 : MLS_DForm_SI34_RT5<14, (outs g8rc:$RT),
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(ins s34imm:$SI),
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"pli $RT, $SI", IIC_IntSimple, []>;
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}
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}
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defm PADDI :
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MLS_DForm_R_SI34_RTA5_p<14, (outs gprc:$RT), (ins gprc:$RA, s34imm:$SI),
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(ins immZero:$RA, s34imm_pcrel:$SI),
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"paddi $RT, $RA, $SI", IIC_LdStLFD>;
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let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
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def PLI : MLS_DForm_SI34_RT5<14, (outs gprc:$RT),
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(ins s34imm:$SI),
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"pli $RT, $SI", IIC_IntSimple, []>;
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}
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let mayLoad = 1, mayStore = 0 in {
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defm PLXV :
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8LS_DForm_R_SI34_XT6_RA5_MEM_p<25, (outs vsrc:$XT), (ins memri34:$D_RA),
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(ins memri34_pcrel:$D_RA),
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"plxv $XT, $D_RA", IIC_LdStLFD>;
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defm PLFS :
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MLS_DForm_R_SI34_RTA5_MEM_p<48, (outs f4rc:$FRT), (ins memri34:$D_RA),
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(ins memri34_pcrel:$D_RA), "plfs $FRT, $D_RA",
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IIC_LdStLFD>;
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defm PLFD :
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MLS_DForm_R_SI34_RTA5_MEM_p<50, (outs f8rc:$FRT), (ins memri34:$D_RA),
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(ins memri34_pcrel:$D_RA), "plfd $FRT, $D_RA",
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IIC_LdStLFD>;
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defm PLXSSP :
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8LS_DForm_R_SI34_RTA5_MEM_p<43, (outs vfrc:$VRT), (ins memri34:$D_RA),
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(ins memri34_pcrel:$D_RA),
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"plxssp $VRT, $D_RA", IIC_LdStLFD>;
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defm PLXSD :
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8LS_DForm_R_SI34_RTA5_MEM_p<42, (outs vfrc:$VRT), (ins memri34:$D_RA),
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(ins memri34_pcrel:$D_RA),
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"plxsd $VRT, $D_RA", IIC_LdStLFD>;
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let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
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defm PLBZ8 :
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MLS_DForm_R_SI34_RTA5_MEM_p<34, (outs g8rc:$RT), (ins memri34:$D_RA),
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(ins memri34_pcrel:$D_RA), "plbz $RT, $D_RA",
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IIC_LdStLFD>;
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defm PLHZ8 :
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MLS_DForm_R_SI34_RTA5_MEM_p<40, (outs g8rc:$RT), (ins memri34:$D_RA),
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(ins memri34_pcrel:$D_RA), "plhz $RT, $D_RA",
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IIC_LdStLFD>;
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defm PLHA8 :
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MLS_DForm_R_SI34_RTA5_MEM_p<42, (outs g8rc:$RT), (ins memri34:$D_RA),
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(ins memri34_pcrel:$D_RA), "plha $RT, $D_RA",
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IIC_LdStLFD>;
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defm PLWA8 :
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8LS_DForm_R_SI34_RTA5_MEM_p<41, (outs g8rc:$RT), (ins memri34:$D_RA),
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(ins memri34_pcrel:$D_RA),
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"plwa $RT, $D_RA", IIC_LdStLFD>;
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defm PLWZ8 :
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MLS_DForm_R_SI34_RTA5_MEM_p<32, (outs g8rc:$RT), (ins memri34:$D_RA),
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(ins memri34_pcrel:$D_RA), "plwz $RT, $D_RA",
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IIC_LdStLFD>;
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}
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defm PLBZ :
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MLS_DForm_R_SI34_RTA5_MEM_p<34, (outs gprc:$RT), (ins memri34:$D_RA),
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(ins memri34_pcrel:$D_RA), "plbz $RT, $D_RA",
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IIC_LdStLFD>;
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defm PLHZ :
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MLS_DForm_R_SI34_RTA5_MEM_p<40, (outs gprc:$RT), (ins memri34:$D_RA),
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(ins memri34_pcrel:$D_RA), "plhz $RT, $D_RA",
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IIC_LdStLFD>;
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defm PLHA :
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MLS_DForm_R_SI34_RTA5_MEM_p<42, (outs gprc:$RT), (ins memri34:$D_RA),
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(ins memri34_pcrel:$D_RA), "plha $RT, $D_RA",
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IIC_LdStLFD>;
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defm PLWZ :
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MLS_DForm_R_SI34_RTA5_MEM_p<32, (outs gprc:$RT), (ins memri34:$D_RA),
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(ins memri34_pcrel:$D_RA), "plwz $RT, $D_RA",
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IIC_LdStLFD>;
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defm PLWA :
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8LS_DForm_R_SI34_RTA5_MEM_p<41, (outs gprc:$RT), (ins memri34:$D_RA),
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(ins memri34_pcrel:$D_RA), "plwa $RT, $D_RA",
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IIC_LdStLFD>;
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defm PLD :
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8LS_DForm_R_SI34_RTA5_MEM_p<57, (outs g8rc:$RT), (ins memri34:$D_RA),
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(ins memri34_pcrel:$D_RA), "pld $RT, $D_RA",
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IIC_LdStLFD>;
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}
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let mayStore = 1, mayLoad = 0 in {
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defm PSTXV :
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8LS_DForm_R_SI34_XT6_RA5_MEM_p<27, (outs), (ins vsrc:$XS, memri34:$D_RA),
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(ins vsrc:$XS, memri34_pcrel:$D_RA),
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"pstxv $XS, $D_RA", IIC_LdStLFD>;
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defm PSTFS :
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MLS_DForm_R_SI34_RTA5_MEM_p<52, (outs), (ins f4rc:$FRS, memri34:$D_RA),
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(ins f4rc:$FRS, memri34_pcrel:$D_RA),
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"pstfs $FRS, $D_RA", IIC_LdStLFD>;
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defm PSTFD :
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MLS_DForm_R_SI34_RTA5_MEM_p<54, (outs), (ins f8rc:$FRS, memri34:$D_RA),
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(ins f8rc:$FRS, memri34_pcrel:$D_RA),
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"pstfd $FRS, $D_RA", IIC_LdStLFD>;
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defm PSTXSSP :
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8LS_DForm_R_SI34_RTA5_MEM_p<47, (outs), (ins vfrc:$VRS, memri34:$D_RA),
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(ins vfrc:$VRS, memri34_pcrel:$D_RA),
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"pstxssp $VRS, $D_RA", IIC_LdStLFD>;
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defm PSTXSD :
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8LS_DForm_R_SI34_RTA5_MEM_p<46, (outs), (ins vfrc:$VRS, memri34:$D_RA),
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(ins vfrc:$VRS, memri34_pcrel:$D_RA),
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"pstxsd $VRS, $D_RA", IIC_LdStLFD>;
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let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
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defm PSTB8 :
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MLS_DForm_R_SI34_RTA5_MEM_p<38, (outs), (ins g8rc:$RS, memri34:$D_RA),
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(ins g8rc:$RS, memri34_pcrel:$D_RA),
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"pstb $RS, $D_RA", IIC_LdStLFD>;
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defm PSTH8 :
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MLS_DForm_R_SI34_RTA5_MEM_p<44, (outs), (ins g8rc:$RS, memri34:$D_RA),
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(ins g8rc:$RS, memri34_pcrel:$D_RA),
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"psth $RS, $D_RA", IIC_LdStLFD>;
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defm PSTW8 :
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MLS_DForm_R_SI34_RTA5_MEM_p<36, (outs), (ins g8rc:$RS, memri34:$D_RA),
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(ins g8rc:$RS, memri34_pcrel:$D_RA),
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"pstw $RS, $D_RA", IIC_LdStLFD>;
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}
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defm PSTB :
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MLS_DForm_R_SI34_RTA5_MEM_p<38, (outs), (ins gprc:$RS, memri34:$D_RA),
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(ins gprc:$RS, memri34_pcrel:$D_RA),
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"pstb $RS, $D_RA", IIC_LdStLFD>;
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defm PSTH :
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MLS_DForm_R_SI34_RTA5_MEM_p<44, (outs), (ins gprc:$RS, memri34:$D_RA),
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(ins gprc:$RS, memri34_pcrel:$D_RA),
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"psth $RS, $D_RA", IIC_LdStLFD>;
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defm PSTW :
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MLS_DForm_R_SI34_RTA5_MEM_p<36, (outs), (ins gprc:$RS, memri34:$D_RA),
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(ins gprc:$RS, memri34_pcrel:$D_RA),
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"pstw $RS, $D_RA", IIC_LdStLFD>;
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defm PSTD :
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8LS_DForm_R_SI34_RTA5_MEM_p<61, (outs), (ins g8rc:$RS, memri34:$D_RA),
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(ins g8rc:$RS, memri34_pcrel:$D_RA),
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"pstd $RS, $D_RA", IIC_LdStLFD>;
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}
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}
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def PPCRegACCRCAsmOperand : AsmOperandClass {
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let Name = "RegACCRC"; let PredicateMethod = "isACCRegNumber";
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}
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def acc : RegisterOperand<ACCRC> {
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let ParserMatchClass = PPCRegACCRCAsmOperand;
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}
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def uacc : RegisterOperand<UACCRC> {
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let ParserMatchClass = PPCRegACCRCAsmOperand;
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}
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def PPCRegVSRpRCAsmOperand : AsmOperandClass {
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@ -676,17 +843,7 @@ multiclass 8LS_DForm_R_XTp5_SI34_MEM_p<bits<6> opcode, dag OOL,
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isPCRel;
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}
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def PPCRegACCRCAsmOperand : AsmOperandClass {
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let Name = "RegACCRC"; let PredicateMethod = "isACCRegNumber";
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}
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def acc : RegisterOperand<ACCRC> {
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let ParserMatchClass = PPCRegACCRCAsmOperand;
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}
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def uacc : RegisterOperand<UACCRC> {
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let ParserMatchClass = PPCRegACCRCAsmOperand;
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}
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// [PO AS XO2 XO]
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class XForm_AT3<bits<6> opcode, bits<5> xo2, bits<10> xo, dag OOL, dag IOL,
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@ -899,159 +1056,7 @@ class MMIRR_XX3Form_XYP4_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
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let Inst{63} = 0;
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}
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def PrefixInstrs : Predicate<"Subtarget->hasPrefixInstrs()">;
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def IsISA3_1 : Predicate<"Subtarget->isISA3_1()">;
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def PairedVectorMemops : Predicate<"Subtarget->pairedVectorMemops()">;
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def RCCp {
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dag AToVSRC = (COPY_TO_REGCLASS $XA, VSRC);
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dag BToVSRC = (COPY_TO_REGCLASS $XB, VSRC);
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}
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let Predicates = [PrefixInstrs] in {
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let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
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defm PADDI8 :
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MLS_DForm_R_SI34_RTA5_p<14, (outs g8rc:$RT), (ins g8rc:$RA, s34imm:$SI),
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(ins immZero:$RA, s34imm_pcrel:$SI),
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"paddi $RT, $RA, $SI", IIC_LdStLFD>;
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let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
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def PLI8 : MLS_DForm_SI34_RT5<14, (outs g8rc:$RT),
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(ins s34imm:$SI),
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"pli $RT, $SI", IIC_IntSimple, []>;
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}
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}
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defm PADDI :
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MLS_DForm_R_SI34_RTA5_p<14, (outs gprc:$RT), (ins gprc:$RA, s34imm:$SI),
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(ins immZero:$RA, s34imm_pcrel:$SI),
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"paddi $RT, $RA, $SI", IIC_LdStLFD>;
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let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
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def PLI : MLS_DForm_SI34_RT5<14, (outs gprc:$RT),
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(ins s34imm:$SI),
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"pli $RT, $SI", IIC_IntSimple, []>;
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}
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let mayLoad = 1, mayStore = 0 in {
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defm PLXV :
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8LS_DForm_R_SI34_XT6_RA5_p<25, (outs vsrc:$XT), (ins memri34:$D_RA),
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(ins memri34_pcrel:$D_RA), "plxv $XT, $D_RA",
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IIC_LdStLFD>;
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defm PLFS :
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MLS_DForm_R_SI34_RTA5_MEM_p<48, (outs f4rc:$FRT), (ins memri34:$D_RA),
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(ins memri34_pcrel:$D_RA), "plfs $FRT, $D_RA",
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IIC_LdStLFD>;
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defm PLFD :
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MLS_DForm_R_SI34_RTA5_MEM_p<50, (outs f8rc:$FRT), (ins memri34:$D_RA),
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(ins memri34_pcrel:$D_RA), "plfd $FRT, $D_RA",
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IIC_LdStLFD>;
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defm PLXSSP :
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8LS_DForm_R_SI34_RTA5_p<43, (outs vfrc:$VRT), (ins memri34:$D_RA),
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(ins memri34_pcrel:$D_RA), "plxssp $VRT, $D_RA",
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IIC_LdStLFD>;
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defm PLXSD :
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8LS_DForm_R_SI34_RTA5_p<42, (outs vfrc:$VRT), (ins memri34:$D_RA),
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(ins memri34_pcrel:$D_RA), "plxsd $VRT, $D_RA",
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IIC_LdStLFD>;
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let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
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defm PLBZ8 :
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MLS_DForm_R_SI34_RTA5_MEM_p<34, (outs g8rc:$RT), (ins memri34:$D_RA),
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(ins memri34_pcrel:$D_RA), "plbz $RT, $D_RA",
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IIC_LdStLFD>;
|
||||
defm PLHZ8 :
|
||||
MLS_DForm_R_SI34_RTA5_MEM_p<40, (outs g8rc:$RT), (ins memri34:$D_RA),
|
||||
(ins memri34_pcrel:$D_RA), "plhz $RT, $D_RA",
|
||||
IIC_LdStLFD>;
|
||||
defm PLHA8 :
|
||||
MLS_DForm_R_SI34_RTA5_MEM_p<42, (outs g8rc:$RT), (ins memri34:$D_RA),
|
||||
(ins memri34_pcrel:$D_RA), "plha $RT, $D_RA",
|
||||
IIC_LdStLFD>;
|
||||
defm PLWA8 :
|
||||
8LS_DForm_R_SI34_RTA5_p<41, (outs g8rc:$RT), (ins memri34:$D_RA),
|
||||
(ins memri34_pcrel:$D_RA), "plwa $RT, $D_RA",
|
||||
IIC_LdStLFD>;
|
||||
defm PLWZ8 :
|
||||
MLS_DForm_R_SI34_RTA5_MEM_p<32, (outs g8rc:$RT), (ins memri34:$D_RA),
|
||||
(ins memri34_pcrel:$D_RA), "plwz $RT, $D_RA",
|
||||
IIC_LdStLFD>;
|
||||
}
|
||||
defm PLBZ :
|
||||
MLS_DForm_R_SI34_RTA5_MEM_p<34, (outs gprc:$RT), (ins memri34:$D_RA),
|
||||
(ins memri34_pcrel:$D_RA), "plbz $RT, $D_RA",
|
||||
IIC_LdStLFD>;
|
||||
defm PLHZ :
|
||||
MLS_DForm_R_SI34_RTA5_MEM_p<40, (outs gprc:$RT), (ins memri34:$D_RA),
|
||||
(ins memri34_pcrel:$D_RA), "plhz $RT, $D_RA",
|
||||
IIC_LdStLFD>;
|
||||
defm PLHA :
|
||||
MLS_DForm_R_SI34_RTA5_MEM_p<42, (outs gprc:$RT), (ins memri34:$D_RA),
|
||||
(ins memri34_pcrel:$D_RA), "plha $RT, $D_RA",
|
||||
IIC_LdStLFD>;
|
||||
defm PLWZ :
|
||||
MLS_DForm_R_SI34_RTA5_MEM_p<32, (outs gprc:$RT), (ins memri34:$D_RA),
|
||||
(ins memri34_pcrel:$D_RA), "plwz $RT, $D_RA",
|
||||
IIC_LdStLFD>;
|
||||
defm PLWA :
|
||||
8LS_DForm_R_SI34_RTA5_p<41, (outs gprc:$RT), (ins memri34:$D_RA),
|
||||
(ins memri34_pcrel:$D_RA), "plwa $RT, $D_RA",
|
||||
IIC_LdStLFD>;
|
||||
defm PLD :
|
||||
8LS_DForm_R_SI34_RTA5_p<57, (outs g8rc:$RT), (ins memri34:$D_RA),
|
||||
(ins memri34_pcrel:$D_RA), "pld $RT, $D_RA",
|
||||
IIC_LdStLFD>;
|
||||
}
|
||||
|
||||
let mayStore = 1, mayLoad = 0 in {
|
||||
defm PSTXV :
|
||||
8LS_DForm_R_SI34_XT6_RA5_p<27, (outs), (ins vsrc:$XS, memri34:$D_RA),
|
||||
(ins vsrc:$XS, memri34_pcrel:$D_RA),
|
||||
"pstxv $XS, $D_RA", IIC_LdStLFD>;
|
||||
defm PSTFS :
|
||||
MLS_DForm_R_SI34_RTA5_MEM_p<52, (outs), (ins f4rc:$FRS, memri34:$D_RA),
|
||||
(ins f4rc:$FRS, memri34_pcrel:$D_RA),
|
||||
"pstfs $FRS, $D_RA", IIC_LdStLFD>;
|
||||
defm PSTFD :
|
||||
MLS_DForm_R_SI34_RTA5_MEM_p<54, (outs), (ins f8rc:$FRS, memri34:$D_RA),
|
||||
(ins f8rc:$FRS, memri34_pcrel:$D_RA),
|
||||
"pstfd $FRS, $D_RA", IIC_LdStLFD>;
|
||||
defm PSTXSSP :
|
||||
8LS_DForm_R_SI34_RTA5_p<47, (outs), (ins vfrc:$VRS, memri34:$D_RA),
|
||||
(ins vfrc:$VRS, memri34_pcrel:$D_RA),
|
||||
"pstxssp $VRS, $D_RA", IIC_LdStLFD>;
|
||||
defm PSTXSD :
|
||||
8LS_DForm_R_SI34_RTA5_p<46, (outs), (ins vfrc:$VRS, memri34:$D_RA),
|
||||
(ins vfrc:$VRS, memri34_pcrel:$D_RA),
|
||||
"pstxsd $VRS, $D_RA", IIC_LdStLFD>;
|
||||
let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
|
||||
defm PSTB8 :
|
||||
MLS_DForm_R_SI34_RTA5_MEM_p<38, (outs), (ins g8rc:$RS, memri34:$D_RA),
|
||||
(ins g8rc:$RS, memri34_pcrel:$D_RA),
|
||||
"pstb $RS, $D_RA", IIC_LdStLFD>;
|
||||
defm PSTH8 :
|
||||
MLS_DForm_R_SI34_RTA5_MEM_p<44, (outs), (ins g8rc:$RS, memri34:$D_RA),
|
||||
(ins g8rc:$RS, memri34_pcrel:$D_RA),
|
||||
"psth $RS, $D_RA", IIC_LdStLFD>;
|
||||
defm PSTW8 :
|
||||
MLS_DForm_R_SI34_RTA5_MEM_p<36, (outs), (ins g8rc:$RS, memri34:$D_RA),
|
||||
(ins g8rc:$RS, memri34_pcrel:$D_RA),
|
||||
"pstw $RS, $D_RA", IIC_LdStLFD>;
|
||||
}
|
||||
defm PSTB :
|
||||
MLS_DForm_R_SI34_RTA5_MEM_p<38, (outs), (ins gprc:$RS, memri34:$D_RA),
|
||||
(ins gprc:$RS, memri34_pcrel:$D_RA),
|
||||
"pstb $RS, $D_RA", IIC_LdStLFD>;
|
||||
defm PSTH :
|
||||
MLS_DForm_R_SI34_RTA5_MEM_p<44, (outs), (ins gprc:$RS, memri34:$D_RA),
|
||||
(ins gprc:$RS, memri34_pcrel:$D_RA),
|
||||
"psth $RS, $D_RA", IIC_LdStLFD>;
|
||||
defm PSTW :
|
||||
MLS_DForm_R_SI34_RTA5_MEM_p<36, (outs), (ins gprc:$RS, memri34:$D_RA),
|
||||
(ins gprc:$RS, memri34_pcrel:$D_RA),
|
||||
"pstw $RS, $D_RA", IIC_LdStLFD>;
|
||||
defm PSTD :
|
||||
8LS_DForm_R_SI34_RTA5_p<61, (outs), (ins g8rc:$RS, memri34:$D_RA),
|
||||
(ins g8rc:$RS, memri34_pcrel:$D_RA),
|
||||
"pstd $RS, $D_RA", IIC_LdStLFD>;
|
||||
}
|
||||
}
|
||||
|
||||
def Concats {
|
||||
dag VecsToVecPair0 =
|
||||
|
|
@ -1366,7 +1371,7 @@ let Predicates = [IsISA3_1] in {
|
|||
def VSLDBI : VNForm_VTAB5_SD3<22, 0, (outs vrrc:$VRT),
|
||||
(ins vrrc:$VRA, vrrc:$VRB, u3imm:$SH),
|
||||
"vsldbi $VRT, $VRA, $VRB, $SH",
|
||||
IIC_VecGeneral,
|
||||
IIC_VecGeneral,
|
||||
[(set v16i8:$VRT,
|
||||
(int_ppc_altivec_vsldbi v16i8:$VRA,
|
||||
v16i8:$VRB,
|
||||
|
|
|
|||
Loading…
Reference in New Issue