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[Hexagon] Avoid UB when shifting unsigned integer left by 32 

llvm-svn: 333771
This commit is contained in:
Krzysztof Parzyszek 2018-06-01 15:39:10 +00:00
parent 2896c773eb
commit bc68385dad
1 changed files with 4 additions and 3 deletions
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7
llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
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@ -1169,16 +1169,17 @@ HexagonTargetLowering::LowerHvxCttz(SDValue Op, SelectionDAG &DAG) const {
// Calculate the vectors of 1 and bitwidth(x). // Calculate the vectors of 1 and bitwidth(x).
MVT ElemTy = ty(InpV).getVectorElementType(); MVT ElemTy = ty(InpV).getVectorElementType();
unsigned ElemWidth = ElemTy.getSizeInBits(); unsigned ElemWidth = ElemTy.getSizeInBits();
uint32_t Splat1 = 0, SplatW = 0; // Using uint64_t because a shift by 32 can happen.
uint64_t Splat1 = 0, SplatW = 0;
assert(isPowerOf2_32(ElemWidth) && ElemWidth <= 32); assert(isPowerOf2_32(ElemWidth) && ElemWidth <= 32);
for (unsigned i = 0; i != 32/ElemWidth; ++i) { for (unsigned i = 0; i != 32/ElemWidth; ++i) {
Splat1 = (Splat1 << ElemWidth) | 1; Splat1 = (Splat1 << ElemWidth) | 1;
SplatW = (SplatW << ElemWidth) | ElemWidth; SplatW = (SplatW << ElemWidth) | ElemWidth;
} }
SDValue Vec1 = DAG.getNode(HexagonISD::VSPLATW, dl, ResTy, SDValue Vec1 = DAG.getNode(HexagonISD::VSPLATW, dl, ResTy,
DAG.getConstant(Splat1, dl, MVT::i32)); DAG.getConstant(uint32_t(Splat1), dl, MVT::i32));
SDValue VecW = DAG.getNode(HexagonISD::VSPLATW, dl, ResTy, SDValue VecW = DAG.getNode(HexagonISD::VSPLATW, dl, ResTy,
DAG.getConstant(SplatW, dl, MVT::i32)); DAG.getConstant(uint32_t(SplatW), dl, MVT::i32));
SDValue VecN1 = DAG.getNode(HexagonISD::VSPLATW, dl, ResTy, SDValue VecN1 = DAG.getNode(HexagonISD::VSPLATW, dl, ResTy,
DAG.getConstant(-1, dl, MVT::i32)); DAG.getConstant(-1, dl, MVT::i32));
// Do not use DAG.getNOT, because that would create BUILD_VECTOR with // Do not use DAG.getNOT, because that would create BUILD_VECTOR with