forked from OSchip/llvm-project
[AArch64][GlobalISel] NFC: Refactor G_FCMP selection code
Refactor this so it's similar to the existing integer comparison code. Also add some missing 64-bit testcases to select-fcmp.mir. Refactoring to prep for improving selection for G_FCMP-related conditional branches etc. Differential Revision: https://reviews.llvm.org/D88614
This commit is contained in:
Jessica Paquette
parent
e4f50e587f
commit
bc43ddf42f
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@ -172,6 +172,11 @@ private:
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emitIntegerCompare(MachineOperand &LHS, MachineOperand &RHS,
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MachineOperand &Predicate,
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MachineIRBuilder &MIRBuilder) const;
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/// Emit a floating point comparison between \p LHS and \p RHS.
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MachineInstr *emitFPCompare(Register LHS, Register RHS,
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MachineIRBuilder &MIRBuilder) const;
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MachineInstr *emitInstr(unsigned Opcode,
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std::initializer_list<llvm::DstOp> DstOps,
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std::initializer_list<llvm::SrcOp> SrcOps,
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@ -238,9 +243,16 @@ private:
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MachineInstr *emitFMovForFConstant(MachineInstr &MI,
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MachineRegisterInfo &MRI) const;
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/// Emit a CSet for a compare.
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/// Emit a CSet for an integer compare.
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///
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/// \p DefReg is expected to be a 32-bit scalar register.
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MachineInstr *emitCSetForICMP(Register DefReg, unsigned Pred,
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MachineIRBuilder &MIRBuilder) const;
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/// Emit a CSet for a FP compare.
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///
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/// \p Dst is expected to be a 32-bit scalar register.
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MachineInstr *emitCSetForFCmp(Register Dst, CmpInst::Predicate Pred,
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MachineIRBuilder &MIRBuilder) const;
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/// Emit a TB(N)Z instruction which tests \p Bit in \p TestReg.
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/// \p IsNegative is true if the test should be "not zero".
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@ -998,20 +1010,6 @@ static unsigned selectSelectOpc(MachineInstr &I, MachineRegisterInfo &MRI,
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return 0;
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}
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/// Helper function to select the opcode for a G_FCMP.
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static unsigned selectFCMPOpc(MachineInstr &I, MachineRegisterInfo &MRI) {
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// If this is a compare against +0.0, then we don't have to explicitly
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// materialize a constant.
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const ConstantFP *FPImm = getConstantFPVRegVal(I.getOperand(3).getReg(), MRI);
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bool ShouldUseImm = FPImm && (FPImm->isZero() && !FPImm->isNegative());
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unsigned OpSize = MRI.getType(I.getOperand(2).getReg()).getSizeInBits();
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if (OpSize != 32 && OpSize != 64)
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return 0;
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unsigned CmpOpcTbl[2][2] = {{AArch64::FCMPSrr, AArch64::FCMPDrr},
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{AArch64::FCMPSri, AArch64::FCMPDri}};
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return CmpOpcTbl[ShouldUseImm][OpSize == 64];
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}
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/// Returns true if \p P is an unsigned integer comparison predicate.
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static bool isUnsignedICMPPred(const CmpInst::Predicate P) {
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switch (P) {
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@ -2882,64 +2880,13 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
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}
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case TargetOpcode::G_FCMP: {
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if (Ty != LLT::scalar(32)) {
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LLVM_DEBUG(dbgs() << "G_FCMP result has type: " << Ty
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<< ", expected: " << LLT::scalar(32) << '\n');
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MachineIRBuilder MIRBuilder(I);
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CmpInst::Predicate Pred =
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static_cast<CmpInst::Predicate>(I.getOperand(1).getPredicate());
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if (!emitFPCompare(I.getOperand(2).getReg(), I.getOperand(3).getReg(),
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MIRBuilder) ||
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!emitCSetForFCmp(I.getOperand(0).getReg(), Pred, MIRBuilder))
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return false;
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}
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unsigned CmpOpc = selectFCMPOpc(I, MRI);
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if (!CmpOpc)
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return false;
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// FIXME: regbank
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AArch64CC::CondCode CC1, CC2;
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changeFCMPPredToAArch64CC(
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(CmpInst::Predicate)I.getOperand(1).getPredicate(), CC1, CC2);
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// Partially build the compare. Decide if we need to add a use for the
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// third operand based off whether or not we're comparing against 0.0.
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auto CmpMI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(CmpOpc))
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.addUse(I.getOperand(2).getReg());
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// If we don't have an immediate compare, then we need to add a use of the
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// register which wasn't used for the immediate.
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// Note that the immediate will always be the last operand.
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if (CmpOpc != AArch64::FCMPSri && CmpOpc != AArch64::FCMPDri)
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CmpMI = CmpMI.addUse(I.getOperand(3).getReg());
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const Register DefReg = I.getOperand(0).getReg();
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Register Def1Reg = DefReg;
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if (CC2 != AArch64CC::AL)
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Def1Reg = MRI.createVirtualRegister(&AArch64::GPR32RegClass);
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MachineInstr &CSetMI =
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*BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::CSINCWr))
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.addDef(Def1Reg)
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.addUse(AArch64::WZR)
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.addUse(AArch64::WZR)
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.addImm(getInvertedCondCode(CC1));
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if (CC2 != AArch64CC::AL) {
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Register Def2Reg = MRI.createVirtualRegister(&AArch64::GPR32RegClass);
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MachineInstr &CSet2MI =
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*BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::CSINCWr))
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.addDef(Def2Reg)
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.addUse(AArch64::WZR)
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.addUse(AArch64::WZR)
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.addImm(getInvertedCondCode(CC2));
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MachineInstr &OrMI =
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*BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::ORRWrr))
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.addDef(DefReg)
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.addUse(Def1Reg)
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.addUse(Def2Reg);
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constrainSelectedInstRegOperands(OrMI, TII, TRI, RBI);
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constrainSelectedInstRegOperands(CSet2MI, TII, TRI, RBI);
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}
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constrainSelectedInstRegOperands(*CmpMI, TII, TRI, RBI);
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constrainSelectedInstRegOperands(CSetMI, TII, TRI, RBI);
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I.eraseFromParent();
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return true;
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}
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@ -3984,6 +3931,66 @@ AArch64InstructionSelector::emitIntegerCompare(
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return {&*CmpMI, P};
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}
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MachineInstr *AArch64InstructionSelector::emitCSetForFCmp(
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Register Dst, CmpInst::Predicate Pred, MachineIRBuilder &MIRBuilder) const {
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MachineRegisterInfo &MRI = *MIRBuilder.getMRI();
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#ifndef NDEBUG
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LLT Ty = MRI.getType(Dst);
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assert(!Ty.isVector() && Ty.getSizeInBits() == 32 &&
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"Expected a 32-bit scalar register?");
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#endif
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const Register ZeroReg = AArch64::WZR;
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auto EmitCSet = [&](Register CsetDst, AArch64CC::CondCode CC) {
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auto CSet =
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MIRBuilder.buildInstr(AArch64::CSINCWr, {CsetDst}, {ZeroReg, ZeroReg})
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.addImm(getInvertedCondCode(CC));
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constrainSelectedInstRegOperands(*CSet, TII, TRI, RBI);
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return &*CSet;
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};
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AArch64CC::CondCode CC1, CC2;
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changeFCMPPredToAArch64CC(Pred, CC1, CC2);
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if (CC2 == AArch64CC::AL)
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return EmitCSet(Dst, CC1);
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const TargetRegisterClass *RC = &AArch64::GPR32RegClass;
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Register Def1Reg = MRI.createVirtualRegister(RC);
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Register Def2Reg = MRI.createVirtualRegister(RC);
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EmitCSet(Def1Reg, CC1);
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EmitCSet(Def2Reg, CC2);
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auto OrMI = MIRBuilder.buildInstr(AArch64::ORRWrr, {Dst}, {Def1Reg, Def2Reg});
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constrainSelectedInstRegOperands(*OrMI, TII, TRI, RBI);
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return &*OrMI;
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}
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MachineInstr *
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AArch64InstructionSelector::emitFPCompare(Register LHS, Register RHS,
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MachineIRBuilder &MIRBuilder) const {
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MachineRegisterInfo &MRI = *MIRBuilder.getMRI();
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LLT Ty = MRI.getType(LHS);
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if (Ty.isVector())
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return nullptr;
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unsigned OpSize = Ty.getSizeInBits();
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if (OpSize != 32 && OpSize != 64)
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return nullptr;
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// If this is a compare against +0.0, then we don't have
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// to explicitly materialize a constant.
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const ConstantFP *FPImm = getConstantFPVRegVal(RHS, MRI);
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bool ShouldUseImm = FPImm && (FPImm->isZero() && !FPImm->isNegative());
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unsigned CmpOpcTbl[2][2] = {{AArch64::FCMPSrr, AArch64::FCMPDrr},
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{AArch64::FCMPSri, AArch64::FCMPDri}};
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unsigned CmpOpc = CmpOpcTbl[ShouldUseImm][OpSize == 64];
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// Partially build the compare. Decide if we need to add a use for the
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// third operand based off whether or not we're comparing against 0.0.
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auto CmpMI = MIRBuilder.buildInstr(CmpOpc).addUse(LHS);
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if (!ShouldUseImm)
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CmpMI.addUse(RHS);
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constrainSelectedInstRegOperands(*CmpMI, TII, TRI, RBI);
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return &*CmpMI;
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}
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MachineInstr *AArch64InstructionSelector::emitVectorConcat(
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Optional<Register> Dst, Register Op1, Register Op2,
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MachineIRBuilder &MIRBuilder) const {
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@ -4169,10 +4176,10 @@ bool AArch64InstructionSelector::tryOptSelect(MachineInstr &I) const {
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CondCode = changeICMPPredToAArch64CC(Pred);
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} else {
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// Get the condition code for the select.
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CmpInst::Predicate Pred =
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static_cast<CmpInst::Predicate>(CondDef->getOperand(1).getPredicate());
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AArch64CC::CondCode CondCode2;
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changeFCMPPredToAArch64CC(
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(CmpInst::Predicate)CondDef->getOperand(1).getPredicate(), CondCode,
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CondCode2);
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changeFCMPPredToAArch64CC(Pred, CondCode, CondCode2);
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// changeFCMPPredToAArch64CC sets CondCode2 to AL when we require two
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// instructions to emit the comparison.
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@ -4181,16 +4188,11 @@ bool AArch64InstructionSelector::tryOptSelect(MachineInstr &I) const {
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if (CondCode2 != AArch64CC::AL)
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return false;
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// Make sure we'll be able to select the compare.
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unsigned CmpOpc = selectFCMPOpc(*CondDef, MRI);
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if (!CmpOpc)
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if (!emitFPCompare(CondDef->getOperand(2).getReg(),
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CondDef->getOperand(3).getReg(), MIB)) {
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LLVM_DEBUG(dbgs() << "Couldn't emit compare for select!\n");
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return false;
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// Emit a new compare.
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auto Cmp = MIB.buildInstr(CmpOpc, {}, {CondDef->getOperand(2).getReg()});
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if (CmpOpc != AArch64::FCMPSri && CmpOpc != AArch64::FCMPDri)
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Cmp.addUse(CondDef->getOperand(3).getReg());
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constrainSelectedInstRegOperands(*Cmp, TII, TRI, RBI);
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}
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}
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// Emit the select.
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@ -54,3 +54,56 @@ body: |
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%3:gpr(s32) = G_FCMP floatpred(oeq), %0(s32), %2
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$s0 = COPY %3(s32)
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RET_ReallyLR implicit $s0
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...
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---
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name: notzero_s64
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.1:
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liveins: $d0, $d1
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; CHECK-LABEL: name: notzero_s64
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; CHECK: liveins: $d0, $d1
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[FMOVDi:%[0-9]+]]:fpr64 = FMOVDi 112
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; CHECK: FCMPDrr [[COPY]], [[FMOVDi]], implicit-def $nzcv
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; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
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; CHECK: $s0 = COPY [[CSINCWr]]
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; CHECK: RET_ReallyLR implicit $s0
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%0:fpr(s64) = COPY $d0
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%1:fpr(s64) = COPY $d1
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%2:fpr(s64) = G_FCONSTANT double 1.000000e+00
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%3:gpr(s32) = G_FCMP floatpred(oeq), %0(s64), %2
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$s0 = COPY %3(s32)
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RET_ReallyLR implicit $s0
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...
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---
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name: zero_s64
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $d0, $d1, $s0
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; CHECK-LABEL: name: zero_s64
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; CHECK: liveins: $d0, $d1, $s0
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: FCMPDri [[COPY]], implicit-def $nzcv
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; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
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; CHECK: $s0 = COPY [[CSINCWr]]
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; CHECK: RET_ReallyLR implicit $s0
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%0:fpr(s64) = COPY $d0
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%1:fpr(s64) = COPY $d1
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%2:fpr(s64) = G_FCONSTANT double 0.000000e+00
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%3:gpr(s32) = G_FCMP floatpred(oeq), %0(s64), %2
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$s0 = COPY %3(s32)
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RET_ReallyLR implicit $s0
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