forked from OSchip/llvm-project
[ARM] Fix computeKnownBits for ARMISD::CMOV
Summary: The true and false operands for the CMOV are operands 0 and 1. ARMISelLowering.cpp::computeKnownBits was looking at operands 1 and 2 instead. This can cause CMOV instructions to be incorrectly folded into BFI if value set by the CMOV is another CMOV, whose known bits are computed incorrectly. This patch fixes the issue and adds a test case. Reviewers: kristof.beyls, jmolloy Subscribers: llvm-commits, aemerson, srhines, rengolin Differential Revision: https://reviews.llvm.org/D31265 llvm-svn: 298624
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@ -11695,8 +11695,8 @@ static void computeKnownBits(SelectionDAG &DAG, SDValue Op, APInt &KnownZero,
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if (Op.getOpcode() == ARMISD::CMOV) {
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APInt KZ2(KnownZero.getBitWidth(), 0);
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APInt KO2(KnownOne.getBitWidth(), 0);
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computeKnownBits(DAG, Op.getOperand(1), KnownZero, KnownOne);
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computeKnownBits(DAG, Op.getOperand(2), KZ2, KO2);
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computeKnownBits(DAG, Op.getOperand(0), KnownZero, KnownOne);
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computeKnownBits(DAG, Op.getOperand(1), KZ2, KO2);
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KnownZero &= KZ2;
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KnownOne &= KO2;
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@ -0,0 +1,19 @@
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; RUN: llc < %s -mtriple=thumbv7 | FileCheck --check-prefix=CHECK-NOBFI %s
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declare zeroext i1 @dummy()
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define i8 @test(i8 %a1, i1 %c) {
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; CHECK-NOBFI-NOT: bfi
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; CHECK-NOBFI: bl dummy
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; CHECK-NOBFI: cmp r0, #0
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; CHECK-NOBFI: it ne
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; CHECK-NOBFI: orrne [[REG:r[0-9]+]], [[REG]], #8
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; CHECK-NOBFI: mov r0, [[REG]]
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%1 = and i8 %a1, -9
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%2 = select i1 %c, i8 %1, i8 %a1
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%3 = tail call zeroext i1 @dummy()
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%4 = or i8 %2, 8
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%ret = select i1 %3, i8 %4, i8 %2
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ret i8 %ret
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}
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