maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

Next round of MC refactoring. This patch factor MC table instantiations, MC 

registeration and creation code into XXXMCDesc libraries.

llvm-svn: 135184
This commit is contained in:
Evan Cheng 2011-07-14 20:59:42 +00:00
parent 0c134b52b9
commit bc153d49b7
134 changed files with 1285 additions and 495 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
llvm/lib/Target/ARM/ARM.h
View File

@ -16,6 +16,7 @@
#define TARGET_ARM_H
#include "ARMBaseInfo.h"
#include "MCTargetDesc/ARMMCTargetDesc.h"
#include "llvm/Support/DataTypes.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Target/TargetMachine.h"
@ -57,8 +58,6 @@ FunctionPass *createMLxExpansionPass();
FunctionPass *createThumb2ITBlockPass();
FunctionPass *createThumb2SizeReductionPass();
extern Target TheARMTarget, TheThumbTarget;
void LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
ARMAsmPrinter &AP);

1
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
View File

@ -36,7 +36,6 @@
#include "llvm/Support/ErrorHandling.h"
#include "llvm/ADT/STLExtras.h"
#define GET_INSTRINFO_MC_DESC
#define GET_INSTRINFO_CTOR
#include "ARMGenInstrInfo.inc"

1
llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
View File

@ -40,7 +40,6 @@
#include "llvm/ADT/SmallVector.h"
#include "llvm/Support/CommandLine.h"
#define GET_REGINFO_MC_DESC
#define GET_REGINFO_TARGET_DESC
#include "ARMGenRegisterInfo.inc"

3
llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp
View File

@ -26,9 +26,6 @@
#include "llvm/ADT/Statistic.h"
#include "llvm/Support/raw_ostream.h"
#define GET_SUBTARGETINFO_ENUM
#include "ARMGenSubtargetInfo.inc"
using namespace llvm;
STATISTIC(MCNumEmitted, "Number of MC instructions emitted.");

2
llvm/lib/Target/ARM/ARMSubtarget.cpp
View File

@ -18,8 +18,6 @@
#include "llvm/Support/CommandLine.h"
#include "llvm/ADT/SmallVector.h"
#define GET_SUBTARGETINFO_ENUM
#define GET_SUBTARGETINFO_MC_DESC
#define GET_SUBTARGETINFO_TARGET_DESC
#define GET_SUBTARGETINFO_CTOR
#include "ARMGenSubtargetInfo.inc"

3
llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
View File

@ -31,9 +31,6 @@
#include "llvm/ADT/StringSwitch.h"
#include "llvm/ADT/Twine.h"
#define GET_SUBTARGETINFO_ENUM
#include "ARMGenSubtargetInfo.inc"
using namespace llvm;
namespace {

7
llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
View File

@ -70,9 +70,10 @@
///
/// { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), 0 }
///
/// And this maps to one MCOperand with the regsiter kind of ARM::CPSR.
#define GET_INSTRINFO_MC_DESC
#include "ARMGenInstrInfo.inc"
namespace llvm {
extern const MCInstrDesc ARMInsts[];
}
using namespace llvm;

1
llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
View File

@ -23,7 +23,6 @@
#define GET_INSTRINFO_MC_DESC
#include "ARMGenInstrInfo.inc"
#define GET_SUBTARGETINFO_ENUM
#define GET_SUBTARGETINFO_MC_DESC
#include "ARMGenSubtargetInfo.inc"

3
llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h
View File

@ -46,4 +46,7 @@ namespace ARM_MC {
#define GET_INSTRINFO_ENUM
#include "ARMGenInstrInfo.inc"
#define GET_SUBTARGETINFO_ENUM
#include "ARMGenSubtargetInfo.inc"
#endif

15
llvm/lib/Target/Alpha/Alpha.h
View File

@ -15,6 +15,7 @@
#ifndef TARGET_ALPHA_H
#define TARGET_ALPHA_H
#include "MCTargetDesc/AlphaMCTargetDesc.h"
#include "llvm/Target/TargetMachine.h"
namespace llvm {
@ -37,20 +38,6 @@ namespace llvm {
FunctionPass *createAlphaLLRPPass(AlphaTargetMachine &tm);
FunctionPass *createAlphaBranchSelectionPass();
extern Target TheAlphaTarget;
} // end namespace llvm;
// Defines symbolic names for Alpha registers. This defines a mapping from
// register name to register number.
//
#define GET_REGINFO_ENUM
#include "AlphaGenRegisterInfo.inc"
// Defines symbolic names for the Alpha instructions.
//
#define GET_INSTRINFO_ENUM
#include "AlphaGenInstrInfo.inc"
#endif

11
llvm/lib/Target/Alpha/AlphaInstrInfo.cpp
View File

@ -21,7 +21,6 @@
#include "llvm/ADT/SmallVector.h"
#include "llvm/Support/ErrorHandling.h"
#define GET_INSTRINFO_MC_DESC
#define GET_INSTRINFO_CTOR
#include "AlphaGenInstrInfo.inc"
using namespace llvm;
@ -382,13 +381,3 @@ unsigned AlphaInstrInfo::getGlobalRetAddr(MachineFunction *MF) const {
AlphaFI->setGlobalRetAddr(GlobalRetAddr);
return GlobalRetAddr;
}
MCInstrInfo *createAlphaMCInstrInfo() {
MCInstrInfo *X = new MCInstrInfo();
InitAlphaMCInstrInfo(X);
return X;
}
extern "C" void LLVMInitializeAlphaMCInstrInfo() {
TargetRegistry::RegisterMCInstrInfo(TheAlphaTarget, createAlphaMCInstrInfo);
}

1
llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp
View File

@ -34,7 +34,6 @@
#include "llvm/ADT/STLExtras.h"
#include <cstdlib>
#define GET_REGINFO_MC_DESC
#define GET_REGINFO_TARGET_DESC
#include "AlphaGenRegisterInfo.inc"

14
llvm/lib/Target/Alpha/AlphaSubtarget.cpp
View File

@ -15,8 +15,6 @@
#include "Alpha.h"
#include "llvm/Target/TargetRegistry.h"
#define GET_SUBTARGETINFO_ENUM
#define GET_SUBTARGETINFO_MC_DESC
#define GET_SUBTARGETINFO_TARGET_DESC
#define GET_SUBTARGETINFO_CTOR
#include "AlphaGenSubtargetInfo.inc"
@ -36,15 +34,3 @@ AlphaSubtarget::AlphaSubtarget(const std::string &TT, const std::string &CPU,
// Initialize scheduling itinerary for the specified CPU.
InstrItins = getInstrItineraryForCPU(CPUName);
}
MCSubtargetInfo *createAlphaMCSubtargetInfo(StringRef TT, StringRef CPU,
StringRef FS) {
MCSubtargetInfo *X = new MCSubtargetInfo();
InitAlphaMCSubtargetInfo(X, TT, CPU, FS);
return X;
}
extern "C" void LLVMInitializeAlphaMCSubtargetInfo() {
TargetRegistry::RegisterMCSubtargetInfo(TheAlphaTarget,
createAlphaMCSubtargetInfo);
}

1
llvm/lib/Target/Alpha/CMakeLists.txt
View File

@ -23,3 +23,4 @@ add_llvm_target(AlphaCodeGen
)
add_subdirectory(TargetInfo)
add_subdirectory(MCTargetDesc)

53
llvm/lib/Target/Alpha/MCTargetDesc/AlphaMCTargetDesc.cpp Normal file
View File

@ -0,0 +1,53 @@
//===-- AlphaMCTargetDesc.cpp - Alpha Target Descriptions -------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file provides Alpha specific target descriptions.
//
//===----------------------------------------------------------------------===//
#include "AlphaMCTargetDesc.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/Target/TargetRegistry.h"
#define GET_INSTRINFO_MC_DESC
#include "AlphaGenInstrInfo.inc"
#define GET_SUBTARGETINFO_MC_DESC
#include "AlphaGenSubtargetInfo.inc"
#define GET_REGINFO_MC_DESC
#include "AlphaGenRegisterInfo.inc"
using namespace llvm;
MCInstrInfo *createAlphaMCInstrInfo() {
MCInstrInfo *X = new MCInstrInfo();
InitAlphaMCInstrInfo(X);
return X;
}
extern "C" void LLVMInitializeAlphaMCInstrInfo() {
TargetRegistry::RegisterMCInstrInfo(TheAlphaTarget, createAlphaMCInstrInfo);
}
MCSubtargetInfo *createAlphaMCSubtargetInfo(StringRef TT, StringRef CPU,
StringRef FS) {
MCSubtargetInfo *X = new MCSubtargetInfo();
InitAlphaMCSubtargetInfo(X, TT, CPU, FS);
return X;
}
extern "C" void LLVMInitializeAlphaMCSubtargetInfo() {
TargetRegistry::RegisterMCSubtargetInfo(TheAlphaTarget,
createAlphaMCSubtargetInfo);
}

40
llvm/lib/Target/Alpha/MCTargetDesc/AlphaMCTargetDesc.h Normal file
View File

@ -0,0 +1,40 @@
//===-- AlphaMCTargetDesc.h - Alpha Target Descriptions ---------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file provides Alpha specific target descriptions.
//
//===----------------------------------------------------------------------===//
#ifndef ALPHAMCTARGETDESC_H
#define ALPHAMCTARGETDESC_H
namespace llvm {
class MCSubtargetInfo;
class Target;
class StringRef;
extern Target TheAlphaTarget;
} // End llvm namespace
// Defines symbolic names for Alpha registers. This defines a mapping from
// register name to register number.
//
#define GET_REGINFO_ENUM
#include "AlphaGenRegisterInfo.inc"
// Defines symbolic names for the Alpha instructions.
//
#define GET_INSTRINFO_ENUM
#include "AlphaGenInstrInfo.inc"
#define GET_SUBTARGETINFO_ENUM
#include "AlphaGenSubtargetInfo.inc"
#endif

1
llvm/lib/Target/Alpha/MCTargetDesc/CMakeLists.txt Normal file
View File

@ -0,0 +1 @@
add_llvm_library(LLVMAlphaDesc AlphaMCTargetDesc.cpp)

16
llvm/lib/Target/Alpha/MCTargetDesc/Makefile Normal file
View File

@ -0,0 +1,16 @@
##===- lib/Target/Alpha/TargetDesc/Makefile ----------------*- Makefile -*-===##
#
# The LLVM Compiler Infrastructure
#
# This file is distributed under the University of Illinois Open Source
# License. See LICENSE.TXT for details.
#
##===----------------------------------------------------------------------===##
LEVEL = ../../../..
LIBRARYNAME = LLVMAlphaDesc
# Hack: we need to include 'main' target directory to grab private headers
CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/..
include $(LEVEL)/Makefile.common

2
llvm/lib/Target/Alpha/Makefile
View File

@ -16,6 +16,6 @@ BUILT_SOURCES = AlphaGenRegisterInfo.inc AlphaGenInstrInfo.inc \
AlphaGenAsmWriter.inc AlphaGenDAGISel.inc \
AlphaGenCallingConv.inc AlphaGenSubtargetInfo.inc
DIRS = TargetInfo
DIRS = TargetInfo MCTargetDesc
include $(LEVEL)/Makefile.common

11
llvm/lib/Target/Blackfin/Blackfin.h
View File

@ -15,6 +15,7 @@
#ifndef TARGET_BLACKFIN_H
#define TARGET_BLACKFIN_H
#include "MCTargetDesc/BlackfinMCTargetDesc.h"
#include "llvm/Target/TargetMachine.h"
namespace llvm {
@ -24,17 +25,7 @@ namespace llvm {
FunctionPass *createBlackfinISelDag(BlackfinTargetMachine &TM,
CodeGenOpt::Level OptLevel);
extern Target TheBlackfinTarget;
} // end namespace llvm
// Defines symbolic names for Blackfin registers. This defines a mapping from
// register name to register number.
#define GET_REGINFO_ENUM
#include "BlackfinGenRegisterInfo.inc"
// Defines symbolic names for the Blackfin instructions.
#define GET_INSTRINFO_ENUM
#include "BlackfinGenInstrInfo.inc"
#endif

12
llvm/lib/Target/Blackfin/BlackfinInstrInfo.cpp
View File

@ -22,7 +22,6 @@
#include "llvm/Support/ErrorHandling.h"
#define GET_INSTRINFO_CTOR
#define GET_INSTRINFO_MC_DESC
#include "BlackfinGenInstrInfo.inc"
using namespace llvm;
@ -255,14 +254,3 @@ loadRegFromAddr(MachineFunction &MF,
SmallVectorImpl<MachineInstr*> &NewMIs) const {
llvm_unreachable("loadRegFromAddr not implemented");
}
MCInstrInfo *createBlackfinMCInstrInfo() {
MCInstrInfo *X = new MCInstrInfo();
InitBlackfinMCInstrInfo(X);
return X;
}
extern "C" void LLVMInitializeBlackfinMCInstrInfo() {
TargetRegistry::RegisterMCInstrInfo(TheBlackfinTarget,
createBlackfinMCInstrInfo);
}

1
llvm/lib/Target/Blackfin/BlackfinRegisterInfo.cpp
View File

@ -30,7 +30,6 @@
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/STLExtras.h"
#define GET_REGINFO_MC_DESC
#define GET_REGINFO_TARGET_DESC
#include "BlackfinGenRegisterInfo.inc"

14
llvm/lib/Target/Blackfin/BlackfinSubtarget.cpp
View File

@ -15,8 +15,6 @@
#include "Blackfin.h"
#include "llvm/Target/TargetRegistry.h"
#define GET_SUBTARGETINFO_ENUM
#define GET_SUBTARGETINFO_MC_DESC
#define GET_SUBTARGETINFO_TARGET_DESC
#define GET_SUBTARGETINFO_CTOR
#include "BlackfinGenSubtargetInfo.inc"
@ -44,15 +42,3 @@ BlackfinSubtarget::BlackfinSubtarget(const std::string &TT,
// Parse features string.
ParseSubtargetFeatures(CPUName, FS);
}
MCSubtargetInfo *createBlackfinMCSubtargetInfo(StringRef TT, StringRef CPU,
StringRef FS) {
MCSubtargetInfo *X = new MCSubtargetInfo();
InitBlackfinMCSubtargetInfo(X, TT, CPU, FS);
return X;
}
extern "C" void LLVMInitializeBlackfinMCSubtargetInfo() {
TargetRegistry::RegisterMCSubtargetInfo(TheBlackfinTarget,
createBlackfinMCSubtargetInfo);
}

1
llvm/lib/Target/Blackfin/CMakeLists.txt
View File

@ -23,3 +23,4 @@ add_llvm_target(BlackfinCodeGen
)
add_subdirectory(TargetInfo)
add_subdirectory(MCTargetDesc)

54
llvm/lib/Target/Blackfin/MCTargetDesc/BlackfinMCTargetDesc.cpp Normal file
View File

@ -0,0 +1,54 @@
//===-- BlackfinMCTargetDesc.cpp - Blackfin Target Descriptions -*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file provides Blackfin specific target descriptions.
//
//===----------------------------------------------------------------------===//
#include "BlackfinMCTargetDesc.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/Target/TargetRegistry.h"
#define GET_INSTRINFO_MC_DESC
#include "BlackfinGenInstrInfo.inc"
#define GET_SUBTARGETINFO_MC_DESC
#include "BlackfinGenSubtargetInfo.inc"
#define GET_REGINFO_MC_DESC
#include "BlackfinGenRegisterInfo.inc"
using namespace llvm;
MCInstrInfo *createBlackfinMCInstrInfo() {
MCInstrInfo *X = new MCInstrInfo();
InitBlackfinMCInstrInfo(X);
return X;
}
extern "C" void LLVMInitializeBlackfinMCInstrInfo() {
TargetRegistry::RegisterMCInstrInfo(TheBlackfinTarget,
createBlackfinMCInstrInfo);
}
MCSubtargetInfo *createBlackfinMCSubtargetInfo(StringRef TT, StringRef CPU,
StringRef FS) {
MCSubtargetInfo *X = new MCSubtargetInfo();
InitBlackfinMCSubtargetInfo(X, TT, CPU, FS);
return X;
}
extern "C" void LLVMInitializeBlackfinMCSubtargetInfo() {
TargetRegistry::RegisterMCSubtargetInfo(TheBlackfinTarget,
createBlackfinMCSubtargetInfo);
}

38
llvm/lib/Target/Blackfin/MCTargetDesc/BlackfinMCTargetDesc.h Normal file
View File

@ -0,0 +1,38 @@
//===-- BlackfinMCTargetDesc.h - Blackfin Target Descriptions ---*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file provides Blackfin specific target descriptions.
//
//===----------------------------------------------------------------------===//
#ifndef BLACKFINMCTARGETDESC_H
#define BLACKFINMCTARGETDESC_H
namespace llvm {
class MCSubtargetInfo;
class Target;
class StringRef;
extern Target TheBlackfinTarget;
} // End llvm namespace
// Defines symbolic names for Blackfin registers. This defines a mapping from
// register name to register number.
#define GET_REGINFO_ENUM
#include "BlackfinGenRegisterInfo.inc"
// Defines symbolic names for the Blackfin instructions.
#define GET_INSTRINFO_ENUM
#include "BlackfinGenInstrInfo.inc"
#define GET_SUBTARGETINFO_ENUM
#include "BlackfinGenSubtargetInfo.inc"
#endif

1
llvm/lib/Target/Blackfin/MCTargetDesc/CMakeLists.txt Normal file
View File

@ -0,0 +1 @@
add_llvm_library(LLVMBlackfinDesc BlackfinMCTargetDesc.cpp)

16
llvm/lib/Target/Blackfin/MCTargetDesc/Makefile Normal file
View File

@ -0,0 +1,16 @@
##===- lib/Target/Blackfin/TargetDesc/Makefile -------------*- Makefile -*-===##
#
# The LLVM Compiler Infrastructure
#
# This file is distributed under the University of Illinois Open Source
# License. See LICENSE.TXT for details.
#
##===----------------------------------------------------------------------===##
LEVEL = ../../../..
LIBRARYNAME = LLVMBlackfinDesc
# Hack: we need to include 'main' target directory to grab private headers
CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/..
include $(LEVEL)/Makefile.common

2
llvm/lib/Target/Blackfin/Makefile
View File

@ -17,7 +17,7 @@ BUILT_SOURCES = BlackfinGenRegisterInfo.inc BlackfinGenInstrInfo.inc \
BlackfinGenDAGISel.inc BlackfinGenSubtargetInfo.inc \
BlackfinGenCallingConv.inc BlackfinGenIntrinsics.inc
DIRS = TargetInfo
DIRS = TargetInfo MCTargetDesc
include $(LEVEL)/Makefile.common

1
llvm/lib/Target/CellSPU/CMakeLists.txt
View File

@ -24,3 +24,4 @@ add_llvm_target(CellSPUCodeGen
)
add_subdirectory(TargetInfo)
add_subdirectory(MCTargetDesc)

1
llvm/lib/Target/CellSPU/MCTargetDesc/CMakeLists.txt Normal file
View File

@ -0,0 +1 @@
add_llvm_library(LLVMCellSPUDesc SPUMCTargetDesc.cpp)

16
llvm/lib/Target/CellSPU/MCTargetDesc/Makefile Normal file
View File

@ -0,0 +1,16 @@
##===- lib/Target/CellSPU/TargetDesc/Makefile --------------*- Makefile -*-===##
#
# The LLVM Compiler Infrastructure
#
# This file is distributed under the University of Illinois Open Source
# License. See LICENSE.TXT for details.
#
##===----------------------------------------------------------------------===##
LEVEL = ../../../..
LIBRARYNAME = LLVMCellSPUDesc
# Hack: we need to include 'main' target directory to grab private headers
CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/..
include $(LEVEL)/Makefile.common

51
llvm/lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.cpp Normal file
View File

@ -0,0 +1,51 @@
//===-- SPUMCTargetDesc.cpp - Cell SPU Target Descriptions -----*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file provides Cell SPU specific target descriptions.
//
//===----------------------------------------------------------------------===//
#include "SPUMCTargetDesc.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/Target/TargetRegistry.h"
#define GET_INSTRINFO_MC_DESC
#include "SPUGenInstrInfo.inc"
#define GET_SUBTARGETINFO_MC_DESC
#include "SPUGenSubtargetInfo.inc"
#define GET_REGINFO_MC_DESC
#include "SPUGenRegisterInfo.inc"
using namespace llvm;
MCInstrInfo *createSPUMCInstrInfo() {
MCInstrInfo *X = new MCInstrInfo();
InitSPUMCInstrInfo(X);
return X;
}
extern "C" void LLVMInitializeCellSPUMCInstrInfo() {
TargetRegistry::RegisterMCInstrInfo(TheCellSPUTarget, createSPUMCInstrInfo);
}
MCSubtargetInfo *createSPUMCSubtargetInfo(StringRef TT, StringRef CPU,
StringRef FS) {
MCSubtargetInfo *X = new MCSubtargetInfo();
InitSPUMCSubtargetInfo(X, TT, CPU, FS);
return X;
}
extern "C" void LLVMInitializeCellSPUMCSubtargetInfo() {
TargetRegistry::RegisterMCSubtargetInfo(TheCellSPUTarget,
createSPUMCSubtargetInfo);
}

40
llvm/lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.h Normal file
View File

@ -0,0 +1,40 @@
//===-- SPUMCTargetDesc.h - Alpha Target Descriptions ---------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file provides Alpha specific target descriptions.
//
//===----------------------------------------------------------------------===//
#ifndef SPUMCTARGETDESC_H
#define SPUMCTARGETDESC_H
namespace llvm {
class MCSubtargetInfo;
class Target;
class StringRef;
extern Target TheCellSPUTarget;
} // End llvm namespace
// Define symbolic names for Cell registers. This defines a mapping from
// register name to register number.
//
#define GET_REGINFO_ENUM
#include "SPUGenRegisterInfo.inc"
// Defines symbolic names for the SPU instructions.
//
#define GET_INSTRINFO_ENUM
#include "SPUGenInstrInfo.inc"
#define GET_SUBTARGETINFO_ENUM
#include "SPUGenSubtargetInfo.inc"
#endif

2
llvm/lib/Target/CellSPU/Makefile
View File

@ -15,6 +15,6 @@ BUILT_SOURCES = SPUGenInstrInfo.inc SPUGenRegisterInfo.inc \
SPUGenDAGISel.inc \
SPUGenSubtargetInfo.inc SPUGenCallingConv.inc
DIRS = TargetInfo
DIRS = TargetInfo MCTargetDesc
include $(LEVEL)/Makefile.common

7
llvm/lib/Target/CellSPU/SPU.h
View File

@ -15,6 +15,7 @@
#ifndef LLVM_TARGET_IBMCELLSPU_H
#define LLVM_TARGET_IBMCELLSPU_H
#include "MCTargetDesc/SPUMCTargetDesc.h"
#include "llvm/Target/TargetMachine.h"
namespace llvm {
@ -25,12 +26,6 @@ namespace llvm {
FunctionPass *createSPUISelDag(SPUTargetMachine &TM);
FunctionPass *createSPUNopFillerPass(SPUTargetMachine &tm);
extern Target TheCellSPUTarget;
}
// Defines symbolic names for the SPU instructions.
//
#define GET_INSTRINFO_ENUM
#include "SPUGenInstrInfo.inc"
#endif /* LLVM_TARGET_IBMCELLSPU_H */

1
llvm/lib/Target/CellSPU/SPUFrameLowering.cpp
View File

@ -13,7 +13,6 @@
#include "SPU.h"
#include "SPUFrameLowering.h"
#include "SPURegisterNames.h"
#include "SPUInstrBuilder.h"
#include "SPUInstrInfo.h"
#include "llvm/Function.h"

1
llvm/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
View File

@ -16,7 +16,6 @@
#include "SPUTargetMachine.h"
#include "SPUHazardRecognizers.h"
#include "SPUFrameLowering.h"
#include "SPURegisterNames.h"
#include "SPUTargetMachine.h"
#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"

1
llvm/lib/Target/CellSPU/SPUISelLowering.cpp
View File

@ -10,7 +10,6 @@
//
//===----------------------------------------------------------------------===//
#include "SPURegisterNames.h"
#include "SPUISelLowering.h"
#include "SPUTargetMachine.h"
#include "SPUFrameLowering.h"

12
llvm/lib/Target/CellSPU/SPUInstrInfo.cpp
View File

@ -11,7 +11,6 @@
//
//===----------------------------------------------------------------------===//
#include "SPURegisterNames.h"
#include "SPUInstrInfo.h"
#include "SPUInstrBuilder.h"
#include "SPUTargetMachine.h"
@ -24,7 +23,6 @@
#include "llvm/Support/raw_ostream.h"
#define GET_INSTRINFO_CTOR
#define GET_INSTRINFO_MC_DESC
#include "SPUGenInstrInfo.inc"
using namespace llvm;
@ -451,13 +449,3 @@ SPUInstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond)
return true;
}
MCInstrInfo *createSPUMCInstrInfo() {
MCInstrInfo *X = new MCInstrInfo();
InitSPUMCInstrInfo(X);
return X;
}
extern "C" void LLVMInitializeCellSPUMCInstrInfo() {
TargetRegistry::RegisterMCInstrInfo(TheCellSPUTarget, createSPUMCInstrInfo);
}

2
llvm/lib/Target/CellSPU/SPURegisterInfo.cpp
View File

@ -14,7 +14,6 @@
#define DEBUG_TYPE "reginfo"
#include "SPU.h"
#include "SPURegisterInfo.h"
#include "SPURegisterNames.h"
#include "SPUInstrBuilder.h"
#include "SPUSubtarget.h"
#include "SPUMachineFunction.h"
@ -43,7 +42,6 @@
#include "llvm/ADT/STLExtras.h"
#include <cstdlib>
#define GET_REGINFO_MC_DESC
#define GET_REGINFO_TARGET_DESC
#include "SPUGenRegisterInfo.inc"

14
llvm/lib/Target/CellSPU/SPUSubtarget.cpp
View File

@ -17,8 +17,6 @@
#include "llvm/Target/TargetRegistry.h"
#include "llvm/ADT/SmallVector.h"
#define GET_SUBTARGETINFO_ENUM
#define GET_SUBTARGETINFO_MC_DESC
#define GET_SUBTARGETINFO_TARGET_DESC
#define GET_SUBTARGETINFO_CTOR
#include "SPUGenSubtargetInfo.inc"
@ -66,15 +64,3 @@ bool SPUSubtarget::enablePostRAScheduler(
CriticalPathRCs.push_back(&SPU::VECREGRegClass);
return OptLevel >= CodeGenOpt::Default;
}
MCSubtargetInfo *createSPUMCSubtargetInfo(StringRef TT, StringRef CPU,
StringRef FS) {
MCSubtargetInfo *X = new MCSubtargetInfo();
InitSPUMCSubtargetInfo(X, TT, CPU, FS);
return X;
}
extern "C" void LLVMInitializeCellSPUMCSubtargetInfo() {
TargetRegistry::RegisterMCSubtargetInfo(TheCellSPUTarget,
createSPUMCSubtargetInfo);
}

1
llvm/lib/Target/CellSPU/SPUTargetMachine.cpp
View File

@ -12,7 +12,6 @@
//===----------------------------------------------------------------------===//
#include "SPU.h"
#include "SPURegisterNames.h"
#include "SPUMCAsmInfo.h"
#include "SPUTargetMachine.h"
#include "llvm/PassManager.h"

1
llvm/lib/Target/MBlaze/CMakeLists.txt
View File

@ -35,3 +35,4 @@ add_subdirectory(AsmParser)
add_subdirectory(Disassembler)
add_subdirectory(InstPrinter)
add_subdirectory(TargetInfo)
add_subdirectory(MCTargetDesc)

6
llvm/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp
View File

@ -27,10 +27,12 @@
// #include "MBlazeGenDecoderTables.inc"
// #include "MBlazeGenRegisterNames.inc"
#define GET_INSTRINFO_MC_DESC
#include "MBlazeGenInstrInfo.inc"
#include "MBlazeGenEDInfo.inc"
namespace llvm {
extern const MCInstrDesc MBlazeInsts[];
}
using namespace llvm;
const unsigned UNSUPPORTED = -1;

11
llvm/lib/Target/MBlaze/MBlaze.h
View File

@ -15,6 +15,7 @@
#ifndef TARGET_MBLAZE_H
#define TARGET_MBLAZE_H
#include "MCTargetDesc/MBlazeMCTargetDesc.h"
#include "llvm/Target/TargetMachine.h"
namespace llvm {
@ -36,16 +37,6 @@ namespace llvm {
FunctionPass *createMBlazeISelDag(MBlazeTargetMachine &TM);
FunctionPass *createMBlazeDelaySlotFillerPass(MBlazeTargetMachine &TM);
extern Target TheMBlazeTarget;
} // end namespace llvm;
// Defines symbolic names for MBlaze registers. This defines a mapping from
// register name to register number.
#define GET_REGINFO_ENUM
#include "MBlazeGenRegisterInfo.inc"
// Defines symbolic names for the MBlaze instructions.
#define GET_INSTRINFO_ENUM
#include "MBlazeGenInstrInfo.inc"
#endif

11
llvm/lib/Target/MBlaze/MBlazeInstrInfo.cpp
View File

@ -23,7 +23,6 @@
#include "llvm/ADT/STLExtras.h"
#define GET_INSTRINFO_CTOR
#define GET_INSTRINFO_MC_DESC
#include "MBlazeGenInstrInfo.inc"
using namespace llvm;
@ -295,13 +294,3 @@ unsigned MBlazeInstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
MBlazeFI->setGlobalBaseReg(GlobalBaseReg);
return GlobalBaseReg;
}
MCInstrInfo *createMBlazeMCInstrInfo() {
MCInstrInfo *X = new MCInstrInfo();
InitMBlazeMCInstrInfo(X);
return X;
}
extern "C" void LLVMInitializeMBlazeMCInstrInfo() {
TargetRegistry::RegisterMCInstrInfo(TheMBlazeTarget, createMBlazeMCInstrInfo);
}

1
llvm/lib/Target/MBlaze/MBlazeRegisterInfo.cpp
View File

@ -37,7 +37,6 @@
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/STLExtras.h"
#define GET_REGINFO_MC_DESC
#define GET_REGINFO_TARGET_DESC
#include "MBlazeGenRegisterInfo.inc"

14
llvm/lib/Target/MBlaze/MBlazeSubtarget.cpp
View File

@ -17,8 +17,6 @@
#include "llvm/Support/CommandLine.h"
#include "llvm/Target/TargetRegistry.h"
#define GET_SUBTARGETINFO_ENUM
#define GET_SUBTARGETINFO_MC_DESC
#define GET_SUBTARGETINFO_TARGET_DESC
#define GET_SUBTARGETINFO_CTOR
#include "MBlazeGenSubtargetInfo.inc"
@ -63,15 +61,3 @@ enablePostRAScheduler(CodeGenOpt::Level OptLevel,
CriticalPathRCs.push_back(&MBlaze::GPRRegClass);
return HasItin && OptLevel >= CodeGenOpt::Default;
}
MCSubtargetInfo *createMBlazeMCSubtargetInfo(StringRef TT, StringRef CPU,
StringRef FS) {
MCSubtargetInfo *X = new MCSubtargetInfo();
InitMBlazeMCSubtargetInfo(X, TT, CPU, FS);
return X;
}
extern "C" void LLVMInitializeMBlazeMCSubtargetInfo() {
TargetRegistry::RegisterMCSubtargetInfo(TheMBlazeTarget,
createMBlazeMCSubtargetInfo);
}

1
llvm/lib/Target/MBlaze/MCTargetDesc/CMakeLists.txt Normal file
View File

@ -0,0 +1 @@
add_llvm_library(LLVMMBlazeDesc MBlazeMCTargetDesc.cpp)

52
llvm/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp Normal file
View File

@ -0,0 +1,52 @@
//===-- MBlazeMCTargetDesc.cpp - MBlaze Target Descriptions -----*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file provides MBlaze specific target descriptions.
//
//===----------------------------------------------------------------------===//
#include "MBlazeMCTargetDesc.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/Target/TargetRegistry.h"
#define GET_INSTRINFO_MC_DESC
#include "MBlazeGenInstrInfo.inc"
#define GET_SUBTARGETINFO_MC_DESC
#include "MBlazeGenSubtargetInfo.inc"
#define GET_REGINFO_MC_DESC
#include "MBlazeGenRegisterInfo.inc"
using namespace llvm;
MCInstrInfo *createMBlazeMCInstrInfo() {
MCInstrInfo *X = new MCInstrInfo();
InitMBlazeMCInstrInfo(X);
return X;
}
extern "C" void LLVMInitializeMBlazeMCInstrInfo() {
TargetRegistry::RegisterMCInstrInfo(TheMBlazeTarget, createMBlazeMCInstrInfo);
}
MCSubtargetInfo *createMBlazeMCSubtargetInfo(StringRef TT, StringRef CPU,
StringRef FS) {
MCSubtargetInfo *X = new MCSubtargetInfo();
InitMBlazeMCSubtargetInfo(X, TT, CPU, FS);
return X;
}
extern "C" void LLVMInitializeMBlazeMCSubtargetInfo() {
TargetRegistry::RegisterMCSubtargetInfo(TheMBlazeTarget,
createMBlazeMCSubtargetInfo);
}

38
llvm/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.h Normal file
View File

@ -0,0 +1,38 @@
//===-- MBlazeMCTargetDesc.h - MBlaze Target Descriptions -------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file provides MBlaze specific target descriptions.
//
//===----------------------------------------------------------------------===//
#ifndef MBLAZEMCTARGETDESC_H
#define MBLAZEMCTARGETDESC_H
namespace llvm {
class MCSubtargetInfo;
class Target;
class StringRef;
extern Target TheMBlazeTarget;
} // End llvm namespace
// Defines symbolic names for MBlaze registers. This defines a mapping from
// register name to register number.
#define GET_REGINFO_ENUM
#include "MBlazeGenRegisterInfo.inc"
// Defines symbolic names for the MBlaze instructions.
#define GET_INSTRINFO_ENUM
#include "MBlazeGenInstrInfo.inc"
#define GET_SUBTARGETINFO_ENUM
#include "MBlazeGenSubtargetInfo.inc"
#endif

16
llvm/lib/Target/MBlaze/MCTargetDesc/Makefile Normal file
View File

@ -0,0 +1,16 @@
##===- lib/Target/MBlaze/TargetDesc/Makefile ---------------*- Makefile -*-===##
#
# The LLVM Compiler Infrastructure
#
# This file is distributed under the University of Illinois Open Source
# License. See LICENSE.TXT for details.
#
##===----------------------------------------------------------------------===##
LEVEL = ../../../..
LIBRARYNAME = LLVMMBlazeDesc
# Hack: we need to include 'main' target directory to grab private headers
CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/..
include $(LEVEL)/Makefile.common

2
llvm/lib/Target/MBlaze/Makefile
View File

@ -18,7 +18,7 @@ BUILT_SOURCES = MBlazeGenRegisterInfo.inc MBlazeGenInstrInfo.inc \
MBlazeGenSubtargetInfo.inc MBlazeGenIntrinsics.inc \
MBlazeGenEDInfo.inc
DIRS = InstPrinter AsmParser Disassembler TargetInfo
DIRS = InstPrinter AsmParser Disassembler TargetInfo MCTargetDesc
include $(LEVEL)/Makefile.common

1
llvm/lib/Target/MSP430/CMakeLists.txt
View File

@ -24,3 +24,4 @@ add_llvm_target(MSP430CodeGen
add_subdirectory(InstPrinter)
add_subdirectory(TargetInfo)
add_subdirectory(MCTargetDesc)

1
llvm/lib/Target/MSP430/MCTargetDesc/CMakeLists.txt Normal file
View File

@ -0,0 +1 @@
add_llvm_library(LLVMMSP430Desc MSP430MCTargetDesc.cpp)

53
llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp Normal file
View File

@ -0,0 +1,53 @@
//===-- MSP430MCTargetDesc.cpp - MSP430 Target Descriptions -----*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file provides MSP430 specific target descriptions.
//
//===----------------------------------------------------------------------===//
#include "MSP430MCTargetDesc.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/Target/TargetRegistry.h"
#define GET_INSTRINFO_MC_DESC
#include "MSP430GenInstrInfo.inc"
#define GET_SUBTARGETINFO_MC_DESC
#include "MSP430GenSubtargetInfo.inc"
#define GET_REGINFO_MC_DESC
#include "MSP430GenRegisterInfo.inc"
using namespace llvm;
MCInstrInfo *createMSP430MCInstrInfo() {
MCInstrInfo *X = new MCInstrInfo();
InitMSP430MCInstrInfo(X);
return X;
}
extern "C" void LLVMInitializeMSP430MCInstrInfo() {
TargetRegistry::RegisterMCInstrInfo(TheMSP430Target, createMSP430MCInstrInfo);
}
MCSubtargetInfo *createMSP430MCSubtargetInfo(StringRef TT, StringRef CPU,
StringRef FS) {
MCSubtargetInfo *X = new MCSubtargetInfo();
InitMSP430MCSubtargetInfo(X, TT, CPU, FS);
return X;
}
extern "C" void LLVMInitializeMSP430MCSubtargetInfo() {
TargetRegistry::RegisterMCSubtargetInfo(TheMSP430Target,
createMSP430MCSubtargetInfo);
}

38
llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.h Normal file
View File

@ -0,0 +1,38 @@
//===-- MSP430MCTargetDesc.h - MSP430 Target Descriptions -------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file provides MSP430 specific target descriptions.
//
//===----------------------------------------------------------------------===//
#ifndef ALPHAMCTARGETDESC_H
#define ALPHAMCTARGETDESC_H
namespace llvm {
class MCSubtargetInfo;
class Target;
class StringRef;
extern Target TheMSP430Target;
} // End llvm namespace
// Defines symbolic names for MSP430 registers.
// This defines a mapping from register name to register number.
#define GET_REGINFO_ENUM
#include "MSP430GenRegisterInfo.inc"
// Defines symbolic names for the MSP430 instructions.
#define GET_INSTRINFO_ENUM
#include "MSP430GenInstrInfo.inc"
#define GET_SUBTARGETINFO_ENUM
#include "MSP430GenSubtargetInfo.inc"
#endif

16
llvm/lib/Target/MSP430/MCTargetDesc/Makefile Normal file
View File

@ -0,0 +1,16 @@
##===- lib/Target/MSP430/TargetDesc/Makefile ---------------*- Makefile -*-===##
#
# The LLVM Compiler Infrastructure
#
# This file is distributed under the University of Illinois Open Source
# License. See LICENSE.TXT for details.
#
##===----------------------------------------------------------------------===##
LEVEL = ../../../..
LIBRARYNAME = LLVMMSP430Desc
# Hack: we need to include 'main' target directory to grab private headers
CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/..
include $(LEVEL)/Makefile.common

12
llvm/lib/Target/MSP430/MSP430.h
View File

@ -15,6 +15,7 @@
#ifndef LLVM_TARGET_MSP430_H
#define LLVM_TARGET_MSP430_H
#include "MCTargetDesc/MSP430MCTargetDesc.h"
#include "llvm/Target/TargetMachine.h"
namespace MSP430CC {
@ -41,17 +42,6 @@ namespace llvm {
FunctionPass *createMSP430BranchSelectionPass();
extern Target TheMSP430Target;
} // end namespace llvm;
// Defines symbolic names for MSP430 registers.
// This defines a mapping from register name to register number.
#define GET_REGINFO_ENUM
#include "MSP430GenRegisterInfo.inc"
// Defines symbolic names for the MSP430 instructions.
#define GET_INSTRINFO_ENUM
#include "MSP430GenInstrInfo.inc"
#endif

11
llvm/lib/Target/MSP430/MSP430InstrInfo.cpp
View File

@ -24,7 +24,6 @@
#include "llvm/Support/ErrorHandling.h"
#define GET_INSTRINFO_CTOR
#define GET_INSTRINFO_MC_DESC
#include "MSP430GenInstrInfo.inc"
using namespace llvm;
@ -335,13 +334,3 @@ unsigned MSP430InstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
return 6;
}
MCInstrInfo *createMSP430MCInstrInfo() {
MCInstrInfo *X = new MCInstrInfo();
InitMSP430MCInstrInfo(X);
return X;
}
extern "C" void LLVMInitializeMSP430MCInstrInfo() {
TargetRegistry::RegisterMCInstrInfo(TheMSP430Target, createMSP430MCInstrInfo);
}

1
llvm/lib/Target/MSP430/MSP430RegisterInfo.cpp
View File

@ -26,7 +26,6 @@
#include "llvm/ADT/BitVector.h"
#include "llvm/Support/ErrorHandling.h"
#define GET_REGINFO_MC_DESC
#define GET_REGINFO_TARGET_DESC
#include "MSP430GenRegisterInfo.inc"

14
llvm/lib/Target/MSP430/MSP430Subtarget.cpp
View File

@ -15,8 +15,6 @@
#include "MSP430.h"
#include "llvm/Target/TargetRegistry.h"
#define GET_SUBTARGETINFO_ENUM
#define GET_SUBTARGETINFO_MC_DESC
#define GET_SUBTARGETINFO_TARGET_DESC
#define GET_SUBTARGETINFO_CTOR
#include "MSP430GenSubtargetInfo.inc"
@ -32,15 +30,3 @@ MSP430Subtarget::MSP430Subtarget(const std::string &TT,
// Parse features string.
ParseSubtargetFeatures(CPUName, FS);
}
MCSubtargetInfo *createMSP430MCSubtargetInfo(StringRef TT, StringRef CPU,
StringRef FS) {
MCSubtargetInfo *X = new MCSubtargetInfo();
InitMSP430MCSubtargetInfo(X, TT, CPU, FS);
return X;
}
extern "C" void LLVMInitializeMSP430MCSubtargetInfo() {
TargetRegistry::RegisterMCSubtargetInfo(TheMSP430Target,
createMSP430MCSubtargetInfo);
}

2
llvm/lib/Target/MSP430/Makefile
View File

@ -17,7 +17,7 @@ BUILT_SOURCES = MSP430GenRegisterInfo.inc MSP430GenInstrInfo.inc \
MSP430GenDAGISel.inc MSP430GenCallingConv.inc \
MSP430GenSubtargetInfo.inc
DIRS = InstPrinter TargetInfo
DIRS = InstPrinter TargetInfo MCTargetDesc
include $(LEVEL)/Makefile.common

1
llvm/lib/Target/Mips/CMakeLists.txt
View File

@ -28,3 +28,4 @@ add_llvm_target(MipsCodeGen
add_subdirectory(InstPrinter)
add_subdirectory(TargetInfo)
add_subdirectory(MCTargetDesc)

1
llvm/lib/Target/Mips/MCTargetDesc/CMakeLists.txt Normal file
View File

@ -0,0 +1 @@
add_llvm_library(LLVMMipsDesc MipsMCTargetDesc.cpp)

16
llvm/lib/Target/Mips/MCTargetDesc/Makefile Normal file
View File

@ -0,0 +1,16 @@
##===- lib/Target/Mips/TargetDesc/Makefile -----------------*- Makefile -*-===##
#
# The LLVM Compiler Infrastructure
#
# This file is distributed under the University of Illinois Open Source
# License. See LICENSE.TXT for details.
#
##===----------------------------------------------------------------------===##
LEVEL = ../../../..
LIBRARYNAME = LLVMMipsDesc
# Hack: we need to include 'main' target directory to grab private headers
CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/..
include $(LEVEL)/Makefile.common

52
llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp Normal file
View File

@ -0,0 +1,52 @@
//===-- MipsMCTargetDesc.cpp - Mips Target Descriptions ---------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file provides Mips specific target descriptions.
//
//===----------------------------------------------------------------------===//
#include "MipsMCTargetDesc.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/Target/TargetRegistry.h"
#define GET_INSTRINFO_MC_DESC
#include "MipsGenInstrInfo.inc"
#define GET_SUBTARGETINFO_MC_DESC
#include "MipsGenSubtargetInfo.inc"
#define GET_REGINFO_MC_DESC
#include "MipsGenRegisterInfo.inc"
using namespace llvm;
MCInstrInfo *createMipsMCInstrInfo() {
MCInstrInfo *X = new MCInstrInfo();
InitMipsMCInstrInfo(X);
return X;
}
extern "C" void LLVMInitializeMipsMCInstrInfo() {
TargetRegistry::RegisterMCInstrInfo(TheMipsTarget, createMipsMCInstrInfo);
}
MCSubtargetInfo *createMipsMCSubtargetInfo(StringRef TT, StringRef CPU,
StringRef FS) {
MCSubtargetInfo *X = new MCSubtargetInfo();
InitMipsMCSubtargetInfo(X, TT, CPU, FS);
return X;
}
extern "C" void LLVMInitializeMipsMCSubtargetInfo() {
TargetRegistry::RegisterMCSubtargetInfo(TheMipsTarget,
createMipsMCSubtargetInfo);
}

39
llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h Normal file
View File

@ -0,0 +1,39 @@
//===-- AlphaMCTargetDesc.h - Alpha Target Descriptions ---------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file provides Alpha specific target descriptions.
//
//===----------------------------------------------------------------------===//
#ifndef ALPHAMCTARGETDESC_H
#define ALPHAMCTARGETDESC_H
namespace llvm {
class MCSubtargetInfo;
class Target;
class StringRef;
extern Target TheMipsTarget;
extern Target TheMipselTarget;
} // End llvm namespace
// Defines symbolic names for Mips registers. This defines a mapping from
// register name to register number.
#define GET_REGINFO_ENUM
#include "MipsGenRegisterInfo.inc"
// Defines symbolic names for the Mips instructions.
#define GET_INSTRINFO_ENUM
#include "MipsGenInstrInfo.inc"
#define GET_SUBTARGETINFO_ENUM
#include "MipsGenSubtargetInfo.inc"
#endif

2
llvm/lib/Target/Mips/Makefile
View File

@ -17,7 +17,7 @@ BUILT_SOURCES = MipsGenRegisterInfo.inc MipsGenInstrInfo.inc \
MipsGenDAGISel.inc MipsGenCallingConv.inc \
MipsGenSubtargetInfo.inc
DIRS = InstPrinter TargetInfo
DIRS = InstPrinter TargetInfo MCTargetDesc
include $(LEVEL)/Makefile.common

13
llvm/lib/Target/Mips/Mips.h
View File

@ -15,6 +15,7 @@
#ifndef TARGET_MIPS_H
#define TARGET_MIPS_H
#include "MCTargetDesc/MipsMCTargetDesc.h"
#include "llvm/Target/TargetMachine.h"
namespace llvm {
@ -28,18 +29,6 @@ namespace llvm {
FunctionPass *createMipsExpandPseudoPass(MipsTargetMachine &TM);
FunctionPass *createMipsEmitGPRestorePass(MipsTargetMachine &TM);
extern Target TheMipsTarget;
extern Target TheMipselTarget;
} // end namespace llvm;
// Defines symbolic names for Mips registers. This defines a mapping from
// register name to register number.
#define GET_REGINFO_ENUM
#include "MipsGenRegisterInfo.inc"
// Defines symbolic names for the Mips instructions.
#define GET_INSTRINFO_ENUM
#include "MipsGenInstrInfo.inc"
#endif

11
llvm/lib/Target/Mips/MipsInstrInfo.cpp
View File

@ -22,7 +22,6 @@
#include "llvm/ADT/STLExtras.h"
#define GET_INSTRINFO_CTOR
#define GET_INSTRINFO_MC_DESC
#include "MipsGenInstrInfo.inc"
using namespace llvm;
@ -460,13 +459,3 @@ unsigned MipsInstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
MipsFI->setGlobalBaseReg(GlobalBaseReg);
return GlobalBaseReg;
}
MCInstrInfo *createMipsMCInstrInfo() {
MCInstrInfo *X = new MCInstrInfo();
InitMipsMCInstrInfo(X);
return X;
}
extern "C" void LLVMInitializeMipsMCInstrInfo() {
TargetRegistry::RegisterMCInstrInfo(TheMipsTarget, createMipsMCInstrInfo);
}

1
llvm/lib/Target/Mips/MipsRegisterInfo.cpp
View File

@ -37,7 +37,6 @@
#include "llvm/ADT/STLExtras.h"
#include "llvm/Analysis/DebugInfo.h"
#define GET_REGINFO_MC_DESC
#define GET_REGINFO_TARGET_DESC
#include "MipsGenRegisterInfo.inc"

14
llvm/lib/Target/Mips/MipsSubtarget.cpp
View File

@ -15,8 +15,6 @@
#include "Mips.h"
#include "llvm/Target/TargetRegistry.h"
#define GET_SUBTARGETINFO_ENUM
#define GET_SUBTARGETINFO_MC_DESC
#define GET_SUBTARGETINFO_TARGET_DESC
#define GET_SUBTARGETINFO_CTOR
#include "MipsGenSubtargetInfo.inc"
@ -62,15 +60,3 @@ MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
HasCondMov = true;
}
}
MCSubtargetInfo *createMipsMCSubtargetInfo(StringRef TT, StringRef CPU,
StringRef FS) {
MCSubtargetInfo *X = new MCSubtargetInfo();
InitMipsMCSubtargetInfo(X, TT, CPU, FS);
return X;
}
extern "C" void LLVMInitializeMipsMCSubtargetInfo() {
TargetRegistry::RegisterMCSubtargetInfo(TheMipsTarget,
createMipsMCSubtargetInfo);
}

1
llvm/lib/Target/PTX/CMakeLists.txt
View File

@ -22,3 +22,4 @@ add_llvm_target(PTXCodeGen
)
add_subdirectory(TargetInfo)
add_subdirectory(MCTargetDesc)

1
llvm/lib/Target/PTX/MCTargetDesc/CMakeLists.txt Normal file
View File

@ -0,0 +1 @@
add_llvm_library(LLVMPTXDesc PTXMCTargetDesc.cpp)

16
llvm/lib/Target/PTX/MCTargetDesc/Makefile Normal file
View File

@ -0,0 +1,16 @@
##===- lib/Target/PTX/TargetDesc/Makefile ------------------*- Makefile -*-===##
#
# The LLVM Compiler Infrastructure
#
# This file is distributed under the University of Illinois Open Source
# License. See LICENSE.TXT for details.
#
##===----------------------------------------------------------------------===##
LEVEL = ../../../..
LIBRARYNAME = LLVMPTXDesc
# Hack: we need to include 'main' target directory to grab private headers
CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/..
include $(LEVEL)/Makefile.common

54
llvm/lib/Target/PTX/MCTargetDesc/PTXMCTargetDesc.cpp Normal file
View File

@ -0,0 +1,54 @@
//===-- PTXMCTargetDesc.cpp - PTX Target Descriptions -----------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file provides PTX specific target descriptions.
//
//===----------------------------------------------------------------------===//
#include "PTXMCTargetDesc.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/Target/TargetRegistry.h"
#define GET_INSTRINFO_MC_DESC
#include "PTXGenInstrInfo.inc"
#define GET_SUBTARGETINFO_MC_DESC
#include "PTXGenSubtargetInfo.inc"
#define GET_REGINFO_MC_DESC
#include "PTXGenRegisterInfo.inc"
using namespace llvm;
MCInstrInfo *createPTXMCInstrInfo() {
MCInstrInfo *X = new MCInstrInfo();
InitPTXMCInstrInfo(X);
return X;
}
extern "C" void LLVMInitializePTXMCInstrInfo() {
TargetRegistry::RegisterMCInstrInfo(ThePTX32Target, createPTXMCInstrInfo);
TargetRegistry::RegisterMCInstrInfo(ThePTX64Target, createPTXMCInstrInfo);
}
MCSubtargetInfo *createPTXMCSubtargetInfo(StringRef TT, StringRef CPU,
StringRef FS) {
MCSubtargetInfo *X = new MCSubtargetInfo();
InitPTXMCSubtargetInfo(X, TT, CPU, FS);
return X;
}
extern "C" void LLVMInitializePTXMCSubtargetInfo() {
TargetRegistry::RegisterMCSubtargetInfo(ThePTX32Target,
createPTXMCSubtargetInfo);
TargetRegistry::RegisterMCSubtargetInfo(ThePTX64Target,
createPTXMCSubtargetInfo);
}

38
llvm/lib/Target/PTX/MCTargetDesc/PTXMCTargetDesc.h Normal file
View File

@ -0,0 +1,38 @@
//===-- PTXMCTargetDesc.h - PTX Target Descriptions ------------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file provides PTX specific target descriptions.
//
//===----------------------------------------------------------------------===//
#ifndef PTXMCTARGETDESC_H
#define PTXMCTARGETDESC_H
namespace llvm {
class MCSubtargetInfo;
class Target;
class StringRef;
extern Target ThePTX32Target;
extern Target ThePTX64Target;
} // End llvm namespace
// Defines symbolic names for PTX registers.
#define GET_REGINFO_ENUM
#include "PTXGenRegisterInfo.inc"
// Defines symbolic names for the PTX instructions.
#define GET_INSTRINFO_ENUM
#include "PTXGenInstrInfo.inc"
#define GET_SUBTARGETINFO_ENUM
#include "PTXGenSubtargetInfo.inc"
#endif

2
llvm/lib/Target/PTX/Makefile
View File

@ -19,6 +19,6 @@ BUILT_SOURCES = PTXGenAsmWriter.inc \
PTXGenRegisterInfo.inc \
PTXGenSubtargetInfo.inc
DIRS = TargetInfo
DIRS = TargetInfo MCTargetDesc
include $(LEVEL)/Makefile.common

11
llvm/lib/Target/PTX/PTX.h
View File

@ -15,6 +15,7 @@
#ifndef PTX_H
#define PTX_H
#include "MCTargetDesc/PTXMCTargetDesc.h"
#include "llvm/Target/TargetMachine.h"
namespace llvm {
@ -42,16 +43,6 @@ namespace llvm {
FunctionPass *createPTXMFInfoExtract(PTXTargetMachine &TM,
CodeGenOpt::Level OptLevel);
extern Target ThePTX32Target;
extern Target ThePTX64Target;
} // namespace llvm;
// Defines symbolic names for PTX registers.
#define GET_REGINFO_ENUM
#include "PTXGenRegisterInfo.inc"
// Defines symbolic names for the PTX instructions.
#define GET_INSTRINFO_ENUM
#include "PTXGenInstrInfo.inc"
#endif // PTX_H

12
llvm/lib/Target/PTX/PTXInstrInfo.cpp
View File

@ -23,7 +23,6 @@
#include "llvm/Support/raw_ostream.h"
#define GET_INSTRINFO_CTOR
#define GET_INSTRINFO_MC_DESC
#include "PTXGenInstrInfo.inc"
using namespace llvm;
@ -409,14 +408,3 @@ MachineBasicBlock *PTXInstrInfo::GetBranchTarget(const MachineInstr& inst) {
assert(target.isMBB() && "FIXME: detect branch target operand");
return target.getMBB();
}
MCInstrInfo *createPTXMCInstrInfo() {
MCInstrInfo *X = new MCInstrInfo();
InitPTXMCInstrInfo(X);
return X;
}
extern "C" void LLVMInitializePTXMCInstrInfo() {
TargetRegistry::RegisterMCInstrInfo(ThePTX32Target, createPTXMCInstrInfo);
TargetRegistry::RegisterMCInstrInfo(ThePTX64Target, createPTXMCInstrInfo);
}

1
llvm/lib/Target/PTX/PTXRegisterInfo.cpp
View File

@ -17,7 +17,6 @@
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
#define GET_REGINFO_MC_DESC
#define GET_REGINFO_TARGET_DESC
#include "PTXGenRegisterInfo.inc"

17
llvm/lib/Target/PTX/PTXSubtarget.cpp
View File

@ -16,8 +16,6 @@
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Target/TargetRegistry.h"
#define GET_SUBTARGETINFO_ENUM
#define GET_SUBTARGETINFO_MC_DESC
#define GET_SUBTARGETINFO_TARGET_DESC
#define GET_SUBTARGETINFO_CTOR
#include "PTXGenSubtargetInfo.inc"
@ -66,18 +64,3 @@ std::string PTXSubtarget::getPTXVersionString() const {
case PTX_VERSION_2_3: return "2.3";
}
}
MCSubtargetInfo *createPTXMCSubtargetInfo(StringRef TT, StringRef CPU,
StringRef FS) {
MCSubtargetInfo *X = new MCSubtargetInfo();
InitPTXMCSubtargetInfo(X, TT, CPU, FS);
return X;
}
extern "C" void LLVMInitializePTXMCSubtargetInfo() {
TargetRegistry::RegisterMCSubtargetInfo(ThePTX32Target,
createPTXMCSubtargetInfo);
TargetRegistry::RegisterMCSubtargetInfo(ThePTX64Target,
createPTXMCSubtargetInfo);
}

1
llvm/lib/Target/PowerPC/CMakeLists.txt
View File

@ -32,3 +32,4 @@ add_llvm_target(PowerPCCodeGen
add_subdirectory(InstPrinter)
add_subdirectory(TargetInfo)
add_subdirectory(MCTargetDesc)

1
llvm/lib/Target/PowerPC/MCTargetDesc/CMakeLists.txt Normal file
View File

@ -0,0 +1 @@
add_llvm_library(LLVMPowerPCDesc PPCMCTargetDesc.cpp)

16
llvm/lib/Target/PowerPC/MCTargetDesc/Makefile Normal file
View File

@ -0,0 +1,16 @@
##===- lib/Target/PowerPC/TargetDesc/Makefile --------------*- Makefile -*-===##
#
# The LLVM Compiler Infrastructure
#
# This file is distributed under the University of Illinois Open Source
# License. See LICENSE.TXT for details.
#
##===----------------------------------------------------------------------===##
LEVEL = ../../../..
LIBRARYNAME = LLVMPowerPCDesc
# Hack: we need to include 'main' target directory to grab private headers
CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/..
include $(LEVEL)/Makefile.common

55
llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp Normal file
View File

@ -0,0 +1,55 @@
//===-- PPCMCTargetDesc.cpp - PowerPC Target Descriptions -------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file provides PowerPC specific target descriptions.
//
//===----------------------------------------------------------------------===//
#include "PPCMCTargetDesc.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/Target/TargetRegistry.h"
#define GET_INSTRINFO_MC_DESC
#include "PPCGenInstrInfo.inc"
#define GET_SUBTARGETINFO_MC_DESC
#include "PPCGenSubtargetInfo.inc"
#define GET_REGINFO_MC_DESC
#include "PPCGenRegisterInfo.inc"
using namespace llvm;
MCInstrInfo *createPPCMCInstrInfo() {
MCInstrInfo *X = new MCInstrInfo();
InitPPCMCInstrInfo(X);
return X;
}
extern "C" void LLVMInitializePowerPCMCInstrInfo() {
TargetRegistry::RegisterMCInstrInfo(ThePPC32Target, createPPCMCInstrInfo);
TargetRegistry::RegisterMCInstrInfo(ThePPC64Target, createPPCMCInstrInfo);
}
MCSubtargetInfo *createPPCMCSubtargetInfo(StringRef TT, StringRef CPU,
StringRef FS) {
MCSubtargetInfo *X = new MCSubtargetInfo();
InitPPCMCSubtargetInfo(X, TT, CPU, FS);
return X;
}
extern "C" void LLVMInitializePowerPCMCSubtargetInfo() {
TargetRegistry::RegisterMCSubtargetInfo(ThePPC32Target,
createPPCMCSubtargetInfo);
TargetRegistry::RegisterMCSubtargetInfo(ThePPC64Target,
createPPCMCSubtargetInfo);
}

41
llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h Normal file
View File

@ -0,0 +1,41 @@
//===-- PPCMCTargetDesc.h - PowerPC Target Descriptions ---------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file provides PowerPC specific target descriptions.
//
//===----------------------------------------------------------------------===//
#ifndef PPCMCTARGETDESC_H
#define PPCMCTARGETDESC_H
namespace llvm {
class MCSubtargetInfo;
class Target;
class StringRef;
extern Target ThePPC32Target;
extern Target ThePPC64Target;
} // End llvm namespace
// Defines symbolic names for PowerPC registers. This defines a mapping from
// register name to register number.
//
#define GET_REGINFO_ENUM
#include "PPCGenRegisterInfo.inc"
// Defines symbolic names for the PowerPC instructions.
//
#define GET_INSTRINFO_ENUM
#include "PPCGenInstrInfo.inc"
#define GET_SUBTARGETINFO_ENUM
#include "PPCGenSubtargetInfo.inc"
#endif

2
llvm/lib/Target/PowerPC/Makefile
View File

@ -18,6 +18,6 @@ BUILT_SOURCES = PPCGenRegisterInfo.inc \
PPCGenSubtargetInfo.inc PPCGenCallingConv.inc \
PPCGenMCCodeEmitter.inc
DIRS = InstPrinter TargetInfo
DIRS = InstPrinter TargetInfo MCTargetDesc
include $(LEVEL)/Makefile.common

15
llvm/lib/Target/PowerPC/PPC.h
View File

@ -15,6 +15,7 @@
#ifndef LLVM_TARGET_POWERPC_H
#define LLVM_TARGET_POWERPC_H
#include "MCTargetDesc/PPCMCTargetDesc.h"
#include <string>
// GCC #defines PPC on Linux but we use it as our namespace name
@ -48,9 +49,6 @@ namespace llvm {
void LowerPPCMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
AsmPrinter &AP, bool isDarwin);
extern Target ThePPC32Target;
extern Target ThePPC64Target;
namespace PPCII {
/// Target Operand Flag enum.
@ -84,15 +82,4 @@ namespace llvm {
} // end namespace llvm;
// Defines symbolic names for PowerPC registers. This defines a mapping from
// register name to register number.
//
#define GET_REGINFO_ENUM
#include "PPCGenRegisterInfo.inc"
// Defines symbolic names for the PowerPC instructions.
//
#define GET_INSTRINFO_ENUM
#include "PPCGenInstrInfo.inc"
#endif

12
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
View File

@ -31,7 +31,6 @@
#include "llvm/ADT/STLExtras.h"
#define GET_INSTRINFO_CTOR
#define GET_INSTRINFO_MC_DESC
#include "PPCGenInstrInfo.inc"
namespace llvm {
@ -654,14 +653,3 @@ unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
return 4; // PowerPC instructions are all 4 bytes
}
}
MCInstrInfo *createPPCMCInstrInfo() {
MCInstrInfo *X = new MCInstrInfo();
InitPPCMCInstrInfo(X);
return X;
}
extern "C" void LLVMInitializePowerPCMCInstrInfo() {
TargetRegistry::RegisterMCInstrInfo(ThePPC32Target, createPPCMCInstrInfo);
TargetRegistry::RegisterMCInstrInfo(ThePPC64Target, createPPCMCInstrInfo);
}

1
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
View File

@ -44,7 +44,6 @@
#include "llvm/ADT/STLExtras.h"
#include <cstdlib>
#define GET_REGINFO_MC_DESC
#define GET_REGINFO_TARGET_DESC
#include "PPCGenRegisterInfo.inc"

16
llvm/lib/Target/PowerPC/PPCSubtarget.cpp
View File

@ -18,8 +18,6 @@
#include "llvm/Target/TargetRegistry.h"
#include <cstdlib>
#define GET_SUBTARGETINFO_ENUM
#define GET_SUBTARGETINFO_MC_DESC
#define GET_SUBTARGETINFO_TARGET_DESC
#define GET_SUBTARGETINFO_CTOR
#include "PPCGenSubtargetInfo.inc"
@ -141,17 +139,3 @@ bool PPCSubtarget::hasLazyResolverStub(const GlobalValue *GV,
return GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
GV->hasCommonLinkage() || isDecl;
}
MCSubtargetInfo *createPPCMCSubtargetInfo(StringRef TT, StringRef CPU,
StringRef FS) {
MCSubtargetInfo *X = new MCSubtargetInfo();
InitPPCMCSubtargetInfo(X, TT, CPU, FS);
return X;
}
extern "C" void LLVMInitializePowerPCMCSubtargetInfo() {
TargetRegistry::RegisterMCSubtargetInfo(ThePPC32Target,
createPPCMCSubtargetInfo);
TargetRegistry::RegisterMCSubtargetInfo(ThePPC64Target,
createPPCMCSubtargetInfo);
}

1
llvm/lib/Target/Sparc/CMakeLists.txt
View File

@ -23,3 +23,4 @@ add_llvm_target(SparcCodeGen
)
add_subdirectory(TargetInfo)
add_subdirectory(MCTargetDesc)

1
llvm/lib/Target/Sparc/MCTargetDesc/CMakeLists.txt Normal file
View File

@ -0,0 +1 @@
add_llvm_library(LLVMSparcDesc SparcMCTargetDesc.cpp)

16
llvm/lib/Target/Sparc/MCTargetDesc/Makefile Normal file
View File

@ -0,0 +1,16 @@
##===- lib/Target/Sparc/TargetDesc/Makefile ----------------*- Makefile -*-===##
#
# The LLVM Compiler Infrastructure
#
# This file is distributed under the University of Illinois Open Source
# License. See LICENSE.TXT for details.
#
##===----------------------------------------------------------------------===##
LEVEL = ../../../..
LIBRARYNAME = LLVMSparcDesc
# Hack: we need to include 'main' target directory to grab private headers
CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/..
include $(LEVEL)/Makefile.common

51
llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp Normal file
View File

@ -0,0 +1,51 @@
//===-- SparcMCTargetDesc.cpp - Sparc Target Descriptions --------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file provides Sparc specific target descriptions.
//
//===----------------------------------------------------------------------===//
#include "SparcMCTargetDesc.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/Target/TargetRegistry.h"
#define GET_INSTRINFO_MC_DESC
#include "SparcGenInstrInfo.inc"
#define GET_SUBTARGETINFO_MC_DESC
#include "SparcGenSubtargetInfo.inc"
#define GET_REGINFO_MC_DESC
#include "SparcGenRegisterInfo.inc"
using namespace llvm;
MCInstrInfo *createSparcMCInstrInfo() {
MCInstrInfo *X = new MCInstrInfo();
InitSparcMCInstrInfo(X);
return X;
}
extern "C" void LLVMInitializeSparcMCInstrInfo() {
TargetRegistry::RegisterMCInstrInfo(TheSparcTarget, createSparcMCInstrInfo);
}
MCSubtargetInfo *createSparcMCSubtargetInfo(StringRef TT, StringRef CPU,
StringRef FS) {
MCSubtargetInfo *X = new MCSubtargetInfo();
InitSparcMCSubtargetInfo(X, TT, CPU, FS);
return X;
}
extern "C" void LLVMInitializeSparcMCSubtargetInfo() {
TargetRegistry::RegisterMCSubtargetInfo(TheSparcTarget,
createSparcMCSubtargetInfo);
}

41
llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h Normal file
View File

@ -0,0 +1,41 @@
//===-- SparcMCTargetDesc.h - Sparc Target Descriptions ---------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file provides Sparc specific target descriptions.
//
//===----------------------------------------------------------------------===//
#ifndef SPARCMCTARGETDESC_H
#define SPARCMCTARGETDESC_H
namespace llvm {
class MCSubtargetInfo;
class Target;
class StringRef;
extern Target TheSparcTarget;
extern Target TheSparcV9Target;
} // End llvm namespace
// Defines symbolic names for Sparc registers. This defines a mapping from
// register name to register number.
//
#define GET_REGINFO_ENUM
#include "SparcGenRegisterInfo.inc"
// Defines symbolic names for the Sparc instructions.
//
#define GET_INSTRINFO_ENUM
#include "SparcGenInstrInfo.inc"
#define GET_SUBTARGETINFO_ENUM
#include "SparcGenSubtargetInfo.inc"
#endif

2
llvm/lib/Target/Sparc/Makefile
View File

@ -16,7 +16,7 @@ BUILT_SOURCES = SparcGenRegisterInfo.inc SparcGenInstrInfo.inc \
SparcGenAsmWriter.inc SparcGenDAGISel.inc \
SparcGenSubtargetInfo.inc SparcGenCallingConv.inc
DIRS = TargetInfo
DIRS = TargetInfo MCTargetDesc
include $(LEVEL)/Makefile.common

Some files were not shown because too many files have changed in this diff Show More