From bc153d49b73d493b1fe28cfac108f2d69ba56cee Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Thu, 14 Jul 2011 20:59:42 +0000 Subject: [PATCH] Next round of MC refactoring. This patch factor MC table instantiations, MC registeration and creation code into XXXMCDesc libraries. llvm-svn: 135184 --- llvm/lib/Target/ARM/ARM.h | 3 +- llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 1 - llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp | 1 - llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp | 3 - llvm/lib/Target/ARM/ARMSubtarget.cpp | 2 - .../lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 3 - .../ARM/Disassembler/ARMDisassemblerCore.cpp | 7 ++- .../ARM/MCTargetDesc/ARMMCTargetDesc.cpp | 1 - .../Target/ARM/MCTargetDesc/ARMMCTargetDesc.h | 3 + llvm/lib/Target/Alpha/Alpha.h | 15 +---- llvm/lib/Target/Alpha/AlphaInstrInfo.cpp | 11 ---- llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp | 1 - llvm/lib/Target/Alpha/AlphaSubtarget.cpp | 14 ----- llvm/lib/Target/Alpha/CMakeLists.txt | 1 + .../Alpha/MCTargetDesc/AlphaMCTargetDesc.cpp | 53 ++++++++++++++++++ .../Alpha/MCTargetDesc/AlphaMCTargetDesc.h | 40 ++++++++++++++ .../Target/Alpha/MCTargetDesc/CMakeLists.txt | 1 + llvm/lib/Target/Alpha/MCTargetDesc/Makefile | 16 ++++++ llvm/lib/Target/Alpha/Makefile | 2 +- llvm/lib/Target/Blackfin/Blackfin.h | 11 +--- .../lib/Target/Blackfin/BlackfinInstrInfo.cpp | 12 ---- .../Target/Blackfin/BlackfinRegisterInfo.cpp | 1 - .../lib/Target/Blackfin/BlackfinSubtarget.cpp | 14 ----- llvm/lib/Target/Blackfin/CMakeLists.txt | 1 + .../MCTargetDesc/BlackfinMCTargetDesc.cpp | 54 ++++++++++++++++++ .../MCTargetDesc/BlackfinMCTargetDesc.h | 38 +++++++++++++ .../Blackfin/MCTargetDesc/CMakeLists.txt | 1 + .../lib/Target/Blackfin/MCTargetDesc/Makefile | 16 ++++++ llvm/lib/Target/Blackfin/Makefile | 2 +- llvm/lib/Target/CellSPU/CMakeLists.txt | 1 + .../CellSPU/MCTargetDesc/CMakeLists.txt | 1 + llvm/lib/Target/CellSPU/MCTargetDesc/Makefile | 16 ++++++ .../CellSPU/MCTargetDesc/SPUMCTargetDesc.cpp | 51 +++++++++++++++++ .../CellSPU/MCTargetDesc/SPUMCTargetDesc.h | 40 ++++++++++++++ llvm/lib/Target/CellSPU/Makefile | 2 +- llvm/lib/Target/CellSPU/SPU.h | 7 +-- llvm/lib/Target/CellSPU/SPUFrameLowering.cpp | 1 - llvm/lib/Target/CellSPU/SPUISelDAGToDAG.cpp | 1 - llvm/lib/Target/CellSPU/SPUISelLowering.cpp | 1 - llvm/lib/Target/CellSPU/SPUInstrInfo.cpp | 12 ---- llvm/lib/Target/CellSPU/SPURegisterInfo.cpp | 2 - llvm/lib/Target/CellSPU/SPUSubtarget.cpp | 14 ----- llvm/lib/Target/CellSPU/SPUTargetMachine.cpp | 1 - llvm/lib/Target/MBlaze/CMakeLists.txt | 1 + .../Disassembler/MBlazeDisassembler.cpp | 6 +- llvm/lib/Target/MBlaze/MBlaze.h | 11 +--- llvm/lib/Target/MBlaze/MBlazeInstrInfo.cpp | 11 ---- llvm/lib/Target/MBlaze/MBlazeRegisterInfo.cpp | 1 - llvm/lib/Target/MBlaze/MBlazeSubtarget.cpp | 14 ----- .../Target/MBlaze/MCTargetDesc/CMakeLists.txt | 1 + .../MCTargetDesc/MBlazeMCTargetDesc.cpp | 52 ++++++++++++++++++ .../MBlaze/MCTargetDesc/MBlazeMCTargetDesc.h | 38 +++++++++++++ llvm/lib/Target/MBlaze/MCTargetDesc/Makefile | 16 ++++++ llvm/lib/Target/MBlaze/Makefile | 2 +- llvm/lib/Target/MSP430/CMakeLists.txt | 1 + .../Target/MSP430/MCTargetDesc/CMakeLists.txt | 1 + .../MCTargetDesc/MSP430MCTargetDesc.cpp | 53 ++++++++++++++++++ .../MSP430/MCTargetDesc/MSP430MCTargetDesc.h | 38 +++++++++++++ llvm/lib/Target/MSP430/MCTargetDesc/Makefile | 16 ++++++ llvm/lib/Target/MSP430/MSP430.h | 12 +--- llvm/lib/Target/MSP430/MSP430InstrInfo.cpp | 11 ---- llvm/lib/Target/MSP430/MSP430RegisterInfo.cpp | 1 - llvm/lib/Target/MSP430/MSP430Subtarget.cpp | 14 ----- llvm/lib/Target/MSP430/Makefile | 2 +- llvm/lib/Target/Mips/CMakeLists.txt | 1 + .../Target/Mips/MCTargetDesc/CMakeLists.txt | 1 + llvm/lib/Target/Mips/MCTargetDesc/Makefile | 16 ++++++ .../Mips/MCTargetDesc/MipsMCTargetDesc.cpp | 52 ++++++++++++++++++ .../Mips/MCTargetDesc/MipsMCTargetDesc.h | 39 +++++++++++++ llvm/lib/Target/Mips/Makefile | 2 +- llvm/lib/Target/Mips/Mips.h | 13 +---- llvm/lib/Target/Mips/MipsInstrInfo.cpp | 11 ---- llvm/lib/Target/Mips/MipsRegisterInfo.cpp | 1 - llvm/lib/Target/Mips/MipsSubtarget.cpp | 14 ----- llvm/lib/Target/PTX/CMakeLists.txt | 1 + .../Target/PTX/MCTargetDesc/CMakeLists.txt | 1 + llvm/lib/Target/PTX/MCTargetDesc/Makefile | 16 ++++++ .../PTX/MCTargetDesc/PTXMCTargetDesc.cpp | 54 ++++++++++++++++++ .../Target/PTX/MCTargetDesc/PTXMCTargetDesc.h | 38 +++++++++++++ llvm/lib/Target/PTX/Makefile | 2 +- llvm/lib/Target/PTX/PTX.h | 11 +--- llvm/lib/Target/PTX/PTXInstrInfo.cpp | 12 ---- llvm/lib/Target/PTX/PTXRegisterInfo.cpp | 1 - llvm/lib/Target/PTX/PTXSubtarget.cpp | 17 ------ llvm/lib/Target/PowerPC/CMakeLists.txt | 1 + .../PowerPC/MCTargetDesc/CMakeLists.txt | 1 + llvm/lib/Target/PowerPC/MCTargetDesc/Makefile | 16 ++++++ .../PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp | 55 +++++++++++++++++++ .../PowerPC/MCTargetDesc/PPCMCTargetDesc.h | 41 ++++++++++++++ llvm/lib/Target/PowerPC/Makefile | 2 +- llvm/lib/Target/PowerPC/PPC.h | 15 +---- llvm/lib/Target/PowerPC/PPCInstrInfo.cpp | 12 ---- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp | 1 - llvm/lib/Target/PowerPC/PPCSubtarget.cpp | 16 ------ llvm/lib/Target/Sparc/CMakeLists.txt | 1 + .../Target/Sparc/MCTargetDesc/CMakeLists.txt | 1 + llvm/lib/Target/Sparc/MCTargetDesc/Makefile | 16 ++++++ .../Sparc/MCTargetDesc/SparcMCTargetDesc.cpp | 51 +++++++++++++++++ .../Sparc/MCTargetDesc/SparcMCTargetDesc.h | 41 ++++++++++++++ llvm/lib/Target/Sparc/Makefile | 2 +- llvm/lib/Target/Sparc/Sparc.h | 16 +----- llvm/lib/Target/Sparc/SparcInstrInfo.cpp | 11 ---- llvm/lib/Target/Sparc/SparcRegisterInfo.cpp | 1 - llvm/lib/Target/Sparc/SparcSubtarget.cpp | 14 ----- llvm/lib/Target/SystemZ/CMakeLists.txt | 1 + .../SystemZ/MCTargetDesc/CMakeLists.txt | 1 + llvm/lib/Target/SystemZ/MCTargetDesc/Makefile | 16 ++++++ .../MCTargetDesc/SystemZMCTargetDesc.cpp | 52 ++++++++++++++++++ .../MCTargetDesc/SystemZMCTargetDesc.h | 38 +++++++++++++ llvm/lib/Target/SystemZ/Makefile | 2 +- llvm/lib/Target/SystemZ/SystemZ.h | 13 +---- llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp | 12 ---- .../Target/SystemZ/SystemZRegisterInfo.cpp | 1 - llvm/lib/Target/SystemZ/SystemZSubtarget.cpp | 14 ----- .../lib/Target/X86/AsmParser/X86AsmParser.cpp | 3 - .../X86/MCTargetDesc/X86MCTargetDesc.cpp | 1 - .../Target/X86/MCTargetDesc/X86MCTargetDesc.h | 3 + llvm/lib/Target/X86/X86InstrInfo.cpp | 1 - llvm/lib/Target/X86/X86MCCodeEmitter.cpp | 3 - llvm/lib/Target/X86/X86RegisterInfo.cpp | 1 - llvm/lib/Target/X86/X86Subtarget.cpp | 2 - llvm/lib/Target/XCore/CMakeLists.txt | 1 + .../Target/XCore/MCTargetDesc/CMakeLists.txt | 1 + llvm/lib/Target/XCore/MCTargetDesc/Makefile | 16 ++++++ .../XCore/MCTargetDesc/XCoreMCTargetDesc.cpp | 51 +++++++++++++++++ .../XCore/MCTargetDesc/XCoreMCTargetDesc.h | 40 ++++++++++++++ llvm/lib/Target/XCore/Makefile | 2 +- llvm/lib/Target/XCore/XCore.h | 14 +---- llvm/lib/Target/XCore/XCoreInstrInfo.cpp | 11 ---- llvm/lib/Target/XCore/XCoreRegisterInfo.cpp | 1 - llvm/lib/Target/XCore/XCoreSubtarget.cpp | 15 ----- llvm/utils/TableGen/InstrInfoEmitter.cpp | 4 +- llvm/utils/TableGen/RegisterInfoEmitter.cpp | 21 ++++--- llvm/utils/TableGen/SubtargetEmitter.cpp | 42 +++++++++----- 134 files changed, 1285 insertions(+), 495 deletions(-) create mode 100644 llvm/lib/Target/Alpha/MCTargetDesc/AlphaMCTargetDesc.cpp create mode 100644 llvm/lib/Target/Alpha/MCTargetDesc/AlphaMCTargetDesc.h create mode 100644 llvm/lib/Target/Alpha/MCTargetDesc/CMakeLists.txt create mode 100644 llvm/lib/Target/Alpha/MCTargetDesc/Makefile create mode 100644 llvm/lib/Target/Blackfin/MCTargetDesc/BlackfinMCTargetDesc.cpp create mode 100644 llvm/lib/Target/Blackfin/MCTargetDesc/BlackfinMCTargetDesc.h create mode 100644 llvm/lib/Target/Blackfin/MCTargetDesc/CMakeLists.txt create mode 100644 llvm/lib/Target/Blackfin/MCTargetDesc/Makefile create mode 100644 llvm/lib/Target/CellSPU/MCTargetDesc/CMakeLists.txt create mode 100644 llvm/lib/Target/CellSPU/MCTargetDesc/Makefile create mode 100644 llvm/lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.cpp create mode 100644 llvm/lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.h create mode 100644 llvm/lib/Target/MBlaze/MCTargetDesc/CMakeLists.txt create mode 100644 llvm/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp create mode 100644 llvm/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.h create mode 100644 llvm/lib/Target/MBlaze/MCTargetDesc/Makefile create mode 100644 llvm/lib/Target/MSP430/MCTargetDesc/CMakeLists.txt create mode 100644 llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp create mode 100644 llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.h create mode 100644 llvm/lib/Target/MSP430/MCTargetDesc/Makefile create mode 100644 llvm/lib/Target/Mips/MCTargetDesc/CMakeLists.txt create mode 100644 llvm/lib/Target/Mips/MCTargetDesc/Makefile create mode 100644 llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp create mode 100644 llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h create mode 100644 llvm/lib/Target/PTX/MCTargetDesc/CMakeLists.txt create mode 100644 llvm/lib/Target/PTX/MCTargetDesc/Makefile create mode 100644 llvm/lib/Target/PTX/MCTargetDesc/PTXMCTargetDesc.cpp create mode 100644 llvm/lib/Target/PTX/MCTargetDesc/PTXMCTargetDesc.h create mode 100644 llvm/lib/Target/PowerPC/MCTargetDesc/CMakeLists.txt create mode 100644 llvm/lib/Target/PowerPC/MCTargetDesc/Makefile create mode 100644 llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp create mode 100644 llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h create mode 100644 llvm/lib/Target/Sparc/MCTargetDesc/CMakeLists.txt create mode 100644 llvm/lib/Target/Sparc/MCTargetDesc/Makefile create mode 100644 llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp create mode 100644 llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h create mode 100644 llvm/lib/Target/SystemZ/MCTargetDesc/CMakeLists.txt create mode 100644 llvm/lib/Target/SystemZ/MCTargetDesc/Makefile create mode 100644 llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp create mode 100644 llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h create mode 100644 llvm/lib/Target/XCore/MCTargetDesc/CMakeLists.txt create mode 100644 llvm/lib/Target/XCore/MCTargetDesc/Makefile create mode 100644 llvm/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp create mode 100644 llvm/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.h diff --git a/llvm/lib/Target/ARM/ARM.h b/llvm/lib/Target/ARM/ARM.h index 267ee52d3f91..08dc340f8541 100644 --- a/llvm/lib/Target/ARM/ARM.h +++ b/llvm/lib/Target/ARM/ARM.h @@ -16,6 +16,7 @@ #define TARGET_ARM_H #include "ARMBaseInfo.h" +#include "MCTargetDesc/ARMMCTargetDesc.h" #include "llvm/Support/DataTypes.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Target/TargetMachine.h" @@ -57,8 +58,6 @@ FunctionPass *createMLxExpansionPass(); FunctionPass *createThumb2ITBlockPass(); FunctionPass *createThumb2SizeReductionPass(); -extern Target TheARMTarget, TheThumbTarget; - void LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, ARMAsmPrinter &AP); diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp index 2c5212aed0e5..c5d588484115 100644 --- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -36,7 +36,6 @@ #include "llvm/Support/ErrorHandling.h" #include "llvm/ADT/STLExtras.h" -#define GET_INSTRINFO_MC_DESC #define GET_INSTRINFO_CTOR #include "ARMGenInstrInfo.inc" diff --git a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp index e46082d23646..ba422952ac1a 100644 --- a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp +++ b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp @@ -40,7 +40,6 @@ #include "llvm/ADT/SmallVector.h" #include "llvm/Support/CommandLine.h" -#define GET_REGINFO_MC_DESC #define GET_REGINFO_TARGET_DESC #include "ARMGenRegisterInfo.inc" diff --git a/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp b/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp index aea1d1d145ae..39be3f0e39f8 100644 --- a/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp +++ b/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp @@ -26,9 +26,6 @@ #include "llvm/ADT/Statistic.h" #include "llvm/Support/raw_ostream.h" -#define GET_SUBTARGETINFO_ENUM -#include "ARMGenSubtargetInfo.inc" - using namespace llvm; STATISTIC(MCNumEmitted, "Number of MC instructions emitted."); diff --git a/llvm/lib/Target/ARM/ARMSubtarget.cpp b/llvm/lib/Target/ARM/ARMSubtarget.cpp index f4fca351d449..1cab9e44ce75 100644 --- a/llvm/lib/Target/ARM/ARMSubtarget.cpp +++ b/llvm/lib/Target/ARM/ARMSubtarget.cpp @@ -18,8 +18,6 @@ #include "llvm/Support/CommandLine.h" #include "llvm/ADT/SmallVector.h" -#define GET_SUBTARGETINFO_ENUM -#define GET_SUBTARGETINFO_MC_DESC #define GET_SUBTARGETINFO_TARGET_DESC #define GET_SUBTARGETINFO_CTOR #include "ARMGenSubtargetInfo.inc" diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index 6783bc3da025..bdcdd7966ebd 100644 --- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -31,9 +31,6 @@ #include "llvm/ADT/StringSwitch.h" #include "llvm/ADT/Twine.h" -#define GET_SUBTARGETINFO_ENUM -#include "ARMGenSubtargetInfo.inc" - using namespace llvm; namespace { diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp index 581d877a2030..d671c0bdfaa0 100644 --- a/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp +++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp @@ -70,9 +70,10 @@ /// /// { ARM::CCRRegClassID, 0|(1<setGlobalRetAddr(GlobalRetAddr); return GlobalRetAddr; } - -MCInstrInfo *createAlphaMCInstrInfo() { - MCInstrInfo *X = new MCInstrInfo(); - InitAlphaMCInstrInfo(X); - return X; -} - -extern "C" void LLVMInitializeAlphaMCInstrInfo() { - TargetRegistry::RegisterMCInstrInfo(TheAlphaTarget, createAlphaMCInstrInfo); -} diff --git a/llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp b/llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp index 028930786465..df8f157266e1 100644 --- a/llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp +++ b/llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp @@ -34,7 +34,6 @@ #include "llvm/ADT/STLExtras.h" #include -#define GET_REGINFO_MC_DESC #define GET_REGINFO_TARGET_DESC #include "AlphaGenRegisterInfo.inc" diff --git a/llvm/lib/Target/Alpha/AlphaSubtarget.cpp b/llvm/lib/Target/Alpha/AlphaSubtarget.cpp index d559d7c54975..624a5e2ebd09 100644 --- a/llvm/lib/Target/Alpha/AlphaSubtarget.cpp +++ b/llvm/lib/Target/Alpha/AlphaSubtarget.cpp @@ -15,8 +15,6 @@ #include "Alpha.h" #include "llvm/Target/TargetRegistry.h" -#define GET_SUBTARGETINFO_ENUM -#define GET_SUBTARGETINFO_MC_DESC #define GET_SUBTARGETINFO_TARGET_DESC #define GET_SUBTARGETINFO_CTOR #include "AlphaGenSubtargetInfo.inc" @@ -36,15 +34,3 @@ AlphaSubtarget::AlphaSubtarget(const std::string &TT, const std::string &CPU, // Initialize scheduling itinerary for the specified CPU. InstrItins = getInstrItineraryForCPU(CPUName); } - -MCSubtargetInfo *createAlphaMCSubtargetInfo(StringRef TT, StringRef CPU, - StringRef FS) { - MCSubtargetInfo *X = new MCSubtargetInfo(); - InitAlphaMCSubtargetInfo(X, TT, CPU, FS); - return X; -} - -extern "C" void LLVMInitializeAlphaMCSubtargetInfo() { - TargetRegistry::RegisterMCSubtargetInfo(TheAlphaTarget, - createAlphaMCSubtargetInfo); -} diff --git a/llvm/lib/Target/Alpha/CMakeLists.txt b/llvm/lib/Target/Alpha/CMakeLists.txt index 3121889f73c3..3cca084741e4 100644 --- a/llvm/lib/Target/Alpha/CMakeLists.txt +++ b/llvm/lib/Target/Alpha/CMakeLists.txt @@ -23,3 +23,4 @@ add_llvm_target(AlphaCodeGen ) add_subdirectory(TargetInfo) +add_subdirectory(MCTargetDesc) diff --git a/llvm/lib/Target/Alpha/MCTargetDesc/AlphaMCTargetDesc.cpp b/llvm/lib/Target/Alpha/MCTargetDesc/AlphaMCTargetDesc.cpp new file mode 100644 index 000000000000..7e256b272bf7 --- /dev/null +++ b/llvm/lib/Target/Alpha/MCTargetDesc/AlphaMCTargetDesc.cpp @@ -0,0 +1,53 @@ +//===-- AlphaMCTargetDesc.cpp - Alpha Target Descriptions -------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file provides Alpha specific target descriptions. +// +//===----------------------------------------------------------------------===// + +#include "AlphaMCTargetDesc.h" +#include "llvm/MC/MCInstrInfo.h" +#include "llvm/MC/MCRegisterInfo.h" +#include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/Target/TargetRegistry.h" + +#define GET_INSTRINFO_MC_DESC +#include "AlphaGenInstrInfo.inc" + +#define GET_SUBTARGETINFO_MC_DESC +#include "AlphaGenSubtargetInfo.inc" + +#define GET_REGINFO_MC_DESC +#include "AlphaGenRegisterInfo.inc" + +using namespace llvm; + + +MCInstrInfo *createAlphaMCInstrInfo() { + MCInstrInfo *X = new MCInstrInfo(); + InitAlphaMCInstrInfo(X); + return X; +} + +extern "C" void LLVMInitializeAlphaMCInstrInfo() { + TargetRegistry::RegisterMCInstrInfo(TheAlphaTarget, createAlphaMCInstrInfo); +} + + +MCSubtargetInfo *createAlphaMCSubtargetInfo(StringRef TT, StringRef CPU, + StringRef FS) { + MCSubtargetInfo *X = new MCSubtargetInfo(); + InitAlphaMCSubtargetInfo(X, TT, CPU, FS); + return X; +} + +extern "C" void LLVMInitializeAlphaMCSubtargetInfo() { + TargetRegistry::RegisterMCSubtargetInfo(TheAlphaTarget, + createAlphaMCSubtargetInfo); +} diff --git a/llvm/lib/Target/Alpha/MCTargetDesc/AlphaMCTargetDesc.h b/llvm/lib/Target/Alpha/MCTargetDesc/AlphaMCTargetDesc.h new file mode 100644 index 000000000000..b0619e6cb011 --- /dev/null +++ b/llvm/lib/Target/Alpha/MCTargetDesc/AlphaMCTargetDesc.h @@ -0,0 +1,40 @@ +//===-- AlphaMCTargetDesc.h - Alpha Target Descriptions ---------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file provides Alpha specific target descriptions. +// +//===----------------------------------------------------------------------===// + +#ifndef ALPHAMCTARGETDESC_H +#define ALPHAMCTARGETDESC_H + +namespace llvm { +class MCSubtargetInfo; +class Target; +class StringRef; + +extern Target TheAlphaTarget; + +} // End llvm namespace + +// Defines symbolic names for Alpha registers. This defines a mapping from +// register name to register number. +// +#define GET_REGINFO_ENUM +#include "AlphaGenRegisterInfo.inc" + +// Defines symbolic names for the Alpha instructions. +// +#define GET_INSTRINFO_ENUM +#include "AlphaGenInstrInfo.inc" + +#define GET_SUBTARGETINFO_ENUM +#include "AlphaGenSubtargetInfo.inc" + +#endif diff --git a/llvm/lib/Target/Alpha/MCTargetDesc/CMakeLists.txt b/llvm/lib/Target/Alpha/MCTargetDesc/CMakeLists.txt new file mode 100644 index 000000000000..b5386041348f --- /dev/null +++ b/llvm/lib/Target/Alpha/MCTargetDesc/CMakeLists.txt @@ -0,0 +1 @@ +add_llvm_library(LLVMAlphaDesc AlphaMCTargetDesc.cpp) diff --git a/llvm/lib/Target/Alpha/MCTargetDesc/Makefile b/llvm/lib/Target/Alpha/MCTargetDesc/Makefile new file mode 100644 index 000000000000..d55175fa69dc --- /dev/null +++ b/llvm/lib/Target/Alpha/MCTargetDesc/Makefile @@ -0,0 +1,16 @@ +##===- lib/Target/Alpha/TargetDesc/Makefile ----------------*- Makefile -*-===## +# +# The LLVM Compiler Infrastructure +# +# This file is distributed under the University of Illinois Open Source +# License. See LICENSE.TXT for details. +# +##===----------------------------------------------------------------------===## + +LEVEL = ../../../.. +LIBRARYNAME = LLVMAlphaDesc + +# Hack: we need to include 'main' target directory to grab private headers +CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/.. + +include $(LEVEL)/Makefile.common diff --git a/llvm/lib/Target/Alpha/Makefile b/llvm/lib/Target/Alpha/Makefile index 9409ae57edf0..f48847a0627d 100644 --- a/llvm/lib/Target/Alpha/Makefile +++ b/llvm/lib/Target/Alpha/Makefile @@ -16,6 +16,6 @@ BUILT_SOURCES = AlphaGenRegisterInfo.inc AlphaGenInstrInfo.inc \ AlphaGenAsmWriter.inc AlphaGenDAGISel.inc \ AlphaGenCallingConv.inc AlphaGenSubtargetInfo.inc -DIRS = TargetInfo +DIRS = TargetInfo MCTargetDesc include $(LEVEL)/Makefile.common diff --git a/llvm/lib/Target/Blackfin/Blackfin.h b/llvm/lib/Target/Blackfin/Blackfin.h index c3ee7e71fd7e..a00ff4cc3275 100644 --- a/llvm/lib/Target/Blackfin/Blackfin.h +++ b/llvm/lib/Target/Blackfin/Blackfin.h @@ -15,6 +15,7 @@ #ifndef TARGET_BLACKFIN_H #define TARGET_BLACKFIN_H +#include "MCTargetDesc/BlackfinMCTargetDesc.h" #include "llvm/Target/TargetMachine.h" namespace llvm { @@ -24,17 +25,7 @@ namespace llvm { FunctionPass *createBlackfinISelDag(BlackfinTargetMachine &TM, CodeGenOpt::Level OptLevel); - extern Target TheBlackfinTarget; } // end namespace llvm -// Defines symbolic names for Blackfin registers. This defines a mapping from -// register name to register number. -#define GET_REGINFO_ENUM -#include "BlackfinGenRegisterInfo.inc" - -// Defines symbolic names for the Blackfin instructions. -#define GET_INSTRINFO_ENUM -#include "BlackfinGenInstrInfo.inc" - #endif diff --git a/llvm/lib/Target/Blackfin/BlackfinInstrInfo.cpp b/llvm/lib/Target/Blackfin/BlackfinInstrInfo.cpp index 5870f7c9a476..d190ae7984b2 100644 --- a/llvm/lib/Target/Blackfin/BlackfinInstrInfo.cpp +++ b/llvm/lib/Target/Blackfin/BlackfinInstrInfo.cpp @@ -22,7 +22,6 @@ #include "llvm/Support/ErrorHandling.h" #define GET_INSTRINFO_CTOR -#define GET_INSTRINFO_MC_DESC #include "BlackfinGenInstrInfo.inc" using namespace llvm; @@ -255,14 +254,3 @@ loadRegFromAddr(MachineFunction &MF, SmallVectorImpl &NewMIs) const { llvm_unreachable("loadRegFromAddr not implemented"); } - -MCInstrInfo *createBlackfinMCInstrInfo() { - MCInstrInfo *X = new MCInstrInfo(); - InitBlackfinMCInstrInfo(X); - return X; -} - -extern "C" void LLVMInitializeBlackfinMCInstrInfo() { - TargetRegistry::RegisterMCInstrInfo(TheBlackfinTarget, - createBlackfinMCInstrInfo); -} diff --git a/llvm/lib/Target/Blackfin/BlackfinRegisterInfo.cpp b/llvm/lib/Target/Blackfin/BlackfinRegisterInfo.cpp index 2f4a453ec045..3a7c104ee055 100644 --- a/llvm/lib/Target/Blackfin/BlackfinRegisterInfo.cpp +++ b/llvm/lib/Target/Blackfin/BlackfinRegisterInfo.cpp @@ -30,7 +30,6 @@ #include "llvm/ADT/BitVector.h" #include "llvm/ADT/STLExtras.h" -#define GET_REGINFO_MC_DESC #define GET_REGINFO_TARGET_DESC #include "BlackfinGenRegisterInfo.inc" diff --git a/llvm/lib/Target/Blackfin/BlackfinSubtarget.cpp b/llvm/lib/Target/Blackfin/BlackfinSubtarget.cpp index c7b50e4d53c7..ec919cdf0b90 100644 --- a/llvm/lib/Target/Blackfin/BlackfinSubtarget.cpp +++ b/llvm/lib/Target/Blackfin/BlackfinSubtarget.cpp @@ -15,8 +15,6 @@ #include "Blackfin.h" #include "llvm/Target/TargetRegistry.h" -#define GET_SUBTARGETINFO_ENUM -#define GET_SUBTARGETINFO_MC_DESC #define GET_SUBTARGETINFO_TARGET_DESC #define GET_SUBTARGETINFO_CTOR #include "BlackfinGenSubtargetInfo.inc" @@ -44,15 +42,3 @@ BlackfinSubtarget::BlackfinSubtarget(const std::string &TT, // Parse features string. ParseSubtargetFeatures(CPUName, FS); } - -MCSubtargetInfo *createBlackfinMCSubtargetInfo(StringRef TT, StringRef CPU, - StringRef FS) { - MCSubtargetInfo *X = new MCSubtargetInfo(); - InitBlackfinMCSubtargetInfo(X, TT, CPU, FS); - return X; -} - -extern "C" void LLVMInitializeBlackfinMCSubtargetInfo() { - TargetRegistry::RegisterMCSubtargetInfo(TheBlackfinTarget, - createBlackfinMCSubtargetInfo); -} diff --git a/llvm/lib/Target/Blackfin/CMakeLists.txt b/llvm/lib/Target/Blackfin/CMakeLists.txt index 9df4ab09038e..31ec281baa28 100644 --- a/llvm/lib/Target/Blackfin/CMakeLists.txt +++ b/llvm/lib/Target/Blackfin/CMakeLists.txt @@ -23,3 +23,4 @@ add_llvm_target(BlackfinCodeGen ) add_subdirectory(TargetInfo) +add_subdirectory(MCTargetDesc) diff --git a/llvm/lib/Target/Blackfin/MCTargetDesc/BlackfinMCTargetDesc.cpp b/llvm/lib/Target/Blackfin/MCTargetDesc/BlackfinMCTargetDesc.cpp new file mode 100644 index 000000000000..521c87dda1d3 --- /dev/null +++ b/llvm/lib/Target/Blackfin/MCTargetDesc/BlackfinMCTargetDesc.cpp @@ -0,0 +1,54 @@ +//===-- BlackfinMCTargetDesc.cpp - Blackfin Target Descriptions -*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file provides Blackfin specific target descriptions. +// +//===----------------------------------------------------------------------===// + +#include "BlackfinMCTargetDesc.h" +#include "llvm/MC/MCInstrInfo.h" +#include "llvm/MC/MCRegisterInfo.h" +#include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/Target/TargetRegistry.h" + +#define GET_INSTRINFO_MC_DESC +#include "BlackfinGenInstrInfo.inc" + +#define GET_SUBTARGETINFO_MC_DESC +#include "BlackfinGenSubtargetInfo.inc" + +#define GET_REGINFO_MC_DESC +#include "BlackfinGenRegisterInfo.inc" + +using namespace llvm; + + +MCInstrInfo *createBlackfinMCInstrInfo() { + MCInstrInfo *X = new MCInstrInfo(); + InitBlackfinMCInstrInfo(X); + return X; +} + +extern "C" void LLVMInitializeBlackfinMCInstrInfo() { + TargetRegistry::RegisterMCInstrInfo(TheBlackfinTarget, + createBlackfinMCInstrInfo); +} + + +MCSubtargetInfo *createBlackfinMCSubtargetInfo(StringRef TT, StringRef CPU, + StringRef FS) { + MCSubtargetInfo *X = new MCSubtargetInfo(); + InitBlackfinMCSubtargetInfo(X, TT, CPU, FS); + return X; +} + +extern "C" void LLVMInitializeBlackfinMCSubtargetInfo() { + TargetRegistry::RegisterMCSubtargetInfo(TheBlackfinTarget, + createBlackfinMCSubtargetInfo); +} diff --git a/llvm/lib/Target/Blackfin/MCTargetDesc/BlackfinMCTargetDesc.h b/llvm/lib/Target/Blackfin/MCTargetDesc/BlackfinMCTargetDesc.h new file mode 100644 index 000000000000..5bffe94fc582 --- /dev/null +++ b/llvm/lib/Target/Blackfin/MCTargetDesc/BlackfinMCTargetDesc.h @@ -0,0 +1,38 @@ +//===-- BlackfinMCTargetDesc.h - Blackfin Target Descriptions ---*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file provides Blackfin specific target descriptions. +// +//===----------------------------------------------------------------------===// + +#ifndef BLACKFINMCTARGETDESC_H +#define BLACKFINMCTARGETDESC_H + +namespace llvm { +class MCSubtargetInfo; +class Target; +class StringRef; + +extern Target TheBlackfinTarget; + +} // End llvm namespace + +// Defines symbolic names for Blackfin registers. This defines a mapping from +// register name to register number. +#define GET_REGINFO_ENUM +#include "BlackfinGenRegisterInfo.inc" + +// Defines symbolic names for the Blackfin instructions. +#define GET_INSTRINFO_ENUM +#include "BlackfinGenInstrInfo.inc" + +#define GET_SUBTARGETINFO_ENUM +#include "BlackfinGenSubtargetInfo.inc" + +#endif diff --git a/llvm/lib/Target/Blackfin/MCTargetDesc/CMakeLists.txt b/llvm/lib/Target/Blackfin/MCTargetDesc/CMakeLists.txt new file mode 100644 index 000000000000..21e1fcea0501 --- /dev/null +++ b/llvm/lib/Target/Blackfin/MCTargetDesc/CMakeLists.txt @@ -0,0 +1 @@ +add_llvm_library(LLVMBlackfinDesc BlackfinMCTargetDesc.cpp) diff --git a/llvm/lib/Target/Blackfin/MCTargetDesc/Makefile b/llvm/lib/Target/Blackfin/MCTargetDesc/Makefile new file mode 100644 index 000000000000..6b26101f4473 --- /dev/null +++ b/llvm/lib/Target/Blackfin/MCTargetDesc/Makefile @@ -0,0 +1,16 @@ +##===- lib/Target/Blackfin/TargetDesc/Makefile -------------*- Makefile -*-===## +# +# The LLVM Compiler Infrastructure +# +# This file is distributed under the University of Illinois Open Source +# License. See LICENSE.TXT for details. +# +##===----------------------------------------------------------------------===## + +LEVEL = ../../../.. +LIBRARYNAME = LLVMBlackfinDesc + +# Hack: we need to include 'main' target directory to grab private headers +CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/.. + +include $(LEVEL)/Makefile.common diff --git a/llvm/lib/Target/Blackfin/Makefile b/llvm/lib/Target/Blackfin/Makefile index 63f154366887..756ac6bcd8a0 100644 --- a/llvm/lib/Target/Blackfin/Makefile +++ b/llvm/lib/Target/Blackfin/Makefile @@ -17,7 +17,7 @@ BUILT_SOURCES = BlackfinGenRegisterInfo.inc BlackfinGenInstrInfo.inc \ BlackfinGenDAGISel.inc BlackfinGenSubtargetInfo.inc \ BlackfinGenCallingConv.inc BlackfinGenIntrinsics.inc -DIRS = TargetInfo +DIRS = TargetInfo MCTargetDesc include $(LEVEL)/Makefile.common diff --git a/llvm/lib/Target/CellSPU/CMakeLists.txt b/llvm/lib/Target/CellSPU/CMakeLists.txt index 14e8208ce924..225830d2a292 100644 --- a/llvm/lib/Target/CellSPU/CMakeLists.txt +++ b/llvm/lib/Target/CellSPU/CMakeLists.txt @@ -24,3 +24,4 @@ add_llvm_target(CellSPUCodeGen ) add_subdirectory(TargetInfo) +add_subdirectory(MCTargetDesc) diff --git a/llvm/lib/Target/CellSPU/MCTargetDesc/CMakeLists.txt b/llvm/lib/Target/CellSPU/MCTargetDesc/CMakeLists.txt new file mode 100644 index 000000000000..87bc856625e3 --- /dev/null +++ b/llvm/lib/Target/CellSPU/MCTargetDesc/CMakeLists.txt @@ -0,0 +1 @@ +add_llvm_library(LLVMCellSPUDesc SPUMCTargetDesc.cpp) diff --git a/llvm/lib/Target/CellSPU/MCTargetDesc/Makefile b/llvm/lib/Target/CellSPU/MCTargetDesc/Makefile new file mode 100644 index 000000000000..10d9a42239ad --- /dev/null +++ b/llvm/lib/Target/CellSPU/MCTargetDesc/Makefile @@ -0,0 +1,16 @@ +##===- lib/Target/CellSPU/TargetDesc/Makefile --------------*- Makefile -*-===## +# +# The LLVM Compiler Infrastructure +# +# This file is distributed under the University of Illinois Open Source +# License. See LICENSE.TXT for details. +# +##===----------------------------------------------------------------------===## + +LEVEL = ../../../.. +LIBRARYNAME = LLVMCellSPUDesc + +# Hack: we need to include 'main' target directory to grab private headers +CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/.. + +include $(LEVEL)/Makefile.common diff --git a/llvm/lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.cpp b/llvm/lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.cpp new file mode 100644 index 000000000000..a3236256843c --- /dev/null +++ b/llvm/lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.cpp @@ -0,0 +1,51 @@ +//===-- SPUMCTargetDesc.cpp - Cell SPU Target Descriptions -----*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file provides Cell SPU specific target descriptions. +// +//===----------------------------------------------------------------------===// + +#include "SPUMCTargetDesc.h" +#include "llvm/MC/MCInstrInfo.h" +#include "llvm/MC/MCRegisterInfo.h" +#include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/Target/TargetRegistry.h" + +#define GET_INSTRINFO_MC_DESC +#include "SPUGenInstrInfo.inc" + +#define GET_SUBTARGETINFO_MC_DESC +#include "SPUGenSubtargetInfo.inc" + +#define GET_REGINFO_MC_DESC +#include "SPUGenRegisterInfo.inc" + +using namespace llvm; + +MCInstrInfo *createSPUMCInstrInfo() { + MCInstrInfo *X = new MCInstrInfo(); + InitSPUMCInstrInfo(X); + return X; +} + +extern "C" void LLVMInitializeCellSPUMCInstrInfo() { + TargetRegistry::RegisterMCInstrInfo(TheCellSPUTarget, createSPUMCInstrInfo); +} + +MCSubtargetInfo *createSPUMCSubtargetInfo(StringRef TT, StringRef CPU, + StringRef FS) { + MCSubtargetInfo *X = new MCSubtargetInfo(); + InitSPUMCSubtargetInfo(X, TT, CPU, FS); + return X; +} + +extern "C" void LLVMInitializeCellSPUMCSubtargetInfo() { + TargetRegistry::RegisterMCSubtargetInfo(TheCellSPUTarget, + createSPUMCSubtargetInfo); +} diff --git a/llvm/lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.h b/llvm/lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.h new file mode 100644 index 000000000000..c5c037d4de44 --- /dev/null +++ b/llvm/lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.h @@ -0,0 +1,40 @@ +//===-- SPUMCTargetDesc.h - Alpha Target Descriptions ---------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file provides Alpha specific target descriptions. +// +//===----------------------------------------------------------------------===// + +#ifndef SPUMCTARGETDESC_H +#define SPUMCTARGETDESC_H + +namespace llvm { +class MCSubtargetInfo; +class Target; +class StringRef; + +extern Target TheCellSPUTarget; + +} // End llvm namespace + +// Define symbolic names for Cell registers. This defines a mapping from +// register name to register number. +// +#define GET_REGINFO_ENUM +#include "SPUGenRegisterInfo.inc" + +// Defines symbolic names for the SPU instructions. +// +#define GET_INSTRINFO_ENUM +#include "SPUGenInstrInfo.inc" + +#define GET_SUBTARGETINFO_ENUM +#include "SPUGenSubtargetInfo.inc" + +#endif diff --git a/llvm/lib/Target/CellSPU/Makefile b/llvm/lib/Target/CellSPU/Makefile index c804b166bf5d..d7a8247f5702 100644 --- a/llvm/lib/Target/CellSPU/Makefile +++ b/llvm/lib/Target/CellSPU/Makefile @@ -15,6 +15,6 @@ BUILT_SOURCES = SPUGenInstrInfo.inc SPUGenRegisterInfo.inc \ SPUGenDAGISel.inc \ SPUGenSubtargetInfo.inc SPUGenCallingConv.inc -DIRS = TargetInfo +DIRS = TargetInfo MCTargetDesc include $(LEVEL)/Makefile.common diff --git a/llvm/lib/Target/CellSPU/SPU.h b/llvm/lib/Target/CellSPU/SPU.h index 5c81c9a77a3c..b51fbc7a5197 100644 --- a/llvm/lib/Target/CellSPU/SPU.h +++ b/llvm/lib/Target/CellSPU/SPU.h @@ -15,6 +15,7 @@ #ifndef LLVM_TARGET_IBMCELLSPU_H #define LLVM_TARGET_IBMCELLSPU_H +#include "MCTargetDesc/SPUMCTargetDesc.h" #include "llvm/Target/TargetMachine.h" namespace llvm { @@ -25,12 +26,6 @@ namespace llvm { FunctionPass *createSPUISelDag(SPUTargetMachine &TM); FunctionPass *createSPUNopFillerPass(SPUTargetMachine &tm); - extern Target TheCellSPUTarget; } -// Defines symbolic names for the SPU instructions. -// -#define GET_INSTRINFO_ENUM -#include "SPUGenInstrInfo.inc" - #endif /* LLVM_TARGET_IBMCELLSPU_H */ diff --git a/llvm/lib/Target/CellSPU/SPUFrameLowering.cpp b/llvm/lib/Target/CellSPU/SPUFrameLowering.cpp index 432f4a1b59e2..a3e7e73ae30a 100644 --- a/llvm/lib/Target/CellSPU/SPUFrameLowering.cpp +++ b/llvm/lib/Target/CellSPU/SPUFrameLowering.cpp @@ -13,7 +13,6 @@ #include "SPU.h" #include "SPUFrameLowering.h" -#include "SPURegisterNames.h" #include "SPUInstrBuilder.h" #include "SPUInstrInfo.h" #include "llvm/Function.h" diff --git a/llvm/lib/Target/CellSPU/SPUISelDAGToDAG.cpp b/llvm/lib/Target/CellSPU/SPUISelDAGToDAG.cpp index 9351ffdc0b7f..a297d036f03e 100644 --- a/llvm/lib/Target/CellSPU/SPUISelDAGToDAG.cpp +++ b/llvm/lib/Target/CellSPU/SPUISelDAGToDAG.cpp @@ -16,7 +16,6 @@ #include "SPUTargetMachine.h" #include "SPUHazardRecognizers.h" #include "SPUFrameLowering.h" -#include "SPURegisterNames.h" #include "SPUTargetMachine.h" #include "llvm/CodeGen/MachineConstantPool.h" #include "llvm/CodeGen/MachineInstrBuilder.h" diff --git a/llvm/lib/Target/CellSPU/SPUISelLowering.cpp b/llvm/lib/Target/CellSPU/SPUISelLowering.cpp index 81d664f70dc1..f0ceee214149 100644 --- a/llvm/lib/Target/CellSPU/SPUISelLowering.cpp +++ b/llvm/lib/Target/CellSPU/SPUISelLowering.cpp @@ -10,7 +10,6 @@ // //===----------------------------------------------------------------------===// -#include "SPURegisterNames.h" #include "SPUISelLowering.h" #include "SPUTargetMachine.h" #include "SPUFrameLowering.h" diff --git a/llvm/lib/Target/CellSPU/SPUInstrInfo.cpp b/llvm/lib/Target/CellSPU/SPUInstrInfo.cpp index 12fae9df8787..e67b10c7984d 100644 --- a/llvm/lib/Target/CellSPU/SPUInstrInfo.cpp +++ b/llvm/lib/Target/CellSPU/SPUInstrInfo.cpp @@ -11,7 +11,6 @@ // //===----------------------------------------------------------------------===// -#include "SPURegisterNames.h" #include "SPUInstrInfo.h" #include "SPUInstrBuilder.h" #include "SPUTargetMachine.h" @@ -24,7 +23,6 @@ #include "llvm/Support/raw_ostream.h" #define GET_INSTRINFO_CTOR -#define GET_INSTRINFO_MC_DESC #include "SPUGenInstrInfo.inc" using namespace llvm; @@ -451,13 +449,3 @@ SPUInstrInfo::ReverseBranchCondition(SmallVectorImpl &Cond) return true; } - -MCInstrInfo *createSPUMCInstrInfo() { - MCInstrInfo *X = new MCInstrInfo(); - InitSPUMCInstrInfo(X); - return X; -} - -extern "C" void LLVMInitializeCellSPUMCInstrInfo() { - TargetRegistry::RegisterMCInstrInfo(TheCellSPUTarget, createSPUMCInstrInfo); -} diff --git a/llvm/lib/Target/CellSPU/SPURegisterInfo.cpp b/llvm/lib/Target/CellSPU/SPURegisterInfo.cpp index fefd141f4b4f..19896c0b4be9 100644 --- a/llvm/lib/Target/CellSPU/SPURegisterInfo.cpp +++ b/llvm/lib/Target/CellSPU/SPURegisterInfo.cpp @@ -14,7 +14,6 @@ #define DEBUG_TYPE "reginfo" #include "SPU.h" #include "SPURegisterInfo.h" -#include "SPURegisterNames.h" #include "SPUInstrBuilder.h" #include "SPUSubtarget.h" #include "SPUMachineFunction.h" @@ -43,7 +42,6 @@ #include "llvm/ADT/STLExtras.h" #include -#define GET_REGINFO_MC_DESC #define GET_REGINFO_TARGET_DESC #include "SPUGenRegisterInfo.inc" diff --git a/llvm/lib/Target/CellSPU/SPUSubtarget.cpp b/llvm/lib/Target/CellSPU/SPUSubtarget.cpp index 51fa1ea1b577..856dc82f786b 100644 --- a/llvm/lib/Target/CellSPU/SPUSubtarget.cpp +++ b/llvm/lib/Target/CellSPU/SPUSubtarget.cpp @@ -17,8 +17,6 @@ #include "llvm/Target/TargetRegistry.h" #include "llvm/ADT/SmallVector.h" -#define GET_SUBTARGETINFO_ENUM -#define GET_SUBTARGETINFO_MC_DESC #define GET_SUBTARGETINFO_TARGET_DESC #define GET_SUBTARGETINFO_CTOR #include "SPUGenSubtargetInfo.inc" @@ -66,15 +64,3 @@ bool SPUSubtarget::enablePostRAScheduler( CriticalPathRCs.push_back(&SPU::VECREGRegClass); return OptLevel >= CodeGenOpt::Default; } - -MCSubtargetInfo *createSPUMCSubtargetInfo(StringRef TT, StringRef CPU, - StringRef FS) { - MCSubtargetInfo *X = new MCSubtargetInfo(); - InitSPUMCSubtargetInfo(X, TT, CPU, FS); - return X; -} - -extern "C" void LLVMInitializeCellSPUMCSubtargetInfo() { - TargetRegistry::RegisterMCSubtargetInfo(TheCellSPUTarget, - createSPUMCSubtargetInfo); -} diff --git a/llvm/lib/Target/CellSPU/SPUTargetMachine.cpp b/llvm/lib/Target/CellSPU/SPUTargetMachine.cpp index 84c5fd7902e0..5903f9b612dd 100644 --- a/llvm/lib/Target/CellSPU/SPUTargetMachine.cpp +++ b/llvm/lib/Target/CellSPU/SPUTargetMachine.cpp @@ -12,7 +12,6 @@ //===----------------------------------------------------------------------===// #include "SPU.h" -#include "SPURegisterNames.h" #include "SPUMCAsmInfo.h" #include "SPUTargetMachine.h" #include "llvm/PassManager.h" diff --git a/llvm/lib/Target/MBlaze/CMakeLists.txt b/llvm/lib/Target/MBlaze/CMakeLists.txt index 536726d8039d..d98968051647 100644 --- a/llvm/lib/Target/MBlaze/CMakeLists.txt +++ b/llvm/lib/Target/MBlaze/CMakeLists.txt @@ -35,3 +35,4 @@ add_subdirectory(AsmParser) add_subdirectory(Disassembler) add_subdirectory(InstPrinter) add_subdirectory(TargetInfo) +add_subdirectory(MCTargetDesc) diff --git a/llvm/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp b/llvm/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp index 14642742e349..0157b4eb0382 100644 --- a/llvm/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp +++ b/llvm/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp @@ -27,10 +27,12 @@ // #include "MBlazeGenDecoderTables.inc" // #include "MBlazeGenRegisterNames.inc" -#define GET_INSTRINFO_MC_DESC -#include "MBlazeGenInstrInfo.inc" #include "MBlazeGenEDInfo.inc" +namespace llvm { +extern const MCInstrDesc MBlazeInsts[]; +} + using namespace llvm; const unsigned UNSUPPORTED = -1; diff --git a/llvm/lib/Target/MBlaze/MBlaze.h b/llvm/lib/Target/MBlaze/MBlaze.h index 26b869b143b3..3390794c9375 100644 --- a/llvm/lib/Target/MBlaze/MBlaze.h +++ b/llvm/lib/Target/MBlaze/MBlaze.h @@ -15,6 +15,7 @@ #ifndef TARGET_MBLAZE_H #define TARGET_MBLAZE_H +#include "MCTargetDesc/MBlazeMCTargetDesc.h" #include "llvm/Target/TargetMachine.h" namespace llvm { @@ -36,16 +37,6 @@ namespace llvm { FunctionPass *createMBlazeISelDag(MBlazeTargetMachine &TM); FunctionPass *createMBlazeDelaySlotFillerPass(MBlazeTargetMachine &TM); - extern Target TheMBlazeTarget; } // end namespace llvm; -// Defines symbolic names for MBlaze registers. This defines a mapping from -// register name to register number. -#define GET_REGINFO_ENUM -#include "MBlazeGenRegisterInfo.inc" - -// Defines symbolic names for the MBlaze instructions. -#define GET_INSTRINFO_ENUM -#include "MBlazeGenInstrInfo.inc" - #endif diff --git a/llvm/lib/Target/MBlaze/MBlazeInstrInfo.cpp b/llvm/lib/Target/MBlaze/MBlazeInstrInfo.cpp index 8f7d956ccba5..188f10a3972e 100644 --- a/llvm/lib/Target/MBlaze/MBlazeInstrInfo.cpp +++ b/llvm/lib/Target/MBlaze/MBlazeInstrInfo.cpp @@ -23,7 +23,6 @@ #include "llvm/ADT/STLExtras.h" #define GET_INSTRINFO_CTOR -#define GET_INSTRINFO_MC_DESC #include "MBlazeGenInstrInfo.inc" using namespace llvm; @@ -295,13 +294,3 @@ unsigned MBlazeInstrInfo::getGlobalBaseReg(MachineFunction *MF) const { MBlazeFI->setGlobalBaseReg(GlobalBaseReg); return GlobalBaseReg; } - -MCInstrInfo *createMBlazeMCInstrInfo() { - MCInstrInfo *X = new MCInstrInfo(); - InitMBlazeMCInstrInfo(X); - return X; -} - -extern "C" void LLVMInitializeMBlazeMCInstrInfo() { - TargetRegistry::RegisterMCInstrInfo(TheMBlazeTarget, createMBlazeMCInstrInfo); -} diff --git a/llvm/lib/Target/MBlaze/MBlazeRegisterInfo.cpp b/llvm/lib/Target/MBlaze/MBlazeRegisterInfo.cpp index 441ece105419..f0b201a66170 100644 --- a/llvm/lib/Target/MBlaze/MBlazeRegisterInfo.cpp +++ b/llvm/lib/Target/MBlaze/MBlazeRegisterInfo.cpp @@ -37,7 +37,6 @@ #include "llvm/ADT/BitVector.h" #include "llvm/ADT/STLExtras.h" -#define GET_REGINFO_MC_DESC #define GET_REGINFO_TARGET_DESC #include "MBlazeGenRegisterInfo.inc" diff --git a/llvm/lib/Target/MBlaze/MBlazeSubtarget.cpp b/llvm/lib/Target/MBlaze/MBlazeSubtarget.cpp index 54be1be37b62..eda141daf2b3 100644 --- a/llvm/lib/Target/MBlaze/MBlazeSubtarget.cpp +++ b/llvm/lib/Target/MBlaze/MBlazeSubtarget.cpp @@ -17,8 +17,6 @@ #include "llvm/Support/CommandLine.h" #include "llvm/Target/TargetRegistry.h" -#define GET_SUBTARGETINFO_ENUM -#define GET_SUBTARGETINFO_MC_DESC #define GET_SUBTARGETINFO_TARGET_DESC #define GET_SUBTARGETINFO_CTOR #include "MBlazeGenSubtargetInfo.inc" @@ -63,15 +61,3 @@ enablePostRAScheduler(CodeGenOpt::Level OptLevel, CriticalPathRCs.push_back(&MBlaze::GPRRegClass); return HasItin && OptLevel >= CodeGenOpt::Default; } - -MCSubtargetInfo *createMBlazeMCSubtargetInfo(StringRef TT, StringRef CPU, - StringRef FS) { - MCSubtargetInfo *X = new MCSubtargetInfo(); - InitMBlazeMCSubtargetInfo(X, TT, CPU, FS); - return X; -} - -extern "C" void LLVMInitializeMBlazeMCSubtargetInfo() { - TargetRegistry::RegisterMCSubtargetInfo(TheMBlazeTarget, - createMBlazeMCSubtargetInfo); -} diff --git a/llvm/lib/Target/MBlaze/MCTargetDesc/CMakeLists.txt b/llvm/lib/Target/MBlaze/MCTargetDesc/CMakeLists.txt new file mode 100644 index 000000000000..a0f2ec448aa5 --- /dev/null +++ b/llvm/lib/Target/MBlaze/MCTargetDesc/CMakeLists.txt @@ -0,0 +1 @@ +add_llvm_library(LLVMMBlazeDesc MBlazeMCTargetDesc.cpp) diff --git a/llvm/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp b/llvm/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp new file mode 100644 index 000000000000..50714e475211 --- /dev/null +++ b/llvm/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp @@ -0,0 +1,52 @@ +//===-- MBlazeMCTargetDesc.cpp - MBlaze Target Descriptions -----*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file provides MBlaze specific target descriptions. +// +//===----------------------------------------------------------------------===// + +#include "MBlazeMCTargetDesc.h" +#include "llvm/MC/MCInstrInfo.h" +#include "llvm/MC/MCRegisterInfo.h" +#include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/Target/TargetRegistry.h" + +#define GET_INSTRINFO_MC_DESC +#include "MBlazeGenInstrInfo.inc" + +#define GET_SUBTARGETINFO_MC_DESC +#include "MBlazeGenSubtargetInfo.inc" + +#define GET_REGINFO_MC_DESC +#include "MBlazeGenRegisterInfo.inc" + +using namespace llvm; + + +MCInstrInfo *createMBlazeMCInstrInfo() { + MCInstrInfo *X = new MCInstrInfo(); + InitMBlazeMCInstrInfo(X); + return X; +} + +extern "C" void LLVMInitializeMBlazeMCInstrInfo() { + TargetRegistry::RegisterMCInstrInfo(TheMBlazeTarget, createMBlazeMCInstrInfo); +} + +MCSubtargetInfo *createMBlazeMCSubtargetInfo(StringRef TT, StringRef CPU, + StringRef FS) { + MCSubtargetInfo *X = new MCSubtargetInfo(); + InitMBlazeMCSubtargetInfo(X, TT, CPU, FS); + return X; +} + +extern "C" void LLVMInitializeMBlazeMCSubtargetInfo() { + TargetRegistry::RegisterMCSubtargetInfo(TheMBlazeTarget, + createMBlazeMCSubtargetInfo); +} diff --git a/llvm/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.h b/llvm/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.h new file mode 100644 index 000000000000..b14772ef060b --- /dev/null +++ b/llvm/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.h @@ -0,0 +1,38 @@ +//===-- MBlazeMCTargetDesc.h - MBlaze Target Descriptions -------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file provides MBlaze specific target descriptions. +// +//===----------------------------------------------------------------------===// + +#ifndef MBLAZEMCTARGETDESC_H +#define MBLAZEMCTARGETDESC_H + +namespace llvm { +class MCSubtargetInfo; +class Target; +class StringRef; + +extern Target TheMBlazeTarget; + +} // End llvm namespace + +// Defines symbolic names for MBlaze registers. This defines a mapping from +// register name to register number. +#define GET_REGINFO_ENUM +#include "MBlazeGenRegisterInfo.inc" + +// Defines symbolic names for the MBlaze instructions. +#define GET_INSTRINFO_ENUM +#include "MBlazeGenInstrInfo.inc" + +#define GET_SUBTARGETINFO_ENUM +#include "MBlazeGenSubtargetInfo.inc" + +#endif diff --git a/llvm/lib/Target/MBlaze/MCTargetDesc/Makefile b/llvm/lib/Target/MBlaze/MCTargetDesc/Makefile new file mode 100644 index 000000000000..71075ffbf47c --- /dev/null +++ b/llvm/lib/Target/MBlaze/MCTargetDesc/Makefile @@ -0,0 +1,16 @@ +##===- lib/Target/MBlaze/TargetDesc/Makefile ---------------*- Makefile -*-===## +# +# The LLVM Compiler Infrastructure +# +# This file is distributed under the University of Illinois Open Source +# License. See LICENSE.TXT for details. +# +##===----------------------------------------------------------------------===## + +LEVEL = ../../../.. +LIBRARYNAME = LLVMMBlazeDesc + +# Hack: we need to include 'main' target directory to grab private headers +CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/.. + +include $(LEVEL)/Makefile.common diff --git a/llvm/lib/Target/MBlaze/Makefile b/llvm/lib/Target/MBlaze/Makefile index 829122f7e6f6..83c2a7d34da1 100644 --- a/llvm/lib/Target/MBlaze/Makefile +++ b/llvm/lib/Target/MBlaze/Makefile @@ -18,7 +18,7 @@ BUILT_SOURCES = MBlazeGenRegisterInfo.inc MBlazeGenInstrInfo.inc \ MBlazeGenSubtargetInfo.inc MBlazeGenIntrinsics.inc \ MBlazeGenEDInfo.inc -DIRS = InstPrinter AsmParser Disassembler TargetInfo +DIRS = InstPrinter AsmParser Disassembler TargetInfo MCTargetDesc include $(LEVEL)/Makefile.common diff --git a/llvm/lib/Target/MSP430/CMakeLists.txt b/llvm/lib/Target/MSP430/CMakeLists.txt index 9d156e79920b..9fec02a9e1dc 100644 --- a/llvm/lib/Target/MSP430/CMakeLists.txt +++ b/llvm/lib/Target/MSP430/CMakeLists.txt @@ -24,3 +24,4 @@ add_llvm_target(MSP430CodeGen add_subdirectory(InstPrinter) add_subdirectory(TargetInfo) +add_subdirectory(MCTargetDesc) diff --git a/llvm/lib/Target/MSP430/MCTargetDesc/CMakeLists.txt b/llvm/lib/Target/MSP430/MCTargetDesc/CMakeLists.txt new file mode 100644 index 000000000000..4b4ccda80b2c --- /dev/null +++ b/llvm/lib/Target/MSP430/MCTargetDesc/CMakeLists.txt @@ -0,0 +1 @@ +add_llvm_library(LLVMMSP430Desc MSP430MCTargetDesc.cpp) diff --git a/llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp b/llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp new file mode 100644 index 000000000000..fc77305d234e --- /dev/null +++ b/llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp @@ -0,0 +1,53 @@ +//===-- MSP430MCTargetDesc.cpp - MSP430 Target Descriptions -----*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file provides MSP430 specific target descriptions. +// +//===----------------------------------------------------------------------===// + +#include "MSP430MCTargetDesc.h" +#include "llvm/MC/MCInstrInfo.h" +#include "llvm/MC/MCRegisterInfo.h" +#include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/Target/TargetRegistry.h" + +#define GET_INSTRINFO_MC_DESC +#include "MSP430GenInstrInfo.inc" + +#define GET_SUBTARGETINFO_MC_DESC +#include "MSP430GenSubtargetInfo.inc" + +#define GET_REGINFO_MC_DESC +#include "MSP430GenRegisterInfo.inc" + +using namespace llvm; + + +MCInstrInfo *createMSP430MCInstrInfo() { + MCInstrInfo *X = new MCInstrInfo(); + InitMSP430MCInstrInfo(X); + return X; +} + +extern "C" void LLVMInitializeMSP430MCInstrInfo() { + TargetRegistry::RegisterMCInstrInfo(TheMSP430Target, createMSP430MCInstrInfo); +} + + +MCSubtargetInfo *createMSP430MCSubtargetInfo(StringRef TT, StringRef CPU, + StringRef FS) { + MCSubtargetInfo *X = new MCSubtargetInfo(); + InitMSP430MCSubtargetInfo(X, TT, CPU, FS); + return X; +} + +extern "C" void LLVMInitializeMSP430MCSubtargetInfo() { + TargetRegistry::RegisterMCSubtargetInfo(TheMSP430Target, + createMSP430MCSubtargetInfo); +} diff --git a/llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.h b/llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.h new file mode 100644 index 000000000000..0d8a6bdb44f9 --- /dev/null +++ b/llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.h @@ -0,0 +1,38 @@ +//===-- MSP430MCTargetDesc.h - MSP430 Target Descriptions -------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file provides MSP430 specific target descriptions. +// +//===----------------------------------------------------------------------===// + +#ifndef ALPHAMCTARGETDESC_H +#define ALPHAMCTARGETDESC_H + +namespace llvm { +class MCSubtargetInfo; +class Target; +class StringRef; + +extern Target TheMSP430Target; + +} // End llvm namespace + +// Defines symbolic names for MSP430 registers. +// This defines a mapping from register name to register number. +#define GET_REGINFO_ENUM +#include "MSP430GenRegisterInfo.inc" + +// Defines symbolic names for the MSP430 instructions. +#define GET_INSTRINFO_ENUM +#include "MSP430GenInstrInfo.inc" + +#define GET_SUBTARGETINFO_ENUM +#include "MSP430GenSubtargetInfo.inc" + +#endif diff --git a/llvm/lib/Target/MSP430/MCTargetDesc/Makefile b/llvm/lib/Target/MSP430/MCTargetDesc/Makefile new file mode 100644 index 000000000000..bb857998eef9 --- /dev/null +++ b/llvm/lib/Target/MSP430/MCTargetDesc/Makefile @@ -0,0 +1,16 @@ +##===- lib/Target/MSP430/TargetDesc/Makefile ---------------*- Makefile -*-===## +# +# The LLVM Compiler Infrastructure +# +# This file is distributed under the University of Illinois Open Source +# License. See LICENSE.TXT for details. +# +##===----------------------------------------------------------------------===## + +LEVEL = ../../../.. +LIBRARYNAME = LLVMMSP430Desc + +# Hack: we need to include 'main' target directory to grab private headers +CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/.. + +include $(LEVEL)/Makefile.common diff --git a/llvm/lib/Target/MSP430/MSP430.h b/llvm/lib/Target/MSP430/MSP430.h index 854d4e457c8d..4574ce5f98b7 100644 --- a/llvm/lib/Target/MSP430/MSP430.h +++ b/llvm/lib/Target/MSP430/MSP430.h @@ -15,6 +15,7 @@ #ifndef LLVM_TARGET_MSP430_H #define LLVM_TARGET_MSP430_H +#include "MCTargetDesc/MSP430MCTargetDesc.h" #include "llvm/Target/TargetMachine.h" namespace MSP430CC { @@ -41,17 +42,6 @@ namespace llvm { FunctionPass *createMSP430BranchSelectionPass(); - extern Target TheMSP430Target; - } // end namespace llvm; -// Defines symbolic names for MSP430 registers. -// This defines a mapping from register name to register number. -#define GET_REGINFO_ENUM -#include "MSP430GenRegisterInfo.inc" - -// Defines symbolic names for the MSP430 instructions. -#define GET_INSTRINFO_ENUM -#include "MSP430GenInstrInfo.inc" - #endif diff --git a/llvm/lib/Target/MSP430/MSP430InstrInfo.cpp b/llvm/lib/Target/MSP430/MSP430InstrInfo.cpp index e9dfd5258a78..846d09361b33 100644 --- a/llvm/lib/Target/MSP430/MSP430InstrInfo.cpp +++ b/llvm/lib/Target/MSP430/MSP430InstrInfo.cpp @@ -24,7 +24,6 @@ #include "llvm/Support/ErrorHandling.h" #define GET_INSTRINFO_CTOR -#define GET_INSTRINFO_MC_DESC #include "MSP430GenInstrInfo.inc" using namespace llvm; @@ -335,13 +334,3 @@ unsigned MSP430InstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { return 6; } - -MCInstrInfo *createMSP430MCInstrInfo() { - MCInstrInfo *X = new MCInstrInfo(); - InitMSP430MCInstrInfo(X); - return X; -} - -extern "C" void LLVMInitializeMSP430MCInstrInfo() { - TargetRegistry::RegisterMCInstrInfo(TheMSP430Target, createMSP430MCInstrInfo); -} diff --git a/llvm/lib/Target/MSP430/MSP430RegisterInfo.cpp b/llvm/lib/Target/MSP430/MSP430RegisterInfo.cpp index da0c3c6c23d9..1cc60bba3a55 100644 --- a/llvm/lib/Target/MSP430/MSP430RegisterInfo.cpp +++ b/llvm/lib/Target/MSP430/MSP430RegisterInfo.cpp @@ -26,7 +26,6 @@ #include "llvm/ADT/BitVector.h" #include "llvm/Support/ErrorHandling.h" -#define GET_REGINFO_MC_DESC #define GET_REGINFO_TARGET_DESC #include "MSP430GenRegisterInfo.inc" diff --git a/llvm/lib/Target/MSP430/MSP430Subtarget.cpp b/llvm/lib/Target/MSP430/MSP430Subtarget.cpp index 6509d5c2ff3a..b58c50afb982 100644 --- a/llvm/lib/Target/MSP430/MSP430Subtarget.cpp +++ b/llvm/lib/Target/MSP430/MSP430Subtarget.cpp @@ -15,8 +15,6 @@ #include "MSP430.h" #include "llvm/Target/TargetRegistry.h" -#define GET_SUBTARGETINFO_ENUM -#define GET_SUBTARGETINFO_MC_DESC #define GET_SUBTARGETINFO_TARGET_DESC #define GET_SUBTARGETINFO_CTOR #include "MSP430GenSubtargetInfo.inc" @@ -32,15 +30,3 @@ MSP430Subtarget::MSP430Subtarget(const std::string &TT, // Parse features string. ParseSubtargetFeatures(CPUName, FS); } - -MCSubtargetInfo *createMSP430MCSubtargetInfo(StringRef TT, StringRef CPU, - StringRef FS) { - MCSubtargetInfo *X = new MCSubtargetInfo(); - InitMSP430MCSubtargetInfo(X, TT, CPU, FS); - return X; -} - -extern "C" void LLVMInitializeMSP430MCSubtargetInfo() { - TargetRegistry::RegisterMCSubtargetInfo(TheMSP430Target, - createMSP430MCSubtargetInfo); -} diff --git a/llvm/lib/Target/MSP430/Makefile b/llvm/lib/Target/MSP430/Makefile index 30a4e491a653..82216edd81e4 100644 --- a/llvm/lib/Target/MSP430/Makefile +++ b/llvm/lib/Target/MSP430/Makefile @@ -17,7 +17,7 @@ BUILT_SOURCES = MSP430GenRegisterInfo.inc MSP430GenInstrInfo.inc \ MSP430GenDAGISel.inc MSP430GenCallingConv.inc \ MSP430GenSubtargetInfo.inc -DIRS = InstPrinter TargetInfo +DIRS = InstPrinter TargetInfo MCTargetDesc include $(LEVEL)/Makefile.common diff --git a/llvm/lib/Target/Mips/CMakeLists.txt b/llvm/lib/Target/Mips/CMakeLists.txt index ca5f6d355d70..4b3c56e69875 100644 --- a/llvm/lib/Target/Mips/CMakeLists.txt +++ b/llvm/lib/Target/Mips/CMakeLists.txt @@ -28,3 +28,4 @@ add_llvm_target(MipsCodeGen add_subdirectory(InstPrinter) add_subdirectory(TargetInfo) +add_subdirectory(MCTargetDesc) diff --git a/llvm/lib/Target/Mips/MCTargetDesc/CMakeLists.txt b/llvm/lib/Target/Mips/MCTargetDesc/CMakeLists.txt new file mode 100644 index 000000000000..f8f46b3fd957 --- /dev/null +++ b/llvm/lib/Target/Mips/MCTargetDesc/CMakeLists.txt @@ -0,0 +1 @@ +add_llvm_library(LLVMMipsDesc MipsMCTargetDesc.cpp) diff --git a/llvm/lib/Target/Mips/MCTargetDesc/Makefile b/llvm/lib/Target/Mips/MCTargetDesc/Makefile new file mode 100644 index 000000000000..7fe2086a6e00 --- /dev/null +++ b/llvm/lib/Target/Mips/MCTargetDesc/Makefile @@ -0,0 +1,16 @@ +##===- lib/Target/Mips/TargetDesc/Makefile -----------------*- Makefile -*-===## +# +# The LLVM Compiler Infrastructure +# +# This file is distributed under the University of Illinois Open Source +# License. See LICENSE.TXT for details. +# +##===----------------------------------------------------------------------===## + +LEVEL = ../../../.. +LIBRARYNAME = LLVMMipsDesc + +# Hack: we need to include 'main' target directory to grab private headers +CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/.. + +include $(LEVEL)/Makefile.common diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp new file mode 100644 index 000000000000..229d676a8163 --- /dev/null +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp @@ -0,0 +1,52 @@ +//===-- MipsMCTargetDesc.cpp - Mips Target Descriptions ---------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file provides Mips specific target descriptions. +// +//===----------------------------------------------------------------------===// + +#include "MipsMCTargetDesc.h" +#include "llvm/MC/MCInstrInfo.h" +#include "llvm/MC/MCRegisterInfo.h" +#include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/Target/TargetRegistry.h" + +#define GET_INSTRINFO_MC_DESC +#include "MipsGenInstrInfo.inc" + +#define GET_SUBTARGETINFO_MC_DESC +#include "MipsGenSubtargetInfo.inc" + +#define GET_REGINFO_MC_DESC +#include "MipsGenRegisterInfo.inc" + +using namespace llvm; + +MCInstrInfo *createMipsMCInstrInfo() { + MCInstrInfo *X = new MCInstrInfo(); + InitMipsMCInstrInfo(X); + return X; +} + +extern "C" void LLVMInitializeMipsMCInstrInfo() { + TargetRegistry::RegisterMCInstrInfo(TheMipsTarget, createMipsMCInstrInfo); +} + + +MCSubtargetInfo *createMipsMCSubtargetInfo(StringRef TT, StringRef CPU, + StringRef FS) { + MCSubtargetInfo *X = new MCSubtargetInfo(); + InitMipsMCSubtargetInfo(X, TT, CPU, FS); + return X; +} + +extern "C" void LLVMInitializeMipsMCSubtargetInfo() { + TargetRegistry::RegisterMCSubtargetInfo(TheMipsTarget, + createMipsMCSubtargetInfo); +} diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h new file mode 100644 index 000000000000..3d18f114c8bd --- /dev/null +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h @@ -0,0 +1,39 @@ +//===-- AlphaMCTargetDesc.h - Alpha Target Descriptions ---------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file provides Alpha specific target descriptions. +// +//===----------------------------------------------------------------------===// + +#ifndef ALPHAMCTARGETDESC_H +#define ALPHAMCTARGETDESC_H + +namespace llvm { +class MCSubtargetInfo; +class Target; +class StringRef; + +extern Target TheMipsTarget; +extern Target TheMipselTarget; + +} // End llvm namespace + +// Defines symbolic names for Mips registers. This defines a mapping from +// register name to register number. +#define GET_REGINFO_ENUM +#include "MipsGenRegisterInfo.inc" + +// Defines symbolic names for the Mips instructions. +#define GET_INSTRINFO_ENUM +#include "MipsGenInstrInfo.inc" + +#define GET_SUBTARGETINFO_ENUM +#include "MipsGenSubtargetInfo.inc" + +#endif diff --git a/llvm/lib/Target/Mips/Makefile b/llvm/lib/Target/Mips/Makefile index 42962dff159e..cc4a8aef224a 100644 --- a/llvm/lib/Target/Mips/Makefile +++ b/llvm/lib/Target/Mips/Makefile @@ -17,7 +17,7 @@ BUILT_SOURCES = MipsGenRegisterInfo.inc MipsGenInstrInfo.inc \ MipsGenDAGISel.inc MipsGenCallingConv.inc \ MipsGenSubtargetInfo.inc -DIRS = InstPrinter TargetInfo +DIRS = InstPrinter TargetInfo MCTargetDesc include $(LEVEL)/Makefile.common diff --git a/llvm/lib/Target/Mips/Mips.h b/llvm/lib/Target/Mips/Mips.h index 738b48c7fbc1..984b5adfc5f3 100644 --- a/llvm/lib/Target/Mips/Mips.h +++ b/llvm/lib/Target/Mips/Mips.h @@ -15,6 +15,7 @@ #ifndef TARGET_MIPS_H #define TARGET_MIPS_H +#include "MCTargetDesc/MipsMCTargetDesc.h" #include "llvm/Target/TargetMachine.h" namespace llvm { @@ -28,18 +29,6 @@ namespace llvm { FunctionPass *createMipsExpandPseudoPass(MipsTargetMachine &TM); FunctionPass *createMipsEmitGPRestorePass(MipsTargetMachine &TM); - extern Target TheMipsTarget; - extern Target TheMipselTarget; - } // end namespace llvm; -// Defines symbolic names for Mips registers. This defines a mapping from -// register name to register number. -#define GET_REGINFO_ENUM -#include "MipsGenRegisterInfo.inc" - -// Defines symbolic names for the Mips instructions. -#define GET_INSTRINFO_ENUM -#include "MipsGenInstrInfo.inc" - #endif diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.cpp b/llvm/lib/Target/Mips/MipsInstrInfo.cpp index 3305a2ce3283..0a7a7f2dfe4e 100644 --- a/llvm/lib/Target/Mips/MipsInstrInfo.cpp +++ b/llvm/lib/Target/Mips/MipsInstrInfo.cpp @@ -22,7 +22,6 @@ #include "llvm/ADT/STLExtras.h" #define GET_INSTRINFO_CTOR -#define GET_INSTRINFO_MC_DESC #include "MipsGenInstrInfo.inc" using namespace llvm; @@ -460,13 +459,3 @@ unsigned MipsInstrInfo::getGlobalBaseReg(MachineFunction *MF) const { MipsFI->setGlobalBaseReg(GlobalBaseReg); return GlobalBaseReg; } - -MCInstrInfo *createMipsMCInstrInfo() { - MCInstrInfo *X = new MCInstrInfo(); - InitMipsMCInstrInfo(X); - return X; -} - -extern "C" void LLVMInitializeMipsMCInstrInfo() { - TargetRegistry::RegisterMCInstrInfo(TheMipsTarget, createMipsMCInstrInfo); -} diff --git a/llvm/lib/Target/Mips/MipsRegisterInfo.cpp b/llvm/lib/Target/Mips/MipsRegisterInfo.cpp index 99a02eeb71ac..24390daff75c 100644 --- a/llvm/lib/Target/Mips/MipsRegisterInfo.cpp +++ b/llvm/lib/Target/Mips/MipsRegisterInfo.cpp @@ -37,7 +37,6 @@ #include "llvm/ADT/STLExtras.h" #include "llvm/Analysis/DebugInfo.h" -#define GET_REGINFO_MC_DESC #define GET_REGINFO_TARGET_DESC #include "MipsGenRegisterInfo.inc" diff --git a/llvm/lib/Target/Mips/MipsSubtarget.cpp b/llvm/lib/Target/Mips/MipsSubtarget.cpp index 28e3c858e844..6eee3333d584 100644 --- a/llvm/lib/Target/Mips/MipsSubtarget.cpp +++ b/llvm/lib/Target/Mips/MipsSubtarget.cpp @@ -15,8 +15,6 @@ #include "Mips.h" #include "llvm/Target/TargetRegistry.h" -#define GET_SUBTARGETINFO_ENUM -#define GET_SUBTARGETINFO_MC_DESC #define GET_SUBTARGETINFO_TARGET_DESC #define GET_SUBTARGETINFO_CTOR #include "MipsGenSubtargetInfo.inc" @@ -62,15 +60,3 @@ MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU, HasCondMov = true; } } - -MCSubtargetInfo *createMipsMCSubtargetInfo(StringRef TT, StringRef CPU, - StringRef FS) { - MCSubtargetInfo *X = new MCSubtargetInfo(); - InitMipsMCSubtargetInfo(X, TT, CPU, FS); - return X; -} - -extern "C" void LLVMInitializeMipsMCSubtargetInfo() { - TargetRegistry::RegisterMCSubtargetInfo(TheMipsTarget, - createMipsMCSubtargetInfo); -} diff --git a/llvm/lib/Target/PTX/CMakeLists.txt b/llvm/lib/Target/PTX/CMakeLists.txt index 0e138c0e3e77..f0ce67f6f9f3 100644 --- a/llvm/lib/Target/PTX/CMakeLists.txt +++ b/llvm/lib/Target/PTX/CMakeLists.txt @@ -22,3 +22,4 @@ add_llvm_target(PTXCodeGen ) add_subdirectory(TargetInfo) +add_subdirectory(MCTargetDesc) diff --git a/llvm/lib/Target/PTX/MCTargetDesc/CMakeLists.txt b/llvm/lib/Target/PTX/MCTargetDesc/CMakeLists.txt new file mode 100644 index 000000000000..6691d056c825 --- /dev/null +++ b/llvm/lib/Target/PTX/MCTargetDesc/CMakeLists.txt @@ -0,0 +1 @@ +add_llvm_library(LLVMPTXDesc PTXMCTargetDesc.cpp) diff --git a/llvm/lib/Target/PTX/MCTargetDesc/Makefile b/llvm/lib/Target/PTX/MCTargetDesc/Makefile new file mode 100644 index 000000000000..35f5a7b2e6ad --- /dev/null +++ b/llvm/lib/Target/PTX/MCTargetDesc/Makefile @@ -0,0 +1,16 @@ +##===- lib/Target/PTX/TargetDesc/Makefile ------------------*- Makefile -*-===## +# +# The LLVM Compiler Infrastructure +# +# This file is distributed under the University of Illinois Open Source +# License. See LICENSE.TXT for details. +# +##===----------------------------------------------------------------------===## + +LEVEL = ../../../.. +LIBRARYNAME = LLVMPTXDesc + +# Hack: we need to include 'main' target directory to grab private headers +CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/.. + +include $(LEVEL)/Makefile.common diff --git a/llvm/lib/Target/PTX/MCTargetDesc/PTXMCTargetDesc.cpp b/llvm/lib/Target/PTX/MCTargetDesc/PTXMCTargetDesc.cpp new file mode 100644 index 000000000000..64113ad3174b --- /dev/null +++ b/llvm/lib/Target/PTX/MCTargetDesc/PTXMCTargetDesc.cpp @@ -0,0 +1,54 @@ +//===-- PTXMCTargetDesc.cpp - PTX Target Descriptions -----------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file provides PTX specific target descriptions. +// +//===----------------------------------------------------------------------===// + +#include "PTXMCTargetDesc.h" +#include "llvm/MC/MCInstrInfo.h" +#include "llvm/MC/MCRegisterInfo.h" +#include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/Target/TargetRegistry.h" + +#define GET_INSTRINFO_MC_DESC +#include "PTXGenInstrInfo.inc" + +#define GET_SUBTARGETINFO_MC_DESC +#include "PTXGenSubtargetInfo.inc" + +#define GET_REGINFO_MC_DESC +#include "PTXGenRegisterInfo.inc" + +using namespace llvm; + +MCInstrInfo *createPTXMCInstrInfo() { + MCInstrInfo *X = new MCInstrInfo(); + InitPTXMCInstrInfo(X); + return X; +} + +extern "C" void LLVMInitializePTXMCInstrInfo() { + TargetRegistry::RegisterMCInstrInfo(ThePTX32Target, createPTXMCInstrInfo); + TargetRegistry::RegisterMCInstrInfo(ThePTX64Target, createPTXMCInstrInfo); +} + +MCSubtargetInfo *createPTXMCSubtargetInfo(StringRef TT, StringRef CPU, + StringRef FS) { + MCSubtargetInfo *X = new MCSubtargetInfo(); + InitPTXMCSubtargetInfo(X, TT, CPU, FS); + return X; +} + +extern "C" void LLVMInitializePTXMCSubtargetInfo() { + TargetRegistry::RegisterMCSubtargetInfo(ThePTX32Target, + createPTXMCSubtargetInfo); + TargetRegistry::RegisterMCSubtargetInfo(ThePTX64Target, + createPTXMCSubtargetInfo); +} diff --git a/llvm/lib/Target/PTX/MCTargetDesc/PTXMCTargetDesc.h b/llvm/lib/Target/PTX/MCTargetDesc/PTXMCTargetDesc.h new file mode 100644 index 000000000000..1003b0b5ece9 --- /dev/null +++ b/llvm/lib/Target/PTX/MCTargetDesc/PTXMCTargetDesc.h @@ -0,0 +1,38 @@ +//===-- PTXMCTargetDesc.h - PTX Target Descriptions ------------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file provides PTX specific target descriptions. +// +//===----------------------------------------------------------------------===// + +#ifndef PTXMCTARGETDESC_H +#define PTXMCTARGETDESC_H + +namespace llvm { +class MCSubtargetInfo; +class Target; +class StringRef; + +extern Target ThePTX32Target; +extern Target ThePTX64Target; + +} // End llvm namespace + +// Defines symbolic names for PTX registers. +#define GET_REGINFO_ENUM +#include "PTXGenRegisterInfo.inc" + +// Defines symbolic names for the PTX instructions. +#define GET_INSTRINFO_ENUM +#include "PTXGenInstrInfo.inc" + +#define GET_SUBTARGETINFO_ENUM +#include "PTXGenSubtargetInfo.inc" + +#endif diff --git a/llvm/lib/Target/PTX/Makefile b/llvm/lib/Target/PTX/Makefile index da3f91524cbf..93dd38aca7ec 100644 --- a/llvm/lib/Target/PTX/Makefile +++ b/llvm/lib/Target/PTX/Makefile @@ -19,6 +19,6 @@ BUILT_SOURCES = PTXGenAsmWriter.inc \ PTXGenRegisterInfo.inc \ PTXGenSubtargetInfo.inc -DIRS = TargetInfo +DIRS = TargetInfo MCTargetDesc include $(LEVEL)/Makefile.common diff --git a/llvm/lib/Target/PTX/PTX.h b/llvm/lib/Target/PTX/PTX.h index 6aaf0686c2f7..28cab2429c81 100644 --- a/llvm/lib/Target/PTX/PTX.h +++ b/llvm/lib/Target/PTX/PTX.h @@ -15,6 +15,7 @@ #ifndef PTX_H #define PTX_H +#include "MCTargetDesc/PTXMCTargetDesc.h" #include "llvm/Target/TargetMachine.h" namespace llvm { @@ -42,16 +43,6 @@ namespace llvm { FunctionPass *createPTXMFInfoExtract(PTXTargetMachine &TM, CodeGenOpt::Level OptLevel); - extern Target ThePTX32Target; - extern Target ThePTX64Target; } // namespace llvm; -// Defines symbolic names for PTX registers. -#define GET_REGINFO_ENUM -#include "PTXGenRegisterInfo.inc" - -// Defines symbolic names for the PTX instructions. -#define GET_INSTRINFO_ENUM -#include "PTXGenInstrInfo.inc" - #endif // PTX_H diff --git a/llvm/lib/Target/PTX/PTXInstrInfo.cpp b/llvm/lib/Target/PTX/PTXInstrInfo.cpp index caa72b45ff90..425265a2fdb7 100644 --- a/llvm/lib/Target/PTX/PTXInstrInfo.cpp +++ b/llvm/lib/Target/PTX/PTXInstrInfo.cpp @@ -23,7 +23,6 @@ #include "llvm/Support/raw_ostream.h" #define GET_INSTRINFO_CTOR -#define GET_INSTRINFO_MC_DESC #include "PTXGenInstrInfo.inc" using namespace llvm; @@ -409,14 +408,3 @@ MachineBasicBlock *PTXInstrInfo::GetBranchTarget(const MachineInstr& inst) { assert(target.isMBB() && "FIXME: detect branch target operand"); return target.getMBB(); } - -MCInstrInfo *createPTXMCInstrInfo() { - MCInstrInfo *X = new MCInstrInfo(); - InitPTXMCInstrInfo(X); - return X; -} - -extern "C" void LLVMInitializePTXMCInstrInfo() { - TargetRegistry::RegisterMCInstrInfo(ThePTX32Target, createPTXMCInstrInfo); - TargetRegistry::RegisterMCInstrInfo(ThePTX64Target, createPTXMCInstrInfo); -} diff --git a/llvm/lib/Target/PTX/PTXRegisterInfo.cpp b/llvm/lib/Target/PTX/PTXRegisterInfo.cpp index f32c2b70a3bc..cb56ea98a2b8 100644 --- a/llvm/lib/Target/PTX/PTXRegisterInfo.cpp +++ b/llvm/lib/Target/PTX/PTXRegisterInfo.cpp @@ -17,7 +17,6 @@ #include "llvm/Support/Debug.h" #include "llvm/Support/raw_ostream.h" -#define GET_REGINFO_MC_DESC #define GET_REGINFO_TARGET_DESC #include "PTXGenRegisterInfo.inc" diff --git a/llvm/lib/Target/PTX/PTXSubtarget.cpp b/llvm/lib/Target/PTX/PTXSubtarget.cpp index ff051672a3e2..8ec646e46f68 100644 --- a/llvm/lib/Target/PTX/PTXSubtarget.cpp +++ b/llvm/lib/Target/PTX/PTXSubtarget.cpp @@ -16,8 +16,6 @@ #include "llvm/Support/ErrorHandling.h" #include "llvm/Target/TargetRegistry.h" -#define GET_SUBTARGETINFO_ENUM -#define GET_SUBTARGETINFO_MC_DESC #define GET_SUBTARGETINFO_TARGET_DESC #define GET_SUBTARGETINFO_CTOR #include "PTXGenSubtargetInfo.inc" @@ -66,18 +64,3 @@ std::string PTXSubtarget::getPTXVersionString() const { case PTX_VERSION_2_3: return "2.3"; } } - - -MCSubtargetInfo *createPTXMCSubtargetInfo(StringRef TT, StringRef CPU, - StringRef FS) { - MCSubtargetInfo *X = new MCSubtargetInfo(); - InitPTXMCSubtargetInfo(X, TT, CPU, FS); - return X; -} - -extern "C" void LLVMInitializePTXMCSubtargetInfo() { - TargetRegistry::RegisterMCSubtargetInfo(ThePTX32Target, - createPTXMCSubtargetInfo); - TargetRegistry::RegisterMCSubtargetInfo(ThePTX64Target, - createPTXMCSubtargetInfo); -} diff --git a/llvm/lib/Target/PowerPC/CMakeLists.txt b/llvm/lib/Target/PowerPC/CMakeLists.txt index be1b525e27df..a6cbb734c456 100644 --- a/llvm/lib/Target/PowerPC/CMakeLists.txt +++ b/llvm/lib/Target/PowerPC/CMakeLists.txt @@ -32,3 +32,4 @@ add_llvm_target(PowerPCCodeGen add_subdirectory(InstPrinter) add_subdirectory(TargetInfo) +add_subdirectory(MCTargetDesc) diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/CMakeLists.txt b/llvm/lib/Target/PowerPC/MCTargetDesc/CMakeLists.txt new file mode 100644 index 000000000000..e6529543b405 --- /dev/null +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/CMakeLists.txt @@ -0,0 +1 @@ +add_llvm_library(LLVMPowerPCDesc PPCMCTargetDesc.cpp) diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/Makefile b/llvm/lib/Target/PowerPC/MCTargetDesc/Makefile new file mode 100644 index 000000000000..9db66622cced --- /dev/null +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/Makefile @@ -0,0 +1,16 @@ +##===- lib/Target/PowerPC/TargetDesc/Makefile --------------*- Makefile -*-===## +# +# The LLVM Compiler Infrastructure +# +# This file is distributed under the University of Illinois Open Source +# License. See LICENSE.TXT for details. +# +##===----------------------------------------------------------------------===## + +LEVEL = ../../../.. +LIBRARYNAME = LLVMPowerPCDesc + +# Hack: we need to include 'main' target directory to grab private headers +CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/.. + +include $(LEVEL)/Makefile.common diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp new file mode 100644 index 000000000000..93d225e4ef37 --- /dev/null +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp @@ -0,0 +1,55 @@ +//===-- PPCMCTargetDesc.cpp - PowerPC Target Descriptions -------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file provides PowerPC specific target descriptions. +// +//===----------------------------------------------------------------------===// + +#include "PPCMCTargetDesc.h" +#include "llvm/MC/MCInstrInfo.h" +#include "llvm/MC/MCRegisterInfo.h" +#include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/Target/TargetRegistry.h" + +#define GET_INSTRINFO_MC_DESC +#include "PPCGenInstrInfo.inc" + +#define GET_SUBTARGETINFO_MC_DESC +#include "PPCGenSubtargetInfo.inc" + +#define GET_REGINFO_MC_DESC +#include "PPCGenRegisterInfo.inc" + +using namespace llvm; + +MCInstrInfo *createPPCMCInstrInfo() { + MCInstrInfo *X = new MCInstrInfo(); + InitPPCMCInstrInfo(X); + return X; +} + +extern "C" void LLVMInitializePowerPCMCInstrInfo() { + TargetRegistry::RegisterMCInstrInfo(ThePPC32Target, createPPCMCInstrInfo); + TargetRegistry::RegisterMCInstrInfo(ThePPC64Target, createPPCMCInstrInfo); +} + + +MCSubtargetInfo *createPPCMCSubtargetInfo(StringRef TT, StringRef CPU, + StringRef FS) { + MCSubtargetInfo *X = new MCSubtargetInfo(); + InitPPCMCSubtargetInfo(X, TT, CPU, FS); + return X; +} + +extern "C" void LLVMInitializePowerPCMCSubtargetInfo() { + TargetRegistry::RegisterMCSubtargetInfo(ThePPC32Target, + createPPCMCSubtargetInfo); + TargetRegistry::RegisterMCSubtargetInfo(ThePPC64Target, + createPPCMCSubtargetInfo); +} diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h new file mode 100644 index 000000000000..cee235097a0a --- /dev/null +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h @@ -0,0 +1,41 @@ +//===-- PPCMCTargetDesc.h - PowerPC Target Descriptions ---------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file provides PowerPC specific target descriptions. +// +//===----------------------------------------------------------------------===// + +#ifndef PPCMCTARGETDESC_H +#define PPCMCTARGETDESC_H + +namespace llvm { +class MCSubtargetInfo; +class Target; +class StringRef; + +extern Target ThePPC32Target; +extern Target ThePPC64Target; + +} // End llvm namespace + +// Defines symbolic names for PowerPC registers. This defines a mapping from +// register name to register number. +// +#define GET_REGINFO_ENUM +#include "PPCGenRegisterInfo.inc" + +// Defines symbolic names for the PowerPC instructions. +// +#define GET_INSTRINFO_ENUM +#include "PPCGenInstrInfo.inc" + +#define GET_SUBTARGETINFO_ENUM +#include "PPCGenSubtargetInfo.inc" + +#endif diff --git a/llvm/lib/Target/PowerPC/Makefile b/llvm/lib/Target/PowerPC/Makefile index 11abb9728be4..1617b26ca4a5 100644 --- a/llvm/lib/Target/PowerPC/Makefile +++ b/llvm/lib/Target/PowerPC/Makefile @@ -18,6 +18,6 @@ BUILT_SOURCES = PPCGenRegisterInfo.inc \ PPCGenSubtargetInfo.inc PPCGenCallingConv.inc \ PPCGenMCCodeEmitter.inc -DIRS = InstPrinter TargetInfo +DIRS = InstPrinter TargetInfo MCTargetDesc include $(LEVEL)/Makefile.common diff --git a/llvm/lib/Target/PowerPC/PPC.h b/llvm/lib/Target/PowerPC/PPC.h index 3c030a683565..7191dd105f3c 100644 --- a/llvm/lib/Target/PowerPC/PPC.h +++ b/llvm/lib/Target/PowerPC/PPC.h @@ -15,6 +15,7 @@ #ifndef LLVM_TARGET_POWERPC_H #define LLVM_TARGET_POWERPC_H +#include "MCTargetDesc/PPCMCTargetDesc.h" #include // GCC #defines PPC on Linux but we use it as our namespace name @@ -48,9 +49,6 @@ namespace llvm { void LowerPPCMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, AsmPrinter &AP, bool isDarwin); - extern Target ThePPC32Target; - extern Target ThePPC64Target; - namespace PPCII { /// Target Operand Flag enum. @@ -84,15 +82,4 @@ namespace llvm { } // end namespace llvm; -// Defines symbolic names for PowerPC registers. This defines a mapping from -// register name to register number. -// -#define GET_REGINFO_ENUM -#include "PPCGenRegisterInfo.inc" - -// Defines symbolic names for the PowerPC instructions. -// -#define GET_INSTRINFO_ENUM -#include "PPCGenInstrInfo.inc" - #endif diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp index 28d8f13bfc16..143444fdc22b 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -31,7 +31,6 @@ #include "llvm/ADT/STLExtras.h" #define GET_INSTRINFO_CTOR -#define GET_INSTRINFO_MC_DESC #include "PPCGenInstrInfo.inc" namespace llvm { @@ -654,14 +653,3 @@ unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { return 4; // PowerPC instructions are all 4 bytes } } - -MCInstrInfo *createPPCMCInstrInfo() { - MCInstrInfo *X = new MCInstrInfo(); - InitPPCMCInstrInfo(X); - return X; -} - -extern "C" void LLVMInitializePowerPCMCInstrInfo() { - TargetRegistry::RegisterMCInstrInfo(ThePPC32Target, createPPCMCInstrInfo); - TargetRegistry::RegisterMCInstrInfo(ThePPC64Target, createPPCMCInstrInfo); -} diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp index db139dae6942..9c2428b92e65 100644 --- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp @@ -44,7 +44,6 @@ #include "llvm/ADT/STLExtras.h" #include -#define GET_REGINFO_MC_DESC #define GET_REGINFO_TARGET_DESC #include "PPCGenRegisterInfo.inc" diff --git a/llvm/lib/Target/PowerPC/PPCSubtarget.cpp b/llvm/lib/Target/PowerPC/PPCSubtarget.cpp index 8abc27a83845..5ea9b0f6596c 100644 --- a/llvm/lib/Target/PowerPC/PPCSubtarget.cpp +++ b/llvm/lib/Target/PowerPC/PPCSubtarget.cpp @@ -18,8 +18,6 @@ #include "llvm/Target/TargetRegistry.h" #include -#define GET_SUBTARGETINFO_ENUM -#define GET_SUBTARGETINFO_MC_DESC #define GET_SUBTARGETINFO_TARGET_DESC #define GET_SUBTARGETINFO_CTOR #include "PPCGenSubtargetInfo.inc" @@ -141,17 +139,3 @@ bool PPCSubtarget::hasLazyResolverStub(const GlobalValue *GV, return GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() || GV->hasCommonLinkage() || isDecl; } - -MCSubtargetInfo *createPPCMCSubtargetInfo(StringRef TT, StringRef CPU, - StringRef FS) { - MCSubtargetInfo *X = new MCSubtargetInfo(); - InitPPCMCSubtargetInfo(X, TT, CPU, FS); - return X; -} - -extern "C" void LLVMInitializePowerPCMCSubtargetInfo() { - TargetRegistry::RegisterMCSubtargetInfo(ThePPC32Target, - createPPCMCSubtargetInfo); - TargetRegistry::RegisterMCSubtargetInfo(ThePPC64Target, - createPPCMCSubtargetInfo); -} diff --git a/llvm/lib/Target/Sparc/CMakeLists.txt b/llvm/lib/Target/Sparc/CMakeLists.txt index e1f54fb63ff5..38e029acd7c0 100644 --- a/llvm/lib/Target/Sparc/CMakeLists.txt +++ b/llvm/lib/Target/Sparc/CMakeLists.txt @@ -23,3 +23,4 @@ add_llvm_target(SparcCodeGen ) add_subdirectory(TargetInfo) +add_subdirectory(MCTargetDesc) diff --git a/llvm/lib/Target/Sparc/MCTargetDesc/CMakeLists.txt b/llvm/lib/Target/Sparc/MCTargetDesc/CMakeLists.txt new file mode 100644 index 000000000000..9c8633fcdfdf --- /dev/null +++ b/llvm/lib/Target/Sparc/MCTargetDesc/CMakeLists.txt @@ -0,0 +1 @@ +add_llvm_library(LLVMSparcDesc SparcMCTargetDesc.cpp) diff --git a/llvm/lib/Target/Sparc/MCTargetDesc/Makefile b/llvm/lib/Target/Sparc/MCTargetDesc/Makefile new file mode 100644 index 000000000000..abcbe2da18ec --- /dev/null +++ b/llvm/lib/Target/Sparc/MCTargetDesc/Makefile @@ -0,0 +1,16 @@ +##===- lib/Target/Sparc/TargetDesc/Makefile ----------------*- Makefile -*-===## +# +# The LLVM Compiler Infrastructure +# +# This file is distributed under the University of Illinois Open Source +# License. See LICENSE.TXT for details. +# +##===----------------------------------------------------------------------===## + +LEVEL = ../../../.. +LIBRARYNAME = LLVMSparcDesc + +# Hack: we need to include 'main' target directory to grab private headers +CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/.. + +include $(LEVEL)/Makefile.common diff --git a/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp b/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp new file mode 100644 index 000000000000..96cd03d91b6f --- /dev/null +++ b/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp @@ -0,0 +1,51 @@ +//===-- SparcMCTargetDesc.cpp - Sparc Target Descriptions --------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file provides Sparc specific target descriptions. +// +//===----------------------------------------------------------------------===// + +#include "SparcMCTargetDesc.h" +#include "llvm/MC/MCInstrInfo.h" +#include "llvm/MC/MCRegisterInfo.h" +#include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/Target/TargetRegistry.h" + +#define GET_INSTRINFO_MC_DESC +#include "SparcGenInstrInfo.inc" + +#define GET_SUBTARGETINFO_MC_DESC +#include "SparcGenSubtargetInfo.inc" + +#define GET_REGINFO_MC_DESC +#include "SparcGenRegisterInfo.inc" + +using namespace llvm; + +MCInstrInfo *createSparcMCInstrInfo() { + MCInstrInfo *X = new MCInstrInfo(); + InitSparcMCInstrInfo(X); + return X; +} + +extern "C" void LLVMInitializeSparcMCInstrInfo() { + TargetRegistry::RegisterMCInstrInfo(TheSparcTarget, createSparcMCInstrInfo); +} + +MCSubtargetInfo *createSparcMCSubtargetInfo(StringRef TT, StringRef CPU, + StringRef FS) { + MCSubtargetInfo *X = new MCSubtargetInfo(); + InitSparcMCSubtargetInfo(X, TT, CPU, FS); + return X; +} + +extern "C" void LLVMInitializeSparcMCSubtargetInfo() { + TargetRegistry::RegisterMCSubtargetInfo(TheSparcTarget, + createSparcMCSubtargetInfo); +} diff --git a/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h b/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h new file mode 100644 index 000000000000..2fd9e3f4cbd3 --- /dev/null +++ b/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h @@ -0,0 +1,41 @@ +//===-- SparcMCTargetDesc.h - Sparc Target Descriptions ---------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file provides Sparc specific target descriptions. +// +//===----------------------------------------------------------------------===// + +#ifndef SPARCMCTARGETDESC_H +#define SPARCMCTARGETDESC_H + +namespace llvm { +class MCSubtargetInfo; +class Target; +class StringRef; + +extern Target TheSparcTarget; +extern Target TheSparcV9Target; + +} // End llvm namespace + +// Defines symbolic names for Sparc registers. This defines a mapping from +// register name to register number. +// +#define GET_REGINFO_ENUM +#include "SparcGenRegisterInfo.inc" + +// Defines symbolic names for the Sparc instructions. +// +#define GET_INSTRINFO_ENUM +#include "SparcGenInstrInfo.inc" + +#define GET_SUBTARGETINFO_ENUM +#include "SparcGenSubtargetInfo.inc" + +#endif diff --git a/llvm/lib/Target/Sparc/Makefile b/llvm/lib/Target/Sparc/Makefile index 89f5053383eb..4b81ada956f2 100644 --- a/llvm/lib/Target/Sparc/Makefile +++ b/llvm/lib/Target/Sparc/Makefile @@ -16,7 +16,7 @@ BUILT_SOURCES = SparcGenRegisterInfo.inc SparcGenInstrInfo.inc \ SparcGenAsmWriter.inc SparcGenDAGISel.inc \ SparcGenSubtargetInfo.inc SparcGenCallingConv.inc -DIRS = TargetInfo +DIRS = TargetInfo MCTargetDesc include $(LEVEL)/Makefile.common diff --git a/llvm/lib/Target/Sparc/Sparc.h b/llvm/lib/Target/Sparc/Sparc.h index d68535b60462..7b2c6141dbf8 100644 --- a/llvm/lib/Target/Sparc/Sparc.h +++ b/llvm/lib/Target/Sparc/Sparc.h @@ -15,6 +15,7 @@ #ifndef TARGET_SPARC_H #define TARGET_SPARC_H +#include "MCTargetDesc/SparcMCTargetDesc.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Target/TargetMachine.h" #include @@ -28,23 +29,8 @@ namespace llvm { FunctionPass *createSparcDelaySlotFillerPass(TargetMachine &TM); FunctionPass *createSparcFPMoverPass(TargetMachine &TM); - extern Target TheSparcTarget; - extern Target TheSparcV9Target; - } // end namespace llvm; -// Defines symbolic names for Sparc registers. This defines a mapping from -// register name to register number. -// -#define GET_REGINFO_ENUM -#include "SparcGenRegisterInfo.inc" - -// Defines symbolic names for the Sparc instructions. -// -#define GET_INSTRINFO_ENUM -#include "SparcGenInstrInfo.inc" - - namespace llvm { // Enums corresponding to Sparc condition codes, both icc's and fcc's. These // values must be kept in sync with the ones in the .td file. diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.cpp b/llvm/lib/Target/Sparc/SparcInstrInfo.cpp index 5738c1dd7fc1..4e3ddf839985 100644 --- a/llvm/lib/Target/Sparc/SparcInstrInfo.cpp +++ b/llvm/lib/Target/Sparc/SparcInstrInfo.cpp @@ -23,7 +23,6 @@ #include "llvm/ADT/SmallVector.h" #define GET_INSTRINFO_CTOR -#define GET_INSTRINFO_MC_DESC #include "SparcGenInstrInfo.inc" using namespace llvm; @@ -345,13 +344,3 @@ unsigned SparcInstrInfo::getGlobalBaseReg(MachineFunction *MF) const SparcFI->setGlobalBaseReg(GlobalBaseReg); return GlobalBaseReg; } - -MCInstrInfo *createSparcMCInstrInfo() { - MCInstrInfo *X = new MCInstrInfo(); - InitSparcMCInstrInfo(X); - return X; -} - -extern "C" void LLVMInitializeSparcMCInstrInfo() { - TargetRegistry::RegisterMCInstrInfo(TheSparcTarget, createSparcMCInstrInfo); -} diff --git a/llvm/lib/Target/Sparc/SparcRegisterInfo.cpp b/llvm/lib/Target/Sparc/SparcRegisterInfo.cpp index 3b0b5fa06758..0acdd2c55d6b 100644 --- a/llvm/lib/Target/Sparc/SparcRegisterInfo.cpp +++ b/llvm/lib/Target/Sparc/SparcRegisterInfo.cpp @@ -24,7 +24,6 @@ #include "llvm/ADT/BitVector.h" #include "llvm/ADT/STLExtras.h" -#define GET_REGINFO_MC_DESC #define GET_REGINFO_TARGET_DESC #include "SparcGenRegisterInfo.inc" diff --git a/llvm/lib/Target/Sparc/SparcSubtarget.cpp b/llvm/lib/Target/Sparc/SparcSubtarget.cpp index 31e20eb3447f..de647e8221a2 100644 --- a/llvm/lib/Target/Sparc/SparcSubtarget.cpp +++ b/llvm/lib/Target/Sparc/SparcSubtarget.cpp @@ -15,8 +15,6 @@ #include "Sparc.h" #include "llvm/Target/TargetRegistry.h" -#define GET_SUBTARGETINFO_ENUM -#define GET_SUBTARGETINFO_MC_DESC #define GET_SUBTARGETINFO_TARGET_DESC #define GET_SUBTARGETINFO_CTOR #include "SparcGenSubtargetInfo.inc" @@ -44,15 +42,3 @@ SparcSubtarget::SparcSubtarget(const std::string &TT, const std::string &CPU, // Parse features string. ParseSubtargetFeatures(CPUName, FS); } - -MCSubtargetInfo *createSparcMCSubtargetInfo(StringRef TT, StringRef CPU, - StringRef FS) { - MCSubtargetInfo *X = new MCSubtargetInfo(); - InitSparcMCSubtargetInfo(X, TT, CPU, FS); - return X; -} - -extern "C" void LLVMInitializeSparcMCSubtargetInfo() { - TargetRegistry::RegisterMCSubtargetInfo(TheSparcTarget, - createSparcMCSubtargetInfo); -} diff --git a/llvm/lib/Target/SystemZ/CMakeLists.txt b/llvm/lib/Target/SystemZ/CMakeLists.txt index 12206b9718e4..218ee1380a33 100644 --- a/llvm/lib/Target/SystemZ/CMakeLists.txt +++ b/llvm/lib/Target/SystemZ/CMakeLists.txt @@ -21,3 +21,4 @@ add_llvm_target(SystemZCodeGen ) add_subdirectory(TargetInfo) +add_subdirectory(MCTargetDesc) diff --git a/llvm/lib/Target/SystemZ/MCTargetDesc/CMakeLists.txt b/llvm/lib/Target/SystemZ/MCTargetDesc/CMakeLists.txt new file mode 100644 index 000000000000..f7fab5f4977e --- /dev/null +++ b/llvm/lib/Target/SystemZ/MCTargetDesc/CMakeLists.txt @@ -0,0 +1 @@ +add_llvm_library(LLVMSystemZDesc SystemZMCTargetDesc.cpp) diff --git a/llvm/lib/Target/SystemZ/MCTargetDesc/Makefile b/llvm/lib/Target/SystemZ/MCTargetDesc/Makefile new file mode 100644 index 000000000000..08f1a9d51fb5 --- /dev/null +++ b/llvm/lib/Target/SystemZ/MCTargetDesc/Makefile @@ -0,0 +1,16 @@ +##===- lib/Target/SystemZ/TargetDesc/Makefile --------------*- Makefile -*-===## +# +# The LLVM Compiler Infrastructure +# +# This file is distributed under the University of Illinois Open Source +# License. See LICENSE.TXT for details. +# +##===----------------------------------------------------------------------===## + +LEVEL = ../../../.. +LIBRARYNAME = LLVMSystemZDesc + +# Hack: we need to include 'main' target directory to grab private headers +CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/.. + +include $(LEVEL)/Makefile.common diff --git a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp new file mode 100644 index 000000000000..c52ceceb4927 --- /dev/null +++ b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp @@ -0,0 +1,52 @@ +//===-- SystemZMCTargetDesc.cpp - SystemZ Target Descriptions ---*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file provides SystemZ specific target descriptions. +// +//===----------------------------------------------------------------------===// + +#include "SystemZMCTargetDesc.h" +#include "llvm/MC/MCInstrInfo.h" +#include "llvm/MC/MCRegisterInfo.h" +#include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/Target/TargetRegistry.h" + +#define GET_INSTRINFO_MC_DESC +#include "SystemZGenInstrInfo.inc" + +#define GET_SUBTARGETINFO_MC_DESC +#include "SystemZGenSubtargetInfo.inc" + +#define GET_REGINFO_MC_DESC +#include "SystemZGenRegisterInfo.inc" + +using namespace llvm; + +MCInstrInfo *createSystemZMCInstrInfo() { + MCInstrInfo *X = new MCInstrInfo(); + InitSystemZMCInstrInfo(X); + return X; +} + +extern "C" void LLVMInitializeSystemZMCInstrInfo() { + TargetRegistry::RegisterMCInstrInfo(TheSystemZTarget, + createSystemZMCInstrInfo); +} + +MCSubtargetInfo *createSystemZMCSubtargetInfo(StringRef TT, StringRef CPU, + StringRef FS) { + MCSubtargetInfo *X = new MCSubtargetInfo(); + InitSystemZMCSubtargetInfo(X, TT, CPU, FS); + return X; +} + +extern "C" void LLVMInitializeSystemZMCSubtargetInfo() { + TargetRegistry::RegisterMCSubtargetInfo(TheSystemZTarget, + createSystemZMCSubtargetInfo); +} diff --git a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h new file mode 100644 index 000000000000..e2ad5afd6e57 --- /dev/null +++ b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h @@ -0,0 +1,38 @@ +//===-- SystemZMCTargetDesc.h - SystemZ Target Descriptions -----*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file provides SystemZ specific target descriptions. +// +//===----------------------------------------------------------------------===// + +#ifndef SYSTEMZMCTARGETDESC_H +#define SYSTEMZMCTARGETDESC_H + +namespace llvm { +class MCSubtargetInfo; +class Target; +class StringRef; + +extern Target TheSystemZTarget; + +} // End llvm namespace + +// Defines symbolic names for SystemZ registers. +// This defines a mapping from register name to register number. +#define GET_REGINFO_ENUM +#include "SystemZGenRegisterInfo.inc" + +// Defines symbolic names for the SystemZ instructions. +#define GET_INSTRINFO_ENUM +#include "SystemZGenInstrInfo.inc" + +#define GET_SUBTARGETINFO_ENUM +#include "SystemZGenSubtargetInfo.inc" + +#endif diff --git a/llvm/lib/Target/SystemZ/Makefile b/llvm/lib/Target/SystemZ/Makefile index fa59dc6f1d0b..6356491debeb 100644 --- a/llvm/lib/Target/SystemZ/Makefile +++ b/llvm/lib/Target/SystemZ/Makefile @@ -16,7 +16,7 @@ BUILT_SOURCES = SystemZGenRegisterInfo.inc SystemZGenInstrInfo.inc \ SystemZGenAsmWriter.inc SystemZGenDAGISel.inc \ SystemZGenSubtargetInfo.inc SystemZGenCallingConv.inc -DIRS = TargetInfo +DIRS = TargetInfo MCTargetDesc include $(LEVEL)/Makefile.common diff --git a/llvm/lib/Target/SystemZ/SystemZ.h b/llvm/lib/Target/SystemZ/SystemZ.h index 84d83c00d946..88960b9cc601 100644 --- a/llvm/lib/Target/SystemZ/SystemZ.h +++ b/llvm/lib/Target/SystemZ/SystemZ.h @@ -15,6 +15,7 @@ #ifndef LLVM_TARGET_SystemZ_H #define LLVM_TARGET_SystemZ_H +#include "MCTargetDesc/SystemZMCTargetDesc.h" #include "llvm/Target/TargetMachine.h" namespace llvm { @@ -47,17 +48,5 @@ namespace llvm { FunctionPass *createSystemZISelDag(SystemZTargetMachine &TM, CodeGenOpt::Level OptLevel); - extern Target TheSystemZTarget; - } // end namespace llvm; - -// Defines symbolic names for SystemZ registers. -// This defines a mapping from register name to register number. -#define GET_REGINFO_ENUM -#include "SystemZGenRegisterInfo.inc" - -// Defines symbolic names for the SystemZ instructions. -#define GET_INSTRINFO_ENUM -#include "SystemZGenInstrInfo.inc" - #endif diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp index ae41d68d3e58..99e2730609e8 100644 --- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp +++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp @@ -25,7 +25,6 @@ #include "llvm/Support/ErrorHandling.h" #define GET_INSTRINFO_CTOR -#define GET_INSTRINFO_MC_DESC #include "SystemZGenInstrInfo.inc" using namespace llvm; @@ -438,14 +437,3 @@ SystemZInstrInfo::getLongDispOpc(unsigned Opc) const { case SystemZ::MOV64Prm: return get(SystemZ::MOV64Prmy); } } - -MCInstrInfo *createSystemZMCInstrInfo() { - MCInstrInfo *X = new MCInstrInfo(); - InitSystemZMCInstrInfo(X); - return X; -} - -extern "C" void LLVMInitializeSystemZMCInstrInfo() { - TargetRegistry::RegisterMCInstrInfo(TheSystemZTarget, - createSystemZMCInstrInfo); -} diff --git a/llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp b/llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp index 21421a9bf72d..59692e883366 100644 --- a/llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp +++ b/llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp @@ -26,7 +26,6 @@ #include "llvm/Target/TargetOptions.h" #include "llvm/ADT/BitVector.h" -#define GET_REGINFO_MC_DESC #define GET_REGINFO_TARGET_DESC #include "SystemZGenRegisterInfo.inc" diff --git a/llvm/lib/Target/SystemZ/SystemZSubtarget.cpp b/llvm/lib/Target/SystemZ/SystemZSubtarget.cpp index fe3046b0cb00..b3ed06639758 100644 --- a/llvm/lib/Target/SystemZ/SystemZSubtarget.cpp +++ b/llvm/lib/Target/SystemZ/SystemZSubtarget.cpp @@ -17,8 +17,6 @@ #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetRegistry.h" -#define GET_SUBTARGETINFO_ENUM -#define GET_SUBTARGETINFO_MC_DESC #define GET_SUBTARGETINFO_TARGET_DESC #define GET_SUBTARGETINFO_CTOR #include "SystemZGenSubtargetInfo.inc" @@ -54,15 +52,3 @@ bool SystemZSubtarget::GVRequiresExtraLoad(const GlobalValue* GV, return false; } - -MCSubtargetInfo *createSystemZMCSubtargetInfo(StringRef TT, StringRef CPU, - StringRef FS) { - MCSubtargetInfo *X = new MCSubtargetInfo(); - InitSystemZMCSubtargetInfo(X, TT, CPU, FS); - return X; -} - -extern "C" void LLVMInitializeSystemZMCSubtargetInfo() { - TargetRegistry::RegisterMCSubtargetInfo(TheSystemZTarget, - createSystemZMCSubtargetInfo); -} diff --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp index 77f5c125aa19..d45dd352fbc4 100644 --- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp +++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp @@ -28,9 +28,6 @@ #include "llvm/Support/SourceMgr.h" #include "llvm/Support/raw_ostream.h" -#define GET_SUBTARGETINFO_ENUM -#include "X86GenSubtargetInfo.inc" - using namespace llvm; namespace { diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp index 04cb459a7f21..bbfe4286e48f 100644 --- a/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp +++ b/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp @@ -25,7 +25,6 @@ #define GET_INSTRINFO_MC_DESC #include "X86GenInstrInfo.inc" -#define GET_SUBTARGETINFO_ENUM #define GET_SUBTARGETINFO_MC_DESC #include "X86GenSubtargetInfo.inc" diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h b/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h index 5294a4fa5b52..89ea22b31be2 100644 --- a/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h +++ b/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h @@ -54,4 +54,7 @@ namespace X86_MC { #define GET_INSTRINFO_ENUM #include "X86GenInstrInfo.inc" +#define GET_SUBTARGETINFO_ENUM +#include "X86GenSubtargetInfo.inc" + #endif diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp index 0509a1515a74..55b5835f52a7 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.cpp +++ b/llvm/lib/Target/X86/X86InstrInfo.cpp @@ -36,7 +36,6 @@ #include #define GET_INSTRINFO_CTOR -#define GET_INSTRINFO_MC_DESC #include "X86GenInstrInfo.inc" using namespace llvm; diff --git a/llvm/lib/Target/X86/X86MCCodeEmitter.cpp b/llvm/lib/Target/X86/X86MCCodeEmitter.cpp index c37a02829788..ce8ef495c001 100644 --- a/llvm/lib/Target/X86/X86MCCodeEmitter.cpp +++ b/llvm/lib/Target/X86/X86MCCodeEmitter.cpp @@ -22,9 +22,6 @@ #include "llvm/MC/MCSymbol.h" #include "llvm/Support/raw_ostream.h" -#define GET_SUBTARGETINFO_ENUM -#include "X86GenSubtargetInfo.inc" - using namespace llvm; namespace { diff --git a/llvm/lib/Target/X86/X86RegisterInfo.cpp b/llvm/lib/Target/X86/X86RegisterInfo.cpp index c116dcbaa2d8..f2faf59367a1 100644 --- a/llvm/lib/Target/X86/X86RegisterInfo.cpp +++ b/llvm/lib/Target/X86/X86RegisterInfo.cpp @@ -40,7 +40,6 @@ #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/CommandLine.h" -#define GET_REGINFO_MC_DESC #define GET_REGINFO_TARGET_DESC #include "X86GenRegisterInfo.inc" diff --git a/llvm/lib/Target/X86/X86Subtarget.cpp b/llvm/lib/Target/X86/X86Subtarget.cpp index d588934fc924..5e6c659e5393 100644 --- a/llvm/lib/Target/X86/X86Subtarget.cpp +++ b/llvm/lib/Target/X86/X86Subtarget.cpp @@ -21,8 +21,6 @@ #include "llvm/Target/TargetMachine.h" #include "llvm/ADT/SmallVector.h" -#define GET_SUBTARGETINFO_ENUM -#define GET_SUBTARGETINFO_MC_DESC #define GET_SUBTARGETINFO_TARGET_DESC #define GET_SUBTARGETINFO_CTOR #include "X86GenSubtargetInfo.inc" diff --git a/llvm/lib/Target/XCore/CMakeLists.txt b/llvm/lib/Target/XCore/CMakeLists.txt index 59c7f51cebde..98c3cfda60c7 100644 --- a/llvm/lib/Target/XCore/CMakeLists.txt +++ b/llvm/lib/Target/XCore/CMakeLists.txt @@ -22,3 +22,4 @@ add_llvm_target(XCoreCodeGen ) add_subdirectory(TargetInfo) +add_subdirectory(MCTargetDesc) diff --git a/llvm/lib/Target/XCore/MCTargetDesc/CMakeLists.txt b/llvm/lib/Target/XCore/MCTargetDesc/CMakeLists.txt new file mode 100644 index 000000000000..849413f3de5f --- /dev/null +++ b/llvm/lib/Target/XCore/MCTargetDesc/CMakeLists.txt @@ -0,0 +1 @@ +add_llvm_library(LLVMXCoreDesc XCoreMCTargetDesc.cpp) diff --git a/llvm/lib/Target/XCore/MCTargetDesc/Makefile b/llvm/lib/Target/XCore/MCTargetDesc/Makefile new file mode 100644 index 000000000000..de61543bfe9c --- /dev/null +++ b/llvm/lib/Target/XCore/MCTargetDesc/Makefile @@ -0,0 +1,16 @@ +##===- lib/Target/XCore/TargetDesc/Makefile ----------------*- Makefile -*-===## +# +# The LLVM Compiler Infrastructure +# +# This file is distributed under the University of Illinois Open Source +# License. See LICENSE.TXT for details. +# +##===----------------------------------------------------------------------===## + +LEVEL = ../../../.. +LIBRARYNAME = LLVMXCoreDesc + +# Hack: we need to include 'main' target directory to grab private headers +CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/.. + +include $(LEVEL)/Makefile.common diff --git a/llvm/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp b/llvm/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp new file mode 100644 index 000000000000..c2f8238e73c8 --- /dev/null +++ b/llvm/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp @@ -0,0 +1,51 @@ +//===-- XCoreMCTargetDesc.cpp - XCore Target Descriptions -------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file provides XCore specific target descriptions. +// +//===----------------------------------------------------------------------===// + +#include "XCoreMCTargetDesc.h" +#include "llvm/MC/MCInstrInfo.h" +#include "llvm/MC/MCRegisterInfo.h" +#include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/Target/TargetRegistry.h" + +#define GET_INSTRINFO_MC_DESC +#include "XCoreGenInstrInfo.inc" + +#define GET_SUBTARGETINFO_MC_DESC +#include "XCoreGenSubtargetInfo.inc" + +#define GET_REGINFO_MC_DESC +#include "XCoreGenRegisterInfo.inc" + +using namespace llvm; + +MCInstrInfo *createXCoreMCInstrInfo() { + MCInstrInfo *X = new MCInstrInfo(); + InitXCoreMCInstrInfo(X); + return X; +} + +extern "C" void LLVMInitializeXCoreMCInstrInfo() { + TargetRegistry::RegisterMCInstrInfo(TheXCoreTarget, createXCoreMCInstrInfo); +} + +MCSubtargetInfo *createXCoreMCSubtargetInfo(StringRef TT, StringRef CPU, + StringRef FS) { + MCSubtargetInfo *X = new MCSubtargetInfo(); + InitXCoreMCSubtargetInfo(X, TT, CPU, FS); + return X; +} + +extern "C" void LLVMInitializeXCoreMCSubtargetInfo() { + TargetRegistry::RegisterMCSubtargetInfo(TheXCoreTarget, + createXCoreMCSubtargetInfo); +} diff --git a/llvm/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.h b/llvm/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.h new file mode 100644 index 000000000000..3cfc3764a62c --- /dev/null +++ b/llvm/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.h @@ -0,0 +1,40 @@ +//===-- XCoreMCTargetDesc.h - XCore Target Descriptions ---------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file provides XCore specific target descriptions. +// +//===----------------------------------------------------------------------===// + +#ifndef XCOREMCTARGETDESC_H +#define XCOREMCTARGETDESC_H + +namespace llvm { +class MCSubtargetInfo; +class Target; +class StringRef; + +extern Target TheXCoreTarget; + +} // End llvm namespace + +// Defines symbolic names for XCore registers. This defines a mapping from +// register name to register number. +// +#define GET_REGINFO_ENUM +#include "XCoreGenRegisterInfo.inc" + +// Defines symbolic names for the XCore instructions. +// +#define GET_INSTRINFO_ENUM +#include "XCoreGenInstrInfo.inc" + +#define GET_SUBTARGETINFO_ENUM +#include "XCoreGenSubtargetInfo.inc" + +#endif diff --git a/llvm/lib/Target/XCore/Makefile b/llvm/lib/Target/XCore/Makefile index a9d9feef655d..b823c4ed37e9 100644 --- a/llvm/lib/Target/XCore/Makefile +++ b/llvm/lib/Target/XCore/Makefile @@ -17,7 +17,7 @@ BUILT_SOURCES = XCoreGenRegisterInfo.inc XCoreGenInstrInfo.inc \ XCoreGenDAGISel.inc XCoreGenCallingConv.inc \ XCoreGenSubtargetInfo.inc -DIRS = TargetInfo +DIRS = TargetInfo MCTargetDesc include $(LEVEL)/Makefile.common diff --git a/llvm/lib/Target/XCore/XCore.h b/llvm/lib/Target/XCore/XCore.h index ec4ab9112818..b8fb0cac319b 100644 --- a/llvm/lib/Target/XCore/XCore.h +++ b/llvm/lib/Target/XCore/XCore.h @@ -15,6 +15,7 @@ #ifndef TARGET_XCORE_H #define TARGET_XCORE_H +#include "MCTargetDesc/XCoreMCTargetDesc.h" #include "llvm/Target/TargetMachine.h" namespace llvm { @@ -25,19 +26,6 @@ namespace llvm { FunctionPass *createXCoreISelDag(XCoreTargetMachine &TM); - extern Target TheXCoreTarget; - } // end namespace llvm; -// Defines symbolic names for XCore registers. This defines a mapping from -// register name to register number. -// -#define GET_REGINFO_ENUM -#include "XCoreGenRegisterInfo.inc" - -// Defines symbolic names for the XCore instructions. -// -#define GET_INSTRINFO_ENUM -#include "XCoreGenInstrInfo.inc" - #endif diff --git a/llvm/lib/Target/XCore/XCoreInstrInfo.cpp b/llvm/lib/Target/XCore/XCoreInstrInfo.cpp index 693a2fe7a568..f90481f3fbc9 100644 --- a/llvm/lib/Target/XCore/XCoreInstrInfo.cpp +++ b/llvm/lib/Target/XCore/XCoreInstrInfo.cpp @@ -24,7 +24,6 @@ #include "llvm/Support/ErrorHandling.h" #define GET_INSTRINFO_CTOR -#define GET_INSTRINFO_MC_DESC #include "XCoreGenInstrInfo.inc" namespace llvm { @@ -397,13 +396,3 @@ ReverseBranchCondition(SmallVectorImpl &Cond) const { Cond[0].setImm(GetOppositeBranchCondition((XCore::CondCode)Cond[0].getImm())); return false; } - -MCInstrInfo *createXCoreMCInstrInfo() { - MCInstrInfo *X = new MCInstrInfo(); - InitXCoreMCInstrInfo(X); - return X; -} - -extern "C" void LLVMInitializeXCoreMCInstrInfo() { - TargetRegistry::RegisterMCInstrInfo(TheXCoreTarget, createXCoreMCInstrInfo); -} diff --git a/llvm/lib/Target/XCore/XCoreRegisterInfo.cpp b/llvm/lib/Target/XCore/XCoreRegisterInfo.cpp index 0aa7d5fb3e9f..357a4a083582 100644 --- a/llvm/lib/Target/XCore/XCoreRegisterInfo.cpp +++ b/llvm/lib/Target/XCore/XCoreRegisterInfo.cpp @@ -33,7 +33,6 @@ #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" -#define GET_REGINFO_MC_DESC #define GET_REGINFO_TARGET_DESC #include "XCoreGenRegisterInfo.inc" diff --git a/llvm/lib/Target/XCore/XCoreSubtarget.cpp b/llvm/lib/Target/XCore/XCoreSubtarget.cpp index 518136407072..ad069bf138a7 100644 --- a/llvm/lib/Target/XCore/XCoreSubtarget.cpp +++ b/llvm/lib/Target/XCore/XCoreSubtarget.cpp @@ -15,8 +15,6 @@ #include "XCore.h" #include "llvm/Target/TargetRegistry.h" -#define GET_SUBTARGETINFO_ENUM -#define GET_SUBTARGETINFO_MC_DESC #define GET_SUBTARGETINFO_TARGET_DESC #define GET_SUBTARGETINFO_CTOR #include "XCoreGenSubtargetInfo.inc" @@ -28,16 +26,3 @@ XCoreSubtarget::XCoreSubtarget(const std::string &TT, : XCoreGenSubtargetInfo(TT, CPU, FS) { } - - -MCSubtargetInfo *createXCoreMCSubtargetInfo(StringRef TT, StringRef CPU, - StringRef FS) { - MCSubtargetInfo *X = new MCSubtargetInfo(); - InitXCoreMCSubtargetInfo(X, TT, CPU, FS); - return X; -} - -extern "C" void LLVMInitializeXCoreMCSubtargetInfo() { - TargetRegistry::RegisterMCSubtargetInfo(TheXCoreTarget, - createXCoreMCSubtargetInfo); -} diff --git a/llvm/utils/TableGen/InstrInfoEmitter.cpp b/llvm/utils/TableGen/InstrInfoEmitter.cpp index 9c5f945d8c96..b27e49787c11 100644 --- a/llvm/utils/TableGen/InstrInfoEmitter.cpp +++ b/llvm/utils/TableGen/InstrInfoEmitter.cpp @@ -198,8 +198,7 @@ void InstrInfoEmitter::run(raw_ostream &OS) { // Emit all of the MCInstrDesc records in their ENUM ordering. // - OS << "\nstatic const MCInstrDesc " << TargetName - << "Insts[] = {\n"; + OS << "\nMCInstrDesc " << TargetName << "Insts[] = {\n"; const std::vector &NumberedInstructions = Target.getInstructionsByEnumValue(); @@ -235,6 +234,7 @@ void InstrInfoEmitter::run(raw_ostream &OS) { OS << "#undef GET_INSTRINFO_CTOR\n"; OS << "namespace llvm {\n"; + OS << "extern const MCInstrDesc " << TargetName << "Insts[];\n"; OS << ClassName << "::" << ClassName << "(int SO, int DO)\n" << " : TargetInstrInfoImpl(SO, DO) {\n" << " InitMCInstrInfo(" << TargetName << "Insts, " diff --git a/llvm/utils/TableGen/RegisterInfoEmitter.cpp b/llvm/utils/TableGen/RegisterInfoEmitter.cpp index abb862445d19..6ad6b408fd50 100644 --- a/llvm/utils/TableGen/RegisterInfoEmitter.cpp +++ b/llvm/utils/TableGen/RegisterInfoEmitter.cpp @@ -162,16 +162,17 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, OS << getQualifiedName(SR[j]->TheDef) << ", "; OS << "0 };\n"; } + OS << "}\n"; // End of anonymous namespace... - OS << "\n const MCRegisterDesc " << TargetName + OS << "\nMCRegisterDesc " << TargetName << "RegDesc[] = { // Descriptors\n"; - OS << " { \"NOREG\",\t0,\t0,\t0 },\n"; + OS << " { \"NOREG\",\t0,\t0,\t0 },\n"; // Now that register alias and sub-registers sets have been emitted, emit the // register descriptors now. for (unsigned i = 0, e = Regs.size(); i != e; ++i) { const CodeGenRegister &Reg = *Regs[i]; - OS << " { \""; + OS << " { \""; OS << Reg.getName() << "\",\t" << Reg.getName() << "_Overlaps,\t"; if (!Reg.getSubRegs().empty()) OS << Reg.getName() << "_SubRegsSet,\t"; @@ -183,9 +184,7 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, OS << "Empty_SuperRegsSet"; OS << " },\n"; } - OS << " };\n"; // End of register descriptors... - - OS << "}\n\n"; // End of anonymous namespace... + OS << "};\n\n"; // End of register descriptors... // MCRegisterInfo initialization routine. OS << "static inline void Init" << TargetName @@ -545,6 +544,7 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, OS << " &" << getQualifiedName(RegisterClasses[i].TheDef) << "RegClass,\n"; OS << " };\n"; + OS << "}\n"; // End of anonymous namespace... // Emit extra information about registers. const std::string &TargetName = Target.getName(); @@ -569,7 +569,8 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, // Emit SubRegIndex names, skipping 0 const std::vector &SubRegIndices = RegBank.getSubRegIndices(); - OS << "\n const char *const SubRegIndexTable[] = { \""; + OS << "\n static const char *const " << TargetName + << "SubRegIndexTable[] = { \""; for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) { OS << SubRegIndices[i]->getName(); if (i+1 != e) @@ -587,7 +588,7 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, } OS << "\n };\n\n"; } - OS << "}\n\n"; // End of anonymous namespace... + OS << "\n"; std::string ClassName = Target.getName() + "GenRegisterInfo"; @@ -658,11 +659,13 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, OS << " }\n}\n\n"; // Emit the constructor of the class... + OS << "extern const MCRegisterDesc " << TargetName << "RegDesc[];\n"; + OS << ClassName << "::" << ClassName << "()\n" << " : TargetRegisterInfo(" << TargetName << "RegInfoDesc" << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n" - << " SubRegIndexTable) {\n" + << " " << TargetName << "SubRegIndexTable) {\n" << " InitMCRegisterInfo(" << TargetName << "RegDesc, " << Regs.size()+1 << ");\n" << "}\n\n"; diff --git a/llvm/utils/TableGen/SubtargetEmitter.cpp b/llvm/utils/TableGen/SubtargetEmitter.cpp index 4813b42c6245..de0a39c8c0ab 100644 --- a/llvm/utils/TableGen/SubtargetEmitter.cpp +++ b/llvm/utils/TableGen/SubtargetEmitter.cpp @@ -81,8 +81,7 @@ unsigned SubtargetEmitter::FeatureKeyValues(raw_ostream &OS) { // Begin feature table OS << "// Sorted (by key) array of values for CPU features.\n" - << "static const llvm::SubtargetFeatureKV " - << Target << "FeatureKV[] = {\n"; + << "llvm::SubtargetFeatureKV " << Target << "FeatureKV[] = {\n"; // For each feature unsigned NumFeatures = 0; @@ -141,8 +140,7 @@ unsigned SubtargetEmitter::CPUKeyValues(raw_ostream &OS) { // Begin processor table OS << "// Sorted (by key) array of values for CPU subtype.\n" - << "static const llvm::SubtargetFeatureKV " - << Target << "SubTypeKV[] = {\n"; + << "llvm::SubtargetFeatureKV " << Target << "SubTypeKV[] = {\n"; // For each processor for (unsigned i = 0, N = ProcessorList.size(); i < N;) { @@ -329,9 +327,9 @@ void SubtargetEmitter::EmitStageAndOperandCycleData(raw_ostream &OS, OS << "\n// Pipeline forwarding pathes for itineraries \"" << Name << "\"\n" << "namespace " << Name << "Bypass {\n"; - OS << " const unsigned NoBypass = 0;\n"; + OS << " unsigned NoBypass = 0;\n"; for (unsigned j = 0, BPN = BPs.size(); j < BPN; ++j) - OS << " const unsigned " << BPs[j]->getName() + OS << " unsigned " << BPs[j]->getName() << " = 1 << " << j << ";\n"; OS << "}\n"; @@ -339,17 +337,16 @@ void SubtargetEmitter::EmitStageAndOperandCycleData(raw_ostream &OS, } // Begin stages table - std::string StageTable = "\nstatic const llvm::InstrStage " + Target + - "Stages[] = {\n"; + std::string StageTable = "\nllvm::InstrStage " + Target + "Stages[] = {\n"; StageTable += " { 0, 0, 0, llvm::InstrStage::Required }, // No itinerary\n"; // Begin operand cycle table - std::string OperandCycleTable = "static const unsigned " + Target + + std::string OperandCycleTable = "unsigned " + Target + "OperandCycles[] = {\n"; OperandCycleTable += " 0, // No itinerary\n"; // Begin pipeline bypass table - std::string BypassTable = "static const unsigned " + Target + + std::string BypassTable = "unsigned " + Target + "ForwardingPathes[] = {\n"; BypassTable += " 0, // No itinerary\n"; @@ -491,7 +488,7 @@ EmitProcessorData(raw_ostream &OS, // Begin processor itinerary table OS << "\n"; - OS << "static const llvm::InstrItinerary " << Name << "[] = {\n"; + OS << "llvm::InstrItinerary " << Name << "[] = {\n"; // For each itinerary class std::vector &ItinList = *ProcListIter++; @@ -533,7 +530,7 @@ void SubtargetEmitter::EmitProcessorLookup(raw_ostream &OS) { // Begin processor table OS << "\n"; OS << "// Sorted (by key) array of itineraries for CPU subtype.\n" - << "static const llvm::SubtargetInfoKV " + << "llvm::SubtargetInfoKV " << Target << "ProcItinKV[] = {\n"; // For each processor @@ -657,12 +654,18 @@ void SubtargetEmitter::run(raw_ostream &OS) { OS << "#undef GET_SUBTARGETINFO_MC_DESC\n"; OS << "namespace llvm {\n"; +#if 0 + OS << "namespace {\n"; +#endif unsigned NumFeatures = FeatureKeyValues(OS); - OS<<"\n"; + OS << "\n"; unsigned NumProcs = CPUKeyValues(OS); - OS<<"\n"; + OS << "\n"; EmitData(OS); - OS<<"\n"; + OS << "\n"; +#if 0 + OS << "}\n"; +#endif // MCInstrInfo initialization routine. OS << "static inline void Init" << Target @@ -717,6 +720,15 @@ void SubtargetEmitter::run(raw_ostream &OS) { OS << "#undef GET_SUBTARGETINFO_CTOR\n"; OS << "namespace llvm {\n"; + OS << "extern const llvm::SubtargetFeatureKV " << Target << "FeatureKV[];\n"; + OS << "extern const llvm::SubtargetFeatureKV " << Target << "SubTypeKV[];\n"; + if (HasItineraries) { + OS << "extern const llvm::SubtargetInfoKV " << Target << "ProcItinKV[];\n"; + OS << "extern const llvm::InstrStage " << Target << "Stages[];\n"; + OS << "extern const unsigned " << Target << "OperandCycles[];\n"; + OS << "extern const unsigned " << Target << "ForwardingPathes[];\n"; + } + OS << ClassName << "::" << ClassName << "(StringRef TT, StringRef CPU, " << "StringRef FS)\n" << " : TargetSubtargetInfo() {\n"