forked from OSchip/llvm-project
[ARM] Add more pattern matching for f16 <-> f64 conversions
Specifically when the conversion is done in two steps, f16 -> f32 -> f64. For example: %1 = tail call float @llvm.convert.from.fp16.f32(i16 %0) %conv = fpext float %1 to double to: vcvtb.f64.f16 llvm-svn: 232954
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@ -627,6 +627,14 @@ def : Pat<(f16_to_fp GPR:$a),
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def : Pat<(f64 (f16_to_fp GPR:$a)),
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(VCVTBHD (COPY_TO_REGCLASS GPR:$a, SPR))>;
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def : Pat<(f64 (fextend (f16_to_fp GPR:$a))),
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(VCVTBHD (COPY_TO_REGCLASS GPR:$a, SPR))>,
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Requires<[HasFPARMv8, HasDPVFP]>;
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def : Pat<(fp_to_f16 (fround (f64 DPR:$a))),
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(i32 (COPY_TO_REGCLASS (VCVTBDH DPR:$a), GPR))>,
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Requires<[HasFPARMv8, HasDPVFP]>;
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multiclass vcvt_inst<string opc, bits<2> rm,
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SDPatternOperator node = null_frag> {
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let PostEncoderMethod = "", DecoderNamespace = "VFPV8" in {
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@ -0,0 +1,31 @@
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; RUN: llc -mtriple=arm -mattr=+fp-armv8 < %s | \
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; RUN: FileCheck --check-prefix=CHECK --check-prefix=V8 %s
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; RUN: llc -mtriple=arm -mattr=+vfp3,+d16 < %s | \
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; RUN: FileCheck --check-prefix=CHECK --check-prefix=NOV8 %s
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declare float @llvm.convert.from.fp16.f32(i16) nounwind readnone
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declare i16 @llvm.convert.to.fp16.f32(float) nounwind readnone
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define void @vcvt_f64_f16(i16* %x, double* %y) nounwind {
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entry:
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; CHECK-LABEL: vcvt_f64_f16
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%0 = load i16, i16* %x, align 2
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%1 = tail call float @llvm.convert.from.fp16.f32(i16 %0)
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%conv = fpext float %1 to double
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; CHECK-V8: vcvtb.f64.f16
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; CHECK-NOV8-NOT: vcvtb.f64.f16
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store double %conv, double* %y, align 8
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ret void
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}
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define void @vcvt_f16_f64(i16* %x, double* %y) nounwind {
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entry:
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; CHECK-LABEL: vcvt_f16_f64
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%0 = load double, double* %y, align 8
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%conv = fptrunc double %0 to float
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; CHECK-V8: vcvtb.f16.f64
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; CHECK-NOV8-NOT: vcvtb.f16.f64
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%1 = tail call i16 @llvm.convert.to.fp16.f32(float %conv)
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store i16 %1, i16* %x, align 2
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ret void
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}
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