forked from OSchip/llvm-project
Update bitcode reader and writer to handle multiple return values.
Take 2. llvm-svn: 47583
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b7e656b177
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bbfd874cb4
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@ -1337,17 +1337,24 @@ bool BitcodeReader::ParseFunctionBody(Function *F) {
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}
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case bitc::FUNC_CODE_INST_RET: // RET: [opty,opval<optional>]
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if (Record.empty()) {
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I = new ReturnInst();
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break;
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} else {
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unsigned OpNum = 0;
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Value *Op;
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if (getValueTypePair(Record, OpNum, NextValueNo, Op) ||
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OpNum != Record.size())
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return Error("Invalid RET record");
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I = new ReturnInst(Op);
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break;
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{
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unsigned Size = Record.size();
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if (Size == 0) {
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I = new ReturnInst();
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break;
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} else {
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unsigned OpNum = 0;
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std::vector<Value *> Vs;
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do {
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Value *Op = NULL;
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if (getValueTypePair(Record, OpNum, NextValueNo, Op))
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return Error("Invalid RET record");
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Vs.push_back(Op);
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} while(OpNum != Record.size());
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I = new ReturnInst(Vs);
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break;
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}
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}
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case bitc::FUNC_CODE_INST_BR: { // BR: [bb#, bb#, opval] or [bb#]
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if (Record.size() != 1 && Record.size() != 3)
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@ -747,15 +747,24 @@ static void WriteInstruction(const Instruction &I, unsigned InstID,
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case Instruction::GetResult:
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Code = bitc::FUNC_CODE_INST_GETRESULT;
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PushValueAndType(I.getOperand(0), InstID, Vals, VE);
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Vals.push_back(Log2_32(cast<GetResultInst>(I).getIndex())+1);
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Vals.push_back(cast<GetResultInst>(I).getIndex());
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break;
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case Instruction::Ret:
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Code = bitc::FUNC_CODE_INST_RET;
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if (!I.getNumOperands())
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AbbrevToUse = FUNCTION_INST_RET_VOID_ABBREV;
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else if (!PushValueAndType(I.getOperand(0), InstID, Vals, VE))
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AbbrevToUse = FUNCTION_INST_RET_VAL_ABBREV;
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{
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Code = bitc::FUNC_CODE_INST_RET;
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unsigned NumOperands = I.getNumOperands();
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// printf ("dpatel write %d\n", NumOperands);
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if (NumOperands == 0)
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AbbrevToUse = FUNCTION_INST_RET_VOID_ABBREV;
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else if (NumOperands == 1) {
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if (!PushValueAndType(I.getOperand(0), InstID, Vals, VE))
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AbbrevToUse = FUNCTION_INST_RET_VAL_ABBREV;
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} else {
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for (unsigned i = 0, e = NumOperands; i != e; ++i)
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PushValueAndType(I.getOperand(i), InstID, Vals, VE);
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}
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}
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break;
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case Instruction::Br:
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Code = bitc::FUNC_CODE_INST_BR;
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@ -1,4 +1,4 @@
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; RUN: llvm-as < %s -disable-output
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; RUN: llvm-as < %s | opt -verify | llvm-dis | llvm-as -disable-output
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define {i32, i8} @foo(i32 %p) {
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ret i32 1, i8 2
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