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Fix more register allocation sensitive tests. 

llvm-svn: 134667
This commit is contained in:
Jakob Stoklund Olesen 2011-07-08 00:24:06 +00:00
parent b138c44276
commit bbe2a5cfff
3 changed files with 8 additions and 8 deletions
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4
llvm/test/CodeGen/Thumb2/2010-06-14-NEONCoalescer.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -O3 -relocation-model=pic -mattr=+thumb2 -mcpu=cortex-a8 | FileCheck %s ; RUN: llc < %s -O3 -relocation-model=pic -mattr=+thumb2 -mcpu=cortex-a8 -disable-branch-fold | FileCheck %s
target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32" target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32"
target triple = "thumbv7-apple-darwin10" target triple = "thumbv7-apple-darwin10"
@ -26,7 +26,7 @@ entry:
; CHECK: vldr.64 [[LDR:d.*]], ; CHECK: vldr.64 [[LDR:d.*]],
; CHECK: LPC0_0: ; CHECK: LPC0_0:
; CHECK: vadd.f64 [[ADD:d.*]], [[LDR]], [[LDR]] ; CHECK: vadd.f64 [[ADD:d.*]], [[LDR]], [[LDR]]
; CHECK: vmov.f64 [[LDR]] ; CHECK-NOT: vmov.f64 [[ADD]]
%5 = fadd <2 x double> %3, %3 ; <<2 x double>> [#uses=2] %5 = fadd <2 x double> %3, %3 ; <<2 x double>> [#uses=2]
%6 = fadd <2 x double> %4, %4 ; <<2 x double>> [#uses=2] %6 = fadd <2 x double> %4, %4 ; <<2 x double>> [#uses=2]
%tmp7 = extractelement <2 x double> %5, i32 0 ; <double> [#uses=1] %tmp7 = extractelement <2 x double> %5, i32 0 ; <double> [#uses=1]

8
llvm/test/CodeGen/Thumb2/lsr-deficiency.ll
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@ -13,16 +13,16 @@
define void @t() nounwind optsize { define void @t() nounwind optsize {
; CHECK: t: ; CHECK: t:
; CHECK: mov.w r2, #1000 ; CHECK: mov{{.*}}, #1000
entry: entry:
%.pre = load i32* @G, align 4 ; <i32> [#uses=1] %.pre = load i32* @G, align 4 ; <i32> [#uses=1]
br label %bb br label %bb
bb: ; preds = %bb, %entry bb: ; preds = %bb, %entry
; CHECK: LBB0_1: ; CHECK: LBB0_1:
; CHECK: cmp r2, #0 ; CHECK: cmp [[R2:r[0-9]+]], #0
; CHECK: sub{{(.w)?}} [[REGISTER:(r[0-9]+)|(lr)]], r2, #1 ; CHECK: sub{{(.w)?}} [[REGISTER:(r[0-9]+)|(lr)]], [[R2]], #1
; CHECK: mov r2, [[REGISTER]] ; CHECK: mov [[R2]], [[REGISTER]]
%0 = phi i32 [ %.pre, %entry ], [ %3, %bb ] ; <i32> [#uses=1] %0 = phi i32 [ %.pre, %entry ], [ %3, %bb ] ; <i32> [#uses=1]
%indvar = phi i32 [ 0, %entry ], [ %indvar.next, %bb ] ; <i32> [#uses=2] %indvar = phi i32 [ 0, %entry ], [ %indvar.next, %bb ] ; <i32> [#uses=2]

4
llvm/test/CodeGen/Thumb2/machine-licm.ll
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@ -52,8 +52,8 @@ return: ; preds = %bb, %entry
define void @t2(i8* %ptr1, i8* %ptr2) nounwind { define void @t2(i8* %ptr1, i8* %ptr2) nounwind {
entry: entry:
; CHECK: t2: ; CHECK: t2:
; CHECK: mov.w r3, #1065353216 ; CHECK: mov.w [[R3:r[0-9]+]], #1065353216
; CHECK: vdup.32 q{{.*}}, r3 ; CHECK: vdup.32 q{{.*}}, [[R3]]
br i1 undef, label %bb1, label %bb2 br i1 undef, label %bb1, label %bb2
bb1: bb1: