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Make some ugly hacks for inline asm operands which name a specific register a bit more thorough. PR13196. 

llvm-svn: 159176
This commit is contained in:
Eli Friedman 2012-06-25 23:42:33 +00:00
parent 31b54a5379
commit bbcd09cc00
2 changed files with 21 additions and 5 deletions
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7
llvm/lib/Target/X86/X86ISelLowering.cpp
View File

@ -16030,12 +16030,15 @@ X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
// wrong class. This can happen with constraints like {xmm0} where the
// target independent register mapper will just pick the first match it can
// find, ignoring the required type.
if (VT == MVT::f32)
if (VT == MVT::f32 || VT == MVT::i32)
Res.second = &X86::FR32RegClass;
else if (VT == MVT::f64)
else if (VT == MVT::f64 || VT == MVT::i64)
Res.second = &X86::FR64RegClass;
else if (X86::VR128RegClass.hasType(VT))
Res.second = &X86::VR128RegClass;
else if (X86::VR256RegClass.hasType(VT))
Res.second = &X86::VR256RegClass;
}
return Res;

19
llvm/test/CodeGen/X86/2008-08-25-AsmRegTypeMismatch.ll → llvm/test/CodeGen/X86/asm-reg-type-mismatch.ll
View File

@ -1,5 +1,4 @@
; RUN: llc < %s -mcpu=core2 | grep xorps | count 2
; RUN: llc < %s -mcpu=core2 | not grep movap
; RUN: llc < %s -mcpu=core2 | FileCheck %s
; PR2715
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
@ -11,8 +10,22 @@ target triple = "x86_64-unknown-linux-gnu"
%struct.nsXPTCVariant = type { %struct.nsXPTCMiniVariant, i8*, %struct.nsXPTType, i8 }
%struct.nsXPTType = type { %struct.XPTTypeDescriptorPrefix }
define i32 @XPTC_InvokeByIndex(%struct.nsISupports* %that, i32 %methodIndex, i32 %paramCount, %struct.nsXPTCVariant* %params) nounwind {
define i32 @test1(%struct.nsISupports* %that, i32 %methodIndex, i32 %paramCount, %struct.nsXPTCVariant* %params) nounwind {
entry:
call void asm sideeffect "", "{xmm0},{xmm1},{xmm2},{xmm3},{xmm4},{xmm5},{xmm6},{xmm7},~{dirflag},~{fpsr},~{flags}"( double undef, double undef, double undef, double 1.0, double undef, double 0.0, double undef, double 0.0 ) nounwind
ret i32 0
; CHECK: test1
; CHECK-NOT: movap
; CHECK: xorps
; CHECK: xorps
; CHECK-NOT: movap
}
define i64 @test2() nounwind {
entry:
%0 = tail call i64 asm sideeffect "movq $1, $0", "={xmm7},*m,~{dirflag},~{fpsr},~{flags}"(i64* null) nounwind
ret i64 %0
; CHECK: test2
; CHECK: movq {{.*}}, %xmm7
; CHECK: movd %xmm7, %rax
}