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Fix up a comment: besides the >80col lines, the operation for this 

addressing mode is encoded in the second operand, not the third.

llvm-svn: 74641
This commit is contained in:
Bob Wilson 2009-07-01 21:22:45 +00:00
parent 1cf085d558
commit bbbf805049
1 changed files with 6 additions and 6 deletions
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12
llvm/lib/Target/ARM/ARMAddressingModes.h
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@ -459,13 +459,13 @@ namespace ARM_AM {
//
// addrmode5 := reg +/- imm8*4
//
// The first operand is always a Reg. The third field encodes the operation
// in bit 8, the immediate in bits 0-7.
// The first operand is always a Reg. The second operand encodes the
// operation in bit 8 and the immediate in bits 0-7.
//
// This can also be used for FP load/store multiple ops. The third field encodes
// writeback mode in bit 8, the number of registers (or 2 times the number of
// registers for DPR ops) in bits 0-7. In addition, bit 9-11 encodes one of the
// following two sub-modes:
// This is also used for FP load/store multiple ops. The second operand
// encodes the writeback mode in bit 8 and the number of registers (or 2
// times the number of registers for DPR ops) in bits 0-7. In addition,
// bits 9-11 encode one of the following two sub-modes:
//
// IA - Increment after
// DB - Decrement before