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[AArch64] Allocate the modified and used regs only once per function. 

llvm-svn: 259510
This commit is contained in:
Chad Rosier 2016-02-02 15:02:30 +00:00
parent 8e18fe6e54
commit bba881ef3d
1 changed files with 17 additions and 12 deletions
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29
llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
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@ -88,6 +88,9 @@ struct AArch64LoadStoreOpt : public MachineFunctionPass {
const TargetRegisterInfo *TRI;
const AArch64Subtarget *Subtarget;
// Track which registers have been modified and used.
BitVector ModifiedRegs, UsedRegs;
// Scan the instructions looking for a load/store that can be combined
// with the current instruction into a load/store pair.
// Return the matching instruction if one is found, else MBB->end().
@ -1015,9 +1018,8 @@ bool AArch64LoadStoreOpt::findMatchingStore(
// Track which registers have been modified and used between the first insn
// and the second insn.
BitVector ModifiedRegs, UsedRegs;
ModifiedRegs.resize(TRI->getNumRegs());
UsedRegs.resize(TRI->getNumRegs());
ModifiedRegs.reset();
UsedRegs.reset();
for (unsigned Count = 0; MBBI != E && Count < Limit;) {
--MBBI;
@ -1096,9 +1098,8 @@ AArch64LoadStoreOpt::findMatchingInsn(MachineBasicBlock::iterator I,
// Track which registers have been modified and used between the first insn
// (inclusive) and the second insn.
BitVector ModifiedRegs, UsedRegs;
ModifiedRegs.resize(TRI->getNumRegs());
UsedRegs.resize(TRI->getNumRegs());
ModifiedRegs.reset();
UsedRegs.reset();
// Remember any instructions that read/write memory between FirstMI and MI.
SmallVector<MachineInstr *, 4> MemInsns;
@ -1378,9 +1379,8 @@ MachineBasicBlock::iterator AArch64LoadStoreOpt::findMatchingUpdateInsnForward(
// Track which registers have been modified and used between the first insn
// (inclusive) and the second insn.
BitVector ModifiedRegs, UsedRegs;
ModifiedRegs.resize(TRI->getNumRegs());
UsedRegs.resize(TRI->getNumRegs());
ModifiedRegs.reset();
UsedRegs.reset();
++MBBI;
for (; MBBI != E; ++MBBI) {
MachineInstr *MI = MBBI;
@ -1428,9 +1428,8 @@ MachineBasicBlock::iterator AArch64LoadStoreOpt::findMatchingUpdateInsnBackward(
// Track which registers have been modified and used between the first insn
// (inclusive) and the second insn.
BitVector ModifiedRegs, UsedRegs;
ModifiedRegs.resize(TRI->getNumRegs());
UsedRegs.resize(TRI->getNumRegs());
ModifiedRegs.reset();
UsedRegs.reset();
--MBBI;
for (; MBBI != B; --MBBI) {
MachineInstr *MI = MBBI;
@ -1784,6 +1783,12 @@ bool AArch64LoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) {
TII = static_cast<const AArch64InstrInfo *>(Subtarget->getInstrInfo());
TRI = Subtarget->getRegisterInfo();
// Resize the modified and used register bitfield trackers. We do this once
// per function and then clear the bitfield each time we optimize a load or
// store.
ModifiedRegs.resize(TRI->getNumRegs());
UsedRegs.resize(TRI->getNumRegs());
bool Modified = false;
bool enableNarrowLdOpt = enableNarrowLdMerge(Fn);
for (auto &MBB : Fn)